void audio_set_clk(unsigned freq, unsigned fs_config)
{
int i;
struct clk *clk;
int xtal = 0;
int (*audio_clock_config)[2];
// if (fs_config == AUDIO_CLK_256FS) {
if(1){
int index=0;
switch(freq)
{
case AUDIO_CLK_FREQ_192:
index=4;
break;
case AUDIO_CLK_FREQ_96:
index=3;
break;
case AUDIO_CLK_FREQ_48:
index=2;
break;
case AUDIO_CLK_FREQ_441:
index=1;
break;
case AUDIO_CLK_FREQ_32:
index=0;
break;
case AUDIO_CLK_FREQ_8:
index = 5;
break;
case AUDIO_CLK_FREQ_11:
index = 6;
break;
case AUDIO_CLK_FREQ_12:
index = 7;
break;
case AUDIO_CLK_FREQ_16:
index = 8;
break;
case AUDIO_CLK_FREQ_22:
index = 9;
break;
case AUDIO_CLK_FREQ_24:
index = 10;
break;
default:
index=0;
break;
};
// get system crystal freq
clk=clk_get_sys("clk_xtal", NULL);
if(!clk)
{
printk(KERN_ERR "can't find clk %s for AUDIO PLL SETTING!\n\n","clk_xtal");
//return -1;
}
else
{
xtal=clk_get_rate(clk);
xtal=xtal/1000000;
if(xtal>=24 && xtal <=25)/*current only support 24,25*/
{
xtal-=24;
}
else
{
printk(KERN_WARNING "UNsupport xtal setting for audio xtal=%d,default to 24M\n",xtal);
xtal=0;
}
}
audio_clock_config = audio_clock_config_table[xtal];
#ifdef CONFIG_SND_AML_M3
if (((clk_get_rate(clk)==24000000)&&(get_ddr_pll_clk()==516000000)&&(index=2))) // 48k
{
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(1 << 8)); // audio clock off
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, READ_MPEG_REG(HHI_AUD_PLL_CNTL) | (1 << 15)); // audio pll off
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 4, 9, 3); // select ddr
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 42-1, 0, 8); // 516/42
WRITE_MPEG_REG_BITS(AIU_CODEC_ADC_LRCLK_CTRL, 64-1, 0, 12);//set codec adc ratio---lrclk
WRITE_MPEG_REG_BITS(AIU_CODEC_DAC_LRCLK_CTRL, 64-1, 0, 12);//set codec dac ratio---lrclk
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1<<23));// gate audac_clkpi
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1 << 8));
printk(KERN_INFO "audio 48k clock from ddr pll %dM\n", 516);
return;
}
else if (((clk_get_rate(clk)==24000000)&&(get_ddr_pll_clk()==508000000)&&(index=1))) // 44.1k
{
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(1 << 8)); // audio clock off
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, READ_MPEG_REG(HHI_AUD_PLL_CNTL) | (1 << 15)); // audio pll off
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 4, 9, 3); // select ddr
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 45-1, 0, 8); // 508/45
WRITE_MPEG_REG_BITS(AIU_CODEC_ADC_LRCLK_CTRL, 64-1, 0, 12);//set codec adc ratio---lrclk
WRITE_MPEG_REG_BITS(AIU_CODEC_DAC_LRCLK_CTRL, 64-1, 0, 12);//set codec dac ratio---lrclk
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1<<23));// gate audac_clkpi
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1 << 8));
printk(KERN_INFO "audio 44.1k clock from ddr pll %dM\n", 508);
return;
}
else if (((clk_get_rate(clk)==24000000)&&(get_ddr_pll_clk()==486000000)&&(index=1))) // 44.1k
{
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(1 << 8)); // audio clock off
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, READ_MPEG_REG(HHI_AUD_PLL_CNTL) | (1 << 15)); // audio pll off
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 4, 9, 3); // select ddr
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 43-1, 0, 8); // 486/42
WRITE_MPEG_REG_BITS(AIU_CODEC_ADC_LRCLK_CTRL, 64-1, 0, 12);//set codec adc ratio---lrclk
WRITE_MPEG_REG_BITS(AIU_CODEC_DAC_LRCLK_CTRL, 64-1, 0, 12);//set codec dac ratio---lrclk
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1<<23));// gate audac_clkpi
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1 << 8));
printk(KERN_INFO "audio 44.1k clock from ddr pll %dM\n", 486);
return;
}
else if (((clk_get_rate(clk)==24000000)&&(get_ddr_pll_clk()==474000000)&&(index=1))) // 44.1k
{
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(1 << 8)); // audio clock off
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, READ_MPEG_REG(HHI_AUD_PLL_CNTL) | (1 << 15)); // audio pll off
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 4, 9, 3); // select ddr
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 42-1, 0, 8); // 474/42
WRITE_MPEG_REG_BITS(AIU_CODEC_ADC_LRCLK_CTRL, 64-1, 0, 12);//set codec adc ratio---lrclk
WRITE_MPEG_REG_BITS(AIU_CODEC_DAC_LRCLK_CTRL, 64-1, 0, 12);//set codec dac ratio---lrclk
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1<<23));// gate audac_clkpi
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1 << 8));
printk(KERN_INFO "audio 44.1k clock from ddr pll %dM\n", 474);
return;
}
#endif
// gate the clock off
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(1 << 8));
//#ifdef CONFIG_SND_AML_M3
#ifdef CONFIG_ARCH_MESON3
WRITE_MPEG_REG(HHI_AUD_PLL_CNTL2, 0x065e31ff);
WRITE_MPEG_REG(HHI_AUD_PLL_CNTL3, 0x9649a941);
// select Audio PLL as MCLK source
//WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(1 << 9));
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 0, 9, 3);
//WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 25-1, 0, 8);
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 13-1, 0, 8);
#endif
// Put the PLL to sleep
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, READ_MPEG_REG(HHI_AUD_PLL_CNTL) | (1 << 15));//found
//#ifdef CONFIG_SND_AML_M3
#ifdef CONFIG_ARCH_MESON3
WRITE_MPEG_REG_BITS(AIU_CODEC_ADC_LRCLK_CTRL, 64-1, 0, 12);//set codec adc ratio---lrclk
WRITE_MPEG_REG_BITS(AIU_CODEC_DAC_LRCLK_CTRL, 64-1, 0, 12);//set codec dac ratio---lrclk
#endif
// Bring out of reset but keep bypassed to allow to stablize
//Wr( HHI_AUD_PLL_CNTL, (1 << 15) | (0 << 14) | (hiu_reg & 0x3FFF) );
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, (1 << 15) | (audio_clock_config[index][0] & 0x7FFF) );//found
// Set the XD value
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, (READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(0xff << 0)) | audio_clock_config[index][1]);//found
// delay 5uS
//udelay(5);
for (i = 0; i < 500000; i++) ;
// Bring the PLL out of sleep
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, READ_MPEG_REG(HHI_AUD_PLL_CNTL) & ~(1 << 15));//found
// gate the clock on
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1 << 8));//found
#if ((defined CONFIG_SND_AML_M1) || (defined CONFIG_SND_AML_M2)||(defined CONFIG_SND_AML_M3))
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) |(1<<23));// gate audac_clkpi
#endif
// delay 2uS
//udelay(2);
for (i = 0; i < 200000; i++) ;
} else if (fs_config == AUDIO_CLK_384FS) {
}
}
extern unsigned int get_ddr_pll_clk(void);
void audio_set_clk(unsigned freq, unsigned fs_config)
{
int i;
int xtal = 0;
int (*audio_clock_config)[2];
// if (fs_config == AUDIO_CLK_256FS) {
if(1){
int index=0;
switch(freq)
{
case AUDIO_CLK_FREQ_192:
index=4;
break;
case AUDIO_CLK_FREQ_96:
index=3;
break;
case AUDIO_CLK_FREQ_48:
index=2;
break;
case AUDIO_CLK_FREQ_441:
index=1;
break;
case AUDIO_CLK_FREQ_32:
index=0;
break;
case AUDIO_CLK_FREQ_8:
index = 5;
break;
case AUDIO_CLK_FREQ_11:
index = 6;
break;
case AUDIO_CLK_FREQ_12:
index = 7;
break;
case AUDIO_CLK_FREQ_16:
index = 8;
break;
case AUDIO_CLK_FREQ_22:
index = 9;
break;
case AUDIO_CLK_FREQ_24:
index = 10;
break;
default:
index=0;
break;
};
#if MESON_CPU_TYPE < MESON_CPU_TYPE_MESON6
// get system crystal freq
clk=clk_get_sys("clk_xtal", NULL);
if(!clk)
{
printk(KERN_ERR "can't find clk %s for AUDIO PLL SETTING!\n\n","clk_xtal");
//return -1;
}
else
{
xtal=clk_get_rate(clk);
xtal=xtal/1000000;
if(xtal>=24 && xtal <=25)/*current only support 24,25*/
{
xtal-=24;
}
else
{
printk(KERN_WARNING "UNsupport xtal setting for audio xtal=%d,default to 24M\n",xtal);
xtal=0;
}
}
audio_clock_config = audio_clock_config_table[xtal];
#endif
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
if (fs_config == AUDIO_CLK_256FS) {
// divide 256
xtal = 0;
}
else if (fs_config == AUDIO_CLK_384FS) {
// divide 384
xtal = 1;
}
audio_clock_config = audio_clock_config_table[xtal];
#endif
#ifdef CONFIG_SND_AML_M3
if (((clk_get_rate(clk)==24000000)&&(get_ddr_pll_clk()==516000000)&&(index=2))) // 48k
{
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(1 << 8)); // audio clock off
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, READ_MPEG_REG(HHI_AUD_PLL_CNTL) | (1 << 15)); // audio pll off
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 4, 9, 3); // select ddr
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 42-1, 0, 8); // 516/42
WRITE_MPEG_REG_BITS(AIU_CODEC_ADC_LRCLK_CTRL, 64-1, 0, 12);//set codec adc ratio---lrclk
WRITE_MPEG_REG_BITS(AIU_CODEC_DAC_LRCLK_CTRL, 64-1, 0, 12);//set codec dac ratio---lrclk
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1<<23));// gate audac_clkpi
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1 << 8));
printk(KERN_INFO "audio 48k clock from ddr pll %dM\n", 516);
return;
}
else if (((clk_get_rate(clk)==24000000)&&(get_ddr_pll_clk()==508000000)&&(index=1))) // 44.1k
{
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(1 << 8)); // audio clock off
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, READ_MPEG_REG(HHI_AUD_PLL_CNTL) | (1 << 15)); // audio pll off
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 4, 9, 3); // select ddr
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 45-1, 0, 8); // 508/45
WRITE_MPEG_REG_BITS(AIU_CODEC_ADC_LRCLK_CTRL, 64-1, 0, 12);//set codec adc ratio---lrclk
WRITE_MPEG_REG_BITS(AIU_CODEC_DAC_LRCLK_CTRL, 64-1, 0, 12);//set codec dac ratio---lrclk
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1<<23));// gate audac_clkpi
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1 << 8));
printk(KERN_INFO "audio 44.1k clock from ddr pll %dM\n", 508);
return;
}
else if (((clk_get_rate(clk)==24000000)&&(get_ddr_pll_clk()==486000000)&&(index=1))) // 44.1k
{
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(1 << 8)); // audio clock off
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, READ_MPEG_REG(HHI_AUD_PLL_CNTL) | (1 << 15)); // audio pll off
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 4, 9, 3); // select ddr
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 43-1, 0, 8); // 486/42
WRITE_MPEG_REG_BITS(AIU_CODEC_ADC_LRCLK_CTRL, 64-1, 0, 12);//set codec adc ratio---lrclk
WRITE_MPEG_REG_BITS(AIU_CODEC_DAC_LRCLK_CTRL, 64-1, 0, 12);//set codec dac ratio---lrclk
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1<<23));// gate audac_clkpi
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1 << 8));
printk(KERN_INFO "audio 44.1k clock from ddr pll %dM\n", 486);
return;
}
else if (((clk_get_rate(clk)==24000000)&&(get_ddr_pll_clk()==474000000)&&(index=1))) // 44.1k
{
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(1 << 8)); // audio clock off
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, READ_MPEG_REG(HHI_AUD_PLL_CNTL) | (1 << 15)); // audio pll off
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 4, 9, 3); // select ddr
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 42-1, 0, 8); // 474/42
WRITE_MPEG_REG_BITS(AIU_CODEC_ADC_LRCLK_CTRL, 64-1, 0, 12);//set codec adc ratio---lrclk
WRITE_MPEG_REG_BITS(AIU_CODEC_DAC_LRCLK_CTRL, 64-1, 0, 12);//set codec dac ratio---lrclk
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1<<23));// gate audac_clkpi
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1 << 8));
printk(KERN_INFO "audio 44.1k clock from ddr pll %dM\n", 474);
return;
}
#endif
// gate the clock off
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(1 << 8));
//#ifdef CONFIG_SND_AML_M3
#ifdef CONFIG_ARCH_MESON3
WRITE_MPEG_REG(HHI_AUD_PLL_CNTL2, 0x065e31ff);
WRITE_MPEG_REG(HHI_AUD_PLL_CNTL3, 0x9649a941);
// select Audio PLL as MCLK source
//WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(1 << 9));
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 0, 9, 3);
//WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 25-1, 0, 8);
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 13-1, 0, 8);
#endif
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
WRITE_MPEG_REG(HHI_MPLL_CNTL3, 0x26e1250);
#endif
#if MESON_CPU_TYPE < MESON_CPU_TYPE_MESON6
// Put the PLL to sleep
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, READ_MPEG_REG(HHI_AUD_PLL_CNTL) | (1 << 15));//found
//#ifdef CONFIG_SND_AML_M3
#if MESON_CPU_TYPE <= MESON_CPU_TYPE_MESON3
WRITE_MPEG_REG_BITS(AIU_CODEC_ADC_LRCLK_CTRL, 64-1, 0, 12);//set codec adc ratio---lrclk
WRITE_MPEG_REG_BITS(AIU_CODEC_DAC_LRCLK_CTRL, 64-1, 0, 12);//set codec dac ratio---lrclk
#endif
// Bring out of reset but keep bypassed to allow to stablize
//Wr( HHI_AUD_PLL_CNTL, (1 << 15) | (0 << 14) | (hiu_reg & 0x3FFF) );
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, (1 << 15) | (audio_clock_config[index][0] & 0x7FFF) );//found
// Set the XD value
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, (READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(0xff << 0)) | audio_clock_config[index][1]);//found
// delay 5uS
//udelay(5);
for (i = 0; i < 500000; i++) ;
// Bring the PLL out of sleep
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, READ_MPEG_REG(HHI_AUD_PLL_CNTL) & ~(1 << 15));//found
// gate the clock on
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1 << 8));//found
#if MESON_CPU_TYPE <= MESON_CPU_TYPE_MESON3
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) |(1<<23));// gate audac_clkpi
#endif
#else // endif CONFIG_ARCH_MESON6
WRITE_MPEG_REG(AIU_CLK_CTRL_MORE, 0);
WRITE_MPEG_REG_BITS(AIU_CODEC_ADC_LRCLK_CTRL, 64-1, 0, 12);//set codec adc ratio---lrclk
WRITE_MPEG_REG_BITS(AIU_CODEC_DAC_LRCLK_CTRL, 64-1, 0, 12);//set codec dac ratio---lrclk
// Select Multi-Phase PLL2 as clock source
WRITE_MPEG_REG_BITS( HHI_AUD_CLK_CNTL, 3, 9, 3);
// Configure Multi-Phase PLL2
WRITE_MPEG_REG(HHI_MPLL_CNTL9, audio_clock_config[index][0]);
// Set the XD value
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, audio_clock_config[index][1], 0, 8);
// delay 5uS
//udelay(5);
for (i = 0; i < 500000; i++) ;
// gate the clock on
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1 << 8));
#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6TV
//Audio DAC Clock enable
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) |(1<<23));
/* ADC clock configuration */
// Disable mclk
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL2, 0, 8, 1);
// Select clk source, 0=ddr_pll; 1=Multi-Phase PLL0; 2=Multi-Phase PLL1; 3=Multi-Phase PLL2.
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL2, 3, 9, 2);
// Set pll over mclk ratio
//we want 256fs ADC MLCK,so for over clock mode,divide more 2 than I2S DAC CLOCK
#if OVERCLOCK == 0
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL2, audio_clock_config[index][1], 0, 8);
#else
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL2, (audio_clock_config[index][1]+1)*2-1, 0, 8);
#endif
// Set mclk over sclk ratio
WRITE_MPEG_REG_BITS(AIU_CLK_CTRL_MORE, 4-1, 8, 6);
// Set sclk over lrclk ratio
WRITE_MPEG_REG_BITS(AIU_CODEC_ADC_LRCLK_CTRL, 64-1, 0, 12);
// Enable sclk
WRITE_MPEG_REG_BITS(AIU_CLK_CTRL_MORE, 1, 14, 1);
// Enable mclk
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL2, 1, 8, 1);
#endif
#endif // endif CONFIG_ARCH_MESON6
// delay 2uS
//udelay(2);
for (i = 0; i < 200000; i++) ;
} else if (fs_config == AUDIO_CLK_384FS) {
}
