/** Interrupt driven FIFO fill function */
static int uarte_nrfx_fifo_fill(struct device *dev,
const u8_t *tx_data,
int len)
{
NRF_UARTE_Type *uarte = get_uarte_instance(dev);
struct uarte_nrfx_data *data = get_dev_data(dev);
const struct uarte_nrfx_config *config = get_dev_config(dev);
if (len > config->tx_buff_size) {
len = config->tx_buff_size;
}
nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_ENDTX);
/* Copy data to RAM buffer for EasyDMA transfer */
for (int i = 0; i < len; i++) {
data->tx_buffer[i] = tx_data[i];
}
nrf_uarte_tx_buffer_set(uarte, data->tx_buffer, len);
nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_STARTTX);
return len;
}
static void prepare_for_transfer(struct device *dev)
{
struct spi_nrfx_data *dev_data = get_dev_data(dev);
const struct spi_nrfx_config *dev_config = get_dev_config(dev);
struct spi_context *ctx = &dev_data->ctx;
int status;
size_t buf_len = spi_context_longest_current_buf(ctx);
if (buf_len > 0) {
nrfx_err_t result;
if (buf_len > dev_config->max_buf_len) {
buf_len = dev_config->max_buf_len;
}
result = nrfx_spis_buffers_set(
&dev_config->spis,
ctx->tx_buf,
spi_context_tx_buf_on(ctx) ? buf_len : 0,
ctx->rx_buf,
spi_context_rx_buf_on(ctx) ? buf_len : 0);
if (result == NRFX_SUCCESS) {
return;
}
/* Cannot prepare for transfer. */
status = -EIO;
} else {
/* Zero-length buffer provided. */
status = 0;
}
spi_context_complete(ctx, status);
}
static int configure(struct device *dev,
const struct spi_config *spi_cfg)
{
struct spi_context *ctx = &get_dev_data(dev)->ctx;
if (spi_context_configured(ctx, spi_cfg)) {
/* Already configured. No need to do it again. */
return 0;
}
if (SPI_OP_MODE_GET(spi_cfg->operation) == SPI_OP_MODE_MASTER) {
LOG_ERR("Master mode is not supported on %s",
dev->config->name);
return -EINVAL;
}
if (spi_cfg->operation & SPI_MODE_LOOP) {
LOG_ERR("Loopback mode is not supported");
return -EINVAL;
}
if ((spi_cfg->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
LOG_ERR("Only single line mode is supported");
return -EINVAL;
}
if (SPI_WORD_SIZE_GET(spi_cfg->operation) != 8) {
LOG_ERR("Word sizes other than 8 bits"
" are not supported");
return -EINVAL;
}
if (spi_cfg->cs) {
LOG_ERR("CS control via GPIO is not supported");
return -EINVAL;
}
ctx->config = spi_cfg;
nrf_spis_configure(get_dev_config(dev)->spis.p_reg,
get_nrf_spis_mode(spi_cfg->operation),
get_nrf_spis_bit_order(spi_cfg->operation));
return 0;
}
static int init_spis(struct device *dev, const nrfx_spis_config_t *config)
{
/* This sets only default values of frequency, mode and bit order.
* The proper ones are set in configure() when a transfer is started.
*/
nrfx_err_t result = nrfx_spis_init(&get_dev_config(dev)->spis,
config,
event_handler,
dev);
if (result != NRFX_SUCCESS) {
LOG_ERR("Failed to initialize device: %s",
dev->config->name);
return -EBUSY;
}
spi_context_unlock_unconditionally(&get_dev_data(dev)->ctx);
return 0;
}
static inline NRF_UARTE_Type *get_uarte_instance(struct device *dev)
{
const struct uarte_nrfx_config *config = get_dev_config(dev);
return config->uarte_regs;
}
