int intel_configure_dsi_pll(struct intel_dsi *intel_dsi,
		struct drm_display_mode *mode)
{
	struct drm_i915_private *dev_priv =
			intel_dsi->base.base.dev->dev_private;
	int ret;
	struct dsi_mnp dsi_mnp;
	u32 dsi_clk;

	DRM_DEBUG_KMS("\n");

	if (intel_dsi->dsi_clock_freq)
		dsi_clk = intel_dsi->dsi_clock_freq;
	else
		get_dsi_clk(intel_dsi, mode, &dsi_clk);

	ret = dsi_calc_mnp(dsi_clk, &dsi_mnp);
	/*ret = mnp_from_clk_table(dsi_clk, &dsi_mnp);*/

	if (ret != 0)
		return ret;

	dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;

	DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
			dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl);

	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, dsi_mnp.dsi_pll_div);
	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl);

	return 0;
}
int intel_configure_dsi_pll(struct intel_dsi *intel_dsi,
		struct drm_display_mode *mode)
{
	struct drm_i915_private *dev_priv =
			intel_dsi->base.base.dev->dev_private;
	int ret;
	struct dsi_mnp dsi_mnp;
	u32 dsi_clk;


	get_dsi_clk(intel_dsi, mode, &dsi_clk);
	ret = dsi_calc_mnp(dsi_clk, &dsi_mnp);
	/*ret = mnp_from_clk_table(dsi_clk, &dsi_mnp);*/

	if (ret != 0)
		return ret;

	intel_cck_write32(dev_priv, 0x48, 0x00000000);
	intel_cck_write32(dev_priv, 0x4C, dsi_mnp.dsi_pll_div);
	intel_cck_write32(dev_priv, 0x48, dsi_mnp.dsi_pll_ctrl);

	return 0;
}