/* * Compliant with CIM_48's sbPciCfg. * Add any south bridge setting. */ static void sb700_pci_cfg() { device_t dev; u8 byte; /* SMBus Device, BDF:0-20-0 */ //dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); dev = _pci_make_tag(0, 20, 0); #if 1 /* Enable watchdog decode timer */ printk_info("enable watchdog decode timer\n"); byte = pci_read_config8(dev, 0x41); byte |= (1 << 3); pci_write_config8(dev, 0x41, byte); /* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles) * generated PCIRST#. */ byte = pmio_read(0x65); byte |= (1 << 4); pmio_write(0x65, byte); #endif /* IDE Device, BDF:0-20-1 */ //dev = pci_locate_device(PCI_ID(0x1002, 0x438C), 0); dev = _pci_make_tag(0, 20, 1); /* Enable IDE Explicit prefetch, 0x63[0] clear */ printk_info("enable IDE explicit prefetch\n"); byte = pci_read_config8(dev, 0x63); byte &= 0xfe; pci_write_config8(dev, 0x63, byte); /* LPC Device, BDF:0-20-3 */ //dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0); dev = _pci_make_tag(0, 20, 3); /* rpr7.2 Enabling LPC DMA function. */ printk_info("enabling lpc dma function\n"); byte = pci_read_config8(dev, 0x40); byte |= (1 << 2); pci_write_config8(dev, 0x40, byte); /* rpr7.3 Disabling LPC TimeOut. 0x48[7] clear. */ printk_info("disable lpc timeout\n"); byte = pci_read_config8(dev, 0x48); byte &= 0x7f; pci_write_config8(dev, 0x48, byte); /* rpr7.5 Disabling LPC MSI Capability, 0x78[1] clear. */ printk_info("disable LPC MSI Capability\n"); byte = pci_read_config8(dev, 0x78); byte &= 0xfd; pci_write_config8(dev, 0x78, byte); #ifdef ENABLE_SATA /* SATA Device, BDF:0-18-0, Non-Raid-5 SATA controller */ //dev = pci_locate_device(PCI_ID(0x1002, 0x4380), 0); dev = _pci_make_tag(0, 17, 0); /* rpr7.12 SATA MSI and D3 Power State Capability. * TODO: We assume S1 is supported. What if it isn't support? */ byte = pci_read_config8(dev, 0x40); byte |= 1 << 0; pci_write_config8(dev, 0x40, byte); if (get_sb700_revision() <= 0x12) pci_write_config8(dev, 0x34, 0x70); else pci_write_config8(dev, 0x34, 0x50); byte &= ~(1 << 0); pci_write_config8(dev, 0x40, byte); #endif /* TODO: There are several pairs of USB devices. * Two 4396s, two 4397s, two 4398s. * The code below only set one of each two. The other * will be done in sb700_usb.c after all. * So we don't take the trouble to set them both. */ /* EHCI Device, BDF:0-19-2, ehci usb controller */ //dev = pci_locate_device(PCI_ID(0x1002, 0x4396), 0); dev = _pci_make_tag(0, 19, 2); /* rpr6.16 Disabling USB EHCI MSI Capability. 0x50[6]. */ byte = pci_read_config8(dev, 0x50); byte |= (1 << 6); pci_write_config8(dev, 0x50, byte); //lycheng add disabling usb ohci and ehci msi capability /* EHCI Device, BDF:0-18-2, ehci usb controller */ //dev = pci_locate_device(PCI_ID(0x1002, 0x4396), 0); dev = _pci_make_tag(0, 18, 2); /* rpr6.16 Disabling USB EHCI MSI Capability. 0x50[6]. */ byte = pci_read_config8(dev, 0x50); byte |= (1 << 6); pci_write_config8(dev, 0x50, byte); /* OHCI0 Device, BDF:0-19-0, ohci usb controller #0 */ //dev = pci_locate_device(PCI_ID(0x1002, 0x4387), 0); dev = _pci_make_tag(0, 19, 0); /* rpr5.11 Disabling USB OHCI MSI Capability. 0x40[12:8]=0x1f. */ printk_info("disable USB OHCI MSI Capability\n"); byte = pci_read_config8(dev, 0x41); byte |= 0x3; pci_write_config8(dev, 0x41, byte); dev = _pci_make_tag(0, 18, 0); /* rpr5.11 Disabling USB OHCI MSI Capability. 0x40[12:8]=0x1f. */ printk_info("disable USB OHCI MSI Capability\n"); byte = pci_read_config8(dev, 0x41); byte |= 0x3; pci_write_config8(dev, 0x41, byte); /* OHCI0 Device, BDF:0-19-1, ohci usb controller #0 */ //dev = pci_locate_device(PCI_ID(0x1002, 0x4398), 0); dev = _pci_make_tag(0, 19, 1); byte = pci_read_config8(dev, 0x41); byte |= 0x3; pci_write_config8(dev, 0x41, byte); dev = _pci_make_tag(0, 18, 1); byte = pci_read_config8(dev, 0x41); byte |= 0x3; pci_write_config8(dev, 0x41, byte); /* OHCI0 Device, BDF:0-20-5, ohci usb controller #0 */ //dev = pci_locate_device(PCI_ID(0x1002, 0x4399), 0); dev = _pci_make_tag(0, 20, 5); byte = pci_read_config8(dev, 0x41); byte |= 0x3; pci_write_config8(dev, 0x41, byte); }
/* * SB700 enables all USB controllers by default in SMBUS Control. * SB700 enables SATA by default in SMBUS Control. */ static void sm_init(device_t dev) { u8 byte; u8 byte_old; u8 rev; u32 dword; void *ioapic_base; uint32_t power_state; uint32_t enable_legacy_usb; u32 nmi_option; printk(BIOS_INFO, "sm_init().\n"); rev = get_sb700_revision(dev); /* This works in a similar fashion to a memory resource, but without an enable bit */ ioapic_base = (void *)(pci_read_config32(dev, 0x74) & (0xffffffe0)); setup_ioapic(ioapic_base, 0); /* Don't rename IOAPIC ID. */ enable_legacy_usb = 1; get_option(&enable_legacy_usb, "enable_legacy_usb"); /* 2.10 Interrupt Routing/Filtering */ byte = pci_read_config8(dev, 0x62); if (enable_legacy_usb) byte |= 0x3; else byte &= ~0x3; pci_write_config8(dev, 0x62, byte); byte = pci_read_config8(dev, 0x67); if (enable_legacy_usb) byte |= 0x1 << 7; else byte &= ~(0x1 << 7); pci_write_config8(dev, 0x67, byte); /* Delay back to back interrupts to the CPU. */ dword = pci_read_config16(dev, 0x64); dword |= 1 << 13; pci_write_config16(dev, 0x64, dword); /* rrg:K8 INTR Enable (BIOS should set this bit after PIC initialization) */ /* rpr 2.1 Enabling Legacy Interrupt */ dword = pci_read_config8(dev, 0x62); dword |= 1 << 2; pci_write_config8(dev, 0x62, dword); dword = pci_read_config32(dev, 0x78); dword |= 1 << 9; pci_write_config32(dev, 0x78, dword); /* enable 0xCD6 0xCD7 */ /* bit 10: MultiMediaTimerIrqEn */ dword = pci_read_config8(dev, 0x64); dword |= 1 << 10; pci_write_config8(dev, 0x64, dword); /* enable serial irq */ byte = pci_read_config8(dev, 0x69); byte |= 1 << 7; /* enable serial irq function */ byte &= ~(0xF << 2); byte |= 4 << 2; /* set NumSerIrqBits=4 */ pci_write_config8(dev, 0x69, byte); /* Sx State Settings * Note: These 2 registers need to be set correctly for the S-state * to work properly. Otherwise the system may hang during resume * from the S-state. */ /*Use 8us clock for delays in the S-state resume timing sequence.*/ byte = pm_ioread(0x65); byte &= ~(1 << 7); pm_iowrite(0x65, byte); /* Delay the APIC interrupt to the CPU until the system has fully resumed from the S-state. */ byte = pm_ioread(0x68); byte |= 1 << 2; pm_iowrite(0x68, byte); /* IRQ0From8254 */ byte = pci_read_config8(dev, 0x41); byte &= ~(1 << 7); pci_write_config8(dev, 0x41, byte); byte = pm_ioread(0x61); if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)) byte &= ~(1 << 1); /* Clear for non-K8 CPUs */ else byte |= 1 << 1; /* Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7 */ pm_iowrite(0x61, byte); /* disable SMI */ byte = pm_ioread(0x53); byte |= 1 << 3; pm_iowrite(0x53, byte); /* power after power fail */ power_state = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; get_option(&power_state, "power_on_after_fail"); if (power_state > 2) { printk(BIOS_WARNING, "Invalid power_on_after_fail setting, using default\n"); power_state = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; } byte = pm_ioread(0x74); byte &= ~0x03; if (power_state == POWER_MODE_OFF) byte |= 0x0; else if (power_state == POWER_MODE_ON) byte |= 0x1; else if (power_state == POWER_MODE_LAST) byte |= 0x2; byte |= 1 << 2; pm_iowrite(0x74, byte); printk(BIOS_INFO, "set power \"%s\" after power fail\n", power_mode_names[power_state]); byte = pm_ioread(0x68); byte &= ~(1 << 1); /* 2.7 */ byte |= 1 << 2; pm_iowrite(0x68, byte); /* 2.7 */ byte = pm_ioread(0x65); byte &= ~(1 << 7); pm_iowrite(0x65, byte); /* 2.16 */ byte = pm_ioread(0x55); byte |= 1 << 5; pm_iowrite(0x55, byte); byte = pm_ioread(0xD7); byte |= 1 << 6 | 1 << 1; pm_iowrite(0xD7, byte); /* 2.15 */ byte = pm_ioread(0x42); byte &= ~(1 << 2); pm_iowrite(0x42, byte); /* Set up NMI on errors */ byte = inb(0x70); /* RTC70 */ byte_old = byte; nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ printk(BIOS_INFO, "++++++++++set NMI+++++\n"); } else { byte |= (1 << 7); /* Can not mask NMI from PCI-E and NMI_NOW */ printk(BIOS_INFO, "++++++++++no set NMI+++++\n"); } byte &= ~(1 << 7); if (byte != byte_old) { outb(byte, 0x70); } /*rpr v2.13 2.22 SMBUS PCI Config */ byte = pci_read_config8(dev, 0xE1); if ((REV_SB700_A11 == rev) || REV_SB700_A12 == rev) { byte |= 1 << 0; } /*Set bit2 to 1, enable Io port 60h read/write SMi trapping and *Io port 64h write Smi trapping. conflict with ps2 keyboard */ //byte |= 1 << 2 | 1 << 3 | 1 << 4; byte |= 1 << 3 | 1 << 4; pci_write_config8(dev, 0xE1, byte); /* 2.5 Enabling Non-Posted Memory Write */ axindxc_reg(0x10, 1 << 9, 1 << 9); /* 2.11 IO Trap Settings */ abcfg_reg(0x10090, 1 << 16, 1 << 16); /* ab index */ pci_write_config32(dev, 0xF0, AB_INDX); /* Initialize the real time clock */ cmos_init(0); /* 4.3 Enabling Upstream DMA Access */ axcfg_reg(0x04, 1 << 2, 1 << 2); /* 4.4 Enabling IDE/PCIB Prefetch for Performance Enhancement */ abcfg_reg(0x10060, 9 << 17, 9 << 17); abcfg_reg(0x10064, 9 << 17, 9 << 17); /* 4.5 Enabling OHCI Prefetch for Performance Enhancement, A12 */ abcfg_reg(0x80, 1 << 0, 1<< 0); /* 4.6 B-Link Client's Credit Variable Settings for the Downstream Arbitration Equation */ /* 4.7 Enabling Additional Address Bits Checking in Downstream */ /* 4.16 IO write and SMI ordering enhancement*/ abcfg_reg(0x9c, 3 << 0, 3 << 0); if (REV_SB700_A12 == rev) { abcfg_reg(0x9c, 1 << 8, 1 << 8); } else if (rev >= REV_SB700_A14) { abcfg_reg(0x9c, 1 << 8, 0 << 8); } if (REV_SB700_A15 == rev) { abcfg_reg(0x90, 1 << 21, 1 << 21); abcfg_reg(0x9c, 1 << 5 | 1 << 9 | 1 << 15, 1 << 5 | 1 << 9 | 1 << 15); } /* 4.8 Set B-Link Prefetch Mode */ abcfg_reg(0x80, 3 << 17, 3 << 17); /* 4.9 Enabling Detection of Upstream Interrupts */ abcfg_reg(0x94, 1 << 20 | 0x7FFFF, 1 << 20 | 0x00FEE); /* 4.10: Enabling Downstream Posted Transactions to Pass Non-Posted * Transactions for the K8 Platform (for All Revisions) */ abcfg_reg(0x10090, 1 << 8, 1 << 8); /* Set ACPI Software clock Throttling Period to 244 us*/ byte = pm_ioread(0x68); byte &= ~(3 << 6); byte |= (2 << 6); /* 244us */ pm_iowrite(0x68, byte); if (REV_SB700_A15 == rev) { u16 word; /* rpr v2.13 4.18 Enabling Posted Pass Non-Posted Downstream */ axindxc_reg(0x02, 1 << 9, 1 << 9); abcfg_reg(0x9C, 0x00007CC0, 0x00007CC0); abcfg_reg(0x1009C, 0x00000030, 0x00000030); abcfg_reg(0x10090, 0x00001E00, 0x00001E00); /* rpr v2.13 4.19 Enabling Posted Pass Non-Posted Upstream */ abcfg_reg(0x58, 0x0000F800, 0x0000E800); /* rpr v2.13 4.20 64 bit Non-Posted Memory Write Support */ axindxc_reg(0x02, 1 << 10, 1 << 10); /* rpr v2.13 2.38 Unconditional Shutdown */ byte = pci_read_config8(dev, 0x43); byte &= ~(1 << 3); pci_write_config8(dev, 0x43, byte); word = pci_read_config16(dev, 0x38); word |= 1 << 12; pci_write_config16(dev, 0x38, word); byte |= 1 << 3; pci_write_config8(dev, 0x43, byte); /* Enable southbridge MMIO decode */ dword = pci_read_config32(dev, SB_MMIO_CFG_REG); dword &= ~(0xffffff << 8); dword |= SB_MMIO_BASE_ADDRESS; dword |= 0x1; pci_write_config32(dev, SB_MMIO_CFG_REG, dword); } byte = pci_read_config8(dev, 0xAE); if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID)) byte |= 1 << 4; byte |= 1 << 5; /* ACPI_DISABLE_TIMER_IRQ_ENHANCEMENT_FOR_8254_TIMER */ byte |= 1 << 6; /* Enable arbiter between APIC and PIC interrupts */ pci_write_config8(dev, 0xAE, byte); /* 4.11:Programming Cycle Delay for AB and BIF Clock Gating */ /* 4.12: Enabling AB and BIF Clock Gating */ abcfg_reg(0x10054, 0xFFFF0000, 0x1040000); abcfg_reg(0x54, 0xFF << 16, 4 << 16); abcfg_reg(0x54, 1 << 24, 0 << 24); abcfg_reg(0x98, 0x0000FF00, 0x00004700); /* 4.13:Enabling AB Int_Arbiter Enhancement (for All Revisions) */ abcfg_reg(0x10054, 0x0000FFFF, 0x07FF); /* 4.14:Enabling Requester ID for upstream traffic. */ abcfg_reg(0x98, 1 << 16, 1 << 16); /* 9.2: Enabling IDE Data Bus DD7 Pull Down Resistor */ byte = pm2_ioread(0xE5); byte |= 1 << 2; pm2_iowrite(0xE5, byte); /* Enable IDE controller. */ byte = pm_ioread(0x59); byte &= ~(1 << 1); pm_iowrite(0x59, byte); /* Enable SCI as irq9. */ outb(0x4, 0xC00); outb(0x9, 0xC01); printk(BIOS_INFO, "sm_init() end\n"); /* Enable NbSb virtual channel */ axcfg_reg(0x114, 0x3f << 1, 0 << 1); axcfg_reg(0x120, 0x7f << 1, 0x7f << 1); axcfg_reg(0x120, 7 << 24, 1 << 24); axcfg_reg(0x120, 1 << 31, 1 << 31); abcfg_reg(0x50, 1 << 3, 1 << 3); }
void sb700_pmio_por_init(void) { u8 byte; #if 1 printk_info("sb700_pmio_por_init()\n"); /* K8KbRstEn, KB_RST# control for K8 system. */ byte = pmio_read(0x66); byte |= 0x20; pmio_write(0x66, byte); /* RPR2.31 PM_TURN_OFF_MSG during ASF Shutdown. */ if (get_sb700_revision() <= 0x12) { byte = pmio_read(0x65); byte &= ~(1 << 7); pmio_write(0x65, byte); byte = pmio_read(0x75); byte &= 0xc0; byte |= 0x05; pmio_write(0x75, byte); byte = pmio_read(0x52); byte &= 0xc0; byte |= 0x08; pmio_write(0x52, byte); } else { byte = pmio_read(0xD7); byte |= 1 << 0; pmio_write(0xD7, byte); byte = pmio_read(0x65); byte |= 1 << 7; pmio_write(0x65, byte); byte = pmio_read(0x75); byte &= 0xc0; byte |= 0x01; pmio_write(0x75, byte); byte = pmio_read(0x52); byte &= 0xc0; byte |= 0x02; pmio_write(0x52, byte); } pmio_write(0x6c, 0xf0); pmio_write(0x6d, 0x00); pmio_write(0x6e, 0xc0); pmio_write(0x6f, 0xfe); /* rpr2.19: Enabling Spread Spectrum */ printk_info("Enabling Spread Spectrum\n"); byte = pmio_read(0x42); byte |= 1 << 7; pmio_write(0x42, byte); /* TODO: Check if it is necessary. IDE reset */ byte = pmio_read(0xB2); byte |= 1 << 0; pmio_write(0xB2, byte); #endif }
static void usb_init2(struct device *dev) { u32 dword; void *usb2_bar0; device_t sm_dev; u8 rev; sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); rev = get_sb700_revision(sm_dev); /* dword = pci_read_config32(dev, 0xf8); */ /* dword |= 40; */ /* pci_write_config32(dev, 0xf8, dword); */ usb2_bar0 = (void *)(pci_read_config32(dev, 0x10) & ~0xFF); printk(BIOS_INFO, "usb2_bar0=0x%p\n", usb2_bar0); /* RPR6.4 Enables the USB PHY auto calibration resister to match 45ohm resistance */ dword = 0x00020F00; write32(usb2_bar0 + 0xC0, dword); /* RPR6.9 Sets In/OUT FIFO threshold for best performance */ dword = 0x00400040; write32(usb2_bar0 + 0xA4, dword); /* RPR6.11 Disabling EHCI Advance Asynchronous Enhancement */ dword = pci_read_config32(dev, 0x50); dword |= (1 << 28); pci_write_config32(dev, 0x50, dword); /* RPR 6.12 EHCI Advance PHY Power Savings */ /* RPR says it is just for A12. CIMM sets it when it is above A11. */ /* But it makes the linux crash, so we skip it */ dword = pci_read_config32(dev, 0x50); dword |= 1 << 31; pci_write_config32(dev, 0x50, dword); /* RPR6.13 Enabling Fix for EHCI Controller Driver Yellow Sign Issue */ /* RPR says it is just for A12. CIMx sets it when it is above A11. */ dword = pci_read_config32(dev, 0x50); dword |= (1 << 20); pci_write_config32(dev, 0x50, dword); /* RPR6.15 EHCI Async Park Mode */ dword = pci_read_config32(dev, 0x50); dword |= (1 << 23); pci_write_config32(dev, 0x50, dword); /* Each step below causes the linux crashes. Leave them here * for future debugging. */ u8 byte; u16 word; /* RPR6.16 Disable EHCI MSI support */ byte = pci_read_config8(dev, 0x50); byte |= (1 << 6); pci_write_config8(dev, 0x50, byte); /* RPR6.17 Disable the EHCI Dynamic Power Saving feature */ word = read32(usb2_bar0 + 0xBC); word &= ~(1 << 12); write16(usb2_bar0 + 0xBC, word); /* RPR6.19 USB Controller DMA Read Delay Tolerant. */ if (rev >= REV_SB700_A14) { byte = pci_read_config8(dev, 0x50); byte |= (1 << 7); pci_write_config8(dev, 0x50, byte); } /* SB700_A15, USB-2_EHCI_PID_ERROR_CHECKING */ if (rev == REV_SB700_A15) { word = pci_read_config16(dev, 0x50); word |= (1 << 9); pci_write_config16(dev, 0x50, word); } /* RPR6.20 Async Park Mode. */ /* RPR recommends not to set these bits. */ #if 0 dword = pci_read_config32(dev, 0x50); dword |= 1 << 23; if (rev >= REV_SB700_A14) { dword &= ~(1 << 2); } pci_write_config32(dev, 0x50, dword); #endif /* RPR6.22 Advance Async Enhancement */ /* RPR6.23 USB Periodic Cache Setting */ dword = pci_read_config32(dev, 0x50); if (rev == REV_SB700_A12) { dword |= 1 << 28; /* 6.22 */ dword |= 1 << 27; /* 6.23 */ } else if (rev >= REV_SB700_A14) { dword |= 1 << 3; dword &= ~(1 << 28); /* 6.22 */ dword |= 1 << 8; dword &= ~(1 << 27); /* 6.23 */ } pci_write_config32(dev, 0x50, dword); printk(BIOS_DEBUG, "rpr 6.23, final dword=%x\n", dword); }