static int register_process_cik(struct device_queue_manager *dqm, struct qcm_process_device *qpd) { struct kfd_process_device *pdd; unsigned int temp; BUG_ON(!dqm || !qpd); pdd = qpd_to_pdd(qpd); /* check if sh_mem_config register already configured */ if (qpd->sh_mem_config == 0) { qpd->sh_mem_config = ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED) | DEFAULT_MTYPE(MTYPE_NONCACHED) | APE1_MTYPE(MTYPE_NONCACHED); qpd->sh_mem_ape1_limit = 0; qpd->sh_mem_ape1_base = 0; } if (qpd->pqm->process->is_32bit_user_mode) { temp = get_sh_mem_bases_32(pdd); qpd->sh_mem_bases = SHARED_BASE(temp); qpd->sh_mem_config |= PTR32; } else { temp = get_sh_mem_bases_nybble_64(pdd); qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp); } pr_debug("kfd: is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n", qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases); return 0; }
static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q, struct qcm_process_device *qpd) { uint32_t value = (1 << SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT); if (q->process->is_32bit_user_mode) value |= (1 << SDMA0_RLC0_VIRTUAL_ADDR__PTR32__SHIFT) | get_sh_mem_bases_32(qpd_to_pdd(qpd)); else value |= ((get_sh_mem_bases_nybble_64(qpd_to_pdd(qpd))) << SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT) & SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK; q->properties.sdma_vm_addr = value; }
static int register_process_vi(struct device_queue_manager *dqm, struct qcm_process_device *qpd) { struct kfd_process_device *pdd; unsigned int temp; pdd = qpd_to_pdd(qpd); /* check if sh_mem_config register already configured */ if (qpd->sh_mem_config == 0) { qpd->sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT | MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT | MTYPE_CC << SH_MEM_CONFIG__APE1_MTYPE__SHIFT | SH_MEM_CONFIG__PRIVATE_ATC_MASK; qpd->sh_mem_ape1_limit = 0; qpd->sh_mem_ape1_base = 0; } if (qpd->pqm->process->is_32bit_user_mode) { temp = get_sh_mem_bases_32(pdd); qpd->sh_mem_bases = temp << SH_MEM_BASES__SHARED_BASE__SHIFT; qpd->sh_mem_config |= SH_MEM_ADDRESS_MODE_HSA32 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT; } else { temp = get_sh_mem_bases_nybble_64(pdd); qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp); qpd->sh_mem_config |= SH_MEM_ADDRESS_MODE_HSA64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT; qpd->sh_mem_config |= 1 << SH_MEM_CONFIG__PRIVATE_ATC__SHIFT; } pr_debug("is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n", qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases); return 0; }