/******************************************************************************* * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. * The interrupt controller knows which pin/line it uses to signal a type of * interrupt. The platform knows which interrupt controller type is being used * in a particular security state e.g. with an ARM GIC, normal world could use * the GICv2 features while the secure world could use GICv3 features and vice * versa. * This function is exported by the platform to let the interrupt management * framework determine for a type of interrupt and security state, which line * should be used in the SCR_EL3 to control its routing to EL3. The interrupt * line is represented as the bit position of the IRQ or FIQ bit in the SCR_EL3. ******************************************************************************/ uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state) { assert(type == INTR_TYPE_S_EL1 || type == INTR_TYPE_EL3 || type == INTR_TYPE_NS); assert(sec_state_is_valid(security_state)); /* * We ignore the security state parameter because Juno is GICv2 only * so both normal and secure worlds are using ARM GICv2. */ return gicv2_interrupt_type_to_line(GICC_BASE, type); }
/******************************************************************************* * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. * The interrupt controller knows which pin/line it uses to signal a type of * interrupt. This function provides a common implementation of * plat_interrupt_type_to_line() in an ARM GIC environment for optional re-use * across platforms. It lets the interrupt management framework determine * for a type of interrupt and security state, which line should be used in the * SCR_EL3 to control its routing to EL3. The interrupt line is represented as * the bit position of the IRQ or FIQ bit in the SCR_EL3. ******************************************************************************/ uint32_t tegra_gic_interrupt_type_to_line(uint32_t type, uint32_t security_state) { assert(type == INTR_TYPE_S_EL1 || type == INTR_TYPE_EL3 || type == INTR_TYPE_NS); assert(sec_state_is_valid(security_state)); /* * We ignore the security state parameter under the assumption that * both normal and secure worlds are using ARM GICv2. This parameter * will be used when the secure world starts using GICv3. */ #if ARM_GIC_ARCH == 2 return gicv2_interrupt_type_to_line(TEGRA_GICC_BASE, type); #else #error "Invalid ARM GIC architecture version specified for platform port" #endif /* ARM_GIC_ARCH */ }