static int __init tegra_init_ahb_gizmo_settings(void) { unsigned long val; val = gizmo_readl(AHB_GIZMO_AHB_MEM); val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR; if (tegra_get_chipid() == TEGRA_CHIPID_TEGRA11 && tegra_revision == TEGRA_REVISION_A02) val |= WR_WAIT_COMMIT_ON_1K; #ifdef CONFIG_ARCH_TEGRA_14x_SOC val |= WR_WAIT_COMMIT_ON_1K | EN_USB_WAIT_COMMIT_ON_1K_STALL; #endif gizmo_writel(val, AHB_GIZMO_AHB_MEM); val = gizmo_readl(AHB_GIZMO_USB); val |= IMMEDIATE; gizmo_writel(val, AHB_GIZMO_USB); val = gizmo_readl(AHB_GIZMO_USB2); val |= IMMEDIATE; gizmo_writel(val, AHB_GIZMO_USB2); val = gizmo_readl(AHB_GIZMO_USB3); val |= IMMEDIATE; gizmo_writel(val, AHB_GIZMO_USB3); val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL); val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3 | AHB_PRIORITY_WEIGHT(7); gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL); val = gizmo_readl(AHB_MEM_PREFETCH_CFG1); val &= ~MST_ID(~0); val |= PREFETCH_ENB | AHBDMA_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000); ahb_gizmo_writel(val, IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG1)); val = gizmo_readl(AHB_MEM_PREFETCH_CFG2); val &= ~MST_ID(~0); val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000); ahb_gizmo_writel(val, IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG2)); val = gizmo_readl(AHB_MEM_PREFETCH_CFG3); val &= ~MST_ID(~0); val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000); ahb_gizmo_writel(val, IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG3)); val = gizmo_readl(AHB_MEM_PREFETCH_CFG4); val &= ~MST_ID(~0); val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000); ahb_gizmo_writel(val, IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG4)); register_syscore_ops(&tegra_ahbgizmo_syscore_ops); return 0; }
static void tegra_ahb_gizmo_init(struct tegra_ahb *ahb) { u32 val; val = gizmo_readl(ahb, AHB_GIZMO_AHB_MEM); val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR; gizmo_writel(ahb, val, AHB_GIZMO_AHB_MEM); val = gizmo_readl(ahb, AHB_GIZMO_USB); val |= IMMEDIATE; gizmo_writel(ahb, val, AHB_GIZMO_USB); val = gizmo_readl(ahb, AHB_GIZMO_USB2); val |= IMMEDIATE; gizmo_writel(ahb, val, AHB_GIZMO_USB2); val = gizmo_readl(ahb, AHB_GIZMO_USB3); val |= IMMEDIATE; gizmo_writel(ahb, val, AHB_GIZMO_USB3); val = gizmo_readl(ahb, AHB_ARBITRATION_PRIORITY_CTRL); val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3 | AHB_PRIORITY_WEIGHT(7); gizmo_writel(ahb, val, AHB_ARBITRATION_PRIORITY_CTRL); val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG1); val &= ~MST_ID(~0); val |= PREFETCH_ENB | AHBDMA_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000); gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG1); val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG2); val &= ~MST_ID(~0); val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000); gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG2); val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG3); val &= ~MST_ID(~0); val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000); gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG3); val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG4); val &= ~MST_ID(~0); val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000); gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG4); }
static int tegra_ahb_resume(struct device *dev) { int i; struct tegra_ahb *ahb = dev_get_drvdata(dev); for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++) gizmo_writel(ahb, ahb->ctx[i], tegra_ahb_gizmo[i]); return 0; }
int tegra_ahb_enable_smmu(struct device_node *dn) { struct device *dev; u32 val; struct tegra_ahb *ahb; dev = driver_find_device(&tegra_ahb_driver.driver, NULL, dn, tegra_ahb_match_by_smmu); if (!dev) return -EPROBE_DEFER; ahb = dev_get_drvdata(dev); val = gizmo_readl(ahb, AHB_ARBITRATION_XBAR_CTRL); val |= AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE; gizmo_writel(ahb, val, AHB_ARBITRATION_XBAR_CTRL); return 0; }
void tegra_ahbgizmo_resume(void) { gizmo_writel(ahb_gizmo[0], AHB_ARBITRATION_DISABLE); gizmo_writel(ahb_gizmo[1], AHB_ARBITRATION_PRIORITY_CTRL); gizmo_writel(ahb_gizmo[2], AHB_GIZMO_AHB_MEM); gizmo_writel(ahb_gizmo[3], AHB_GIZMO_APB_DMA); gizmo_writel(ahb_gizmo[4], AHB_GIZMO_IDE); gizmo_writel(ahb_gizmo[5], AHB_GIZMO_USB); gizmo_writel(ahb_gizmo[6], AHB_GIZMO_AHB_XBAR_BRIDGE); gizmo_writel(ahb_gizmo[7], AHB_GIZMO_CPU_AHB_BRIDGE); gizmo_writel(ahb_gizmo[8], AHB_GIZMO_COP_AHB_BRIDGE); gizmo_writel(ahb_gizmo[9], AHB_GIZMO_XBAR_APB_CTLR); gizmo_writel(ahb_gizmo[10], AHB_GIZMO_VCP_AHB_BRIDGE); gizmo_writel(ahb_gizmo[11], AHB_GIZMO_NAND); gizmo_writel(ahb_gizmo[12], AHB_GIZMO_SDMMC4); gizmo_writel(ahb_gizmo[13], AHB_GIZMO_XIO); gizmo_writel(ahb_gizmo[14], AHB_GIZMO_BSEV); gizmo_writel(ahb_gizmo[15], AHB_GIZMO_BSEA); gizmo_writel(ahb_gizmo[16], AHB_GIZMO_NOR); gizmo_writel(ahb_gizmo[17], AHB_GIZMO_USB2); gizmo_writel(ahb_gizmo[18], AHB_GIZMO_USB3); gizmo_writel(ahb_gizmo[19], AHB_GIZMO_SDMMC1); gizmo_writel(ahb_gizmo[20], AHB_GIZMO_SDMMC2); gizmo_writel(ahb_gizmo[21], AHB_GIZMO_SDMMC3); ahb_gizmo_writel(ahb_gizmo[22], IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG_X)); gizmo_writel(ahb_gizmo[23], AHB_ARBITRATION_XBAR_CTRL); ahb_gizmo_writel(ahb_gizmo[24], IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG3)); ahb_gizmo_writel(ahb_gizmo[25], IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG4)); ahb_gizmo_writel(ahb_gizmo[26], IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG1)); ahb_gizmo_writel(ahb_gizmo[27], IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG2)); gizmo_writel(ahb_gizmo[28], AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID); gizmo_writel(ahb_gizmo[29], AHB_GIZMO_TZRAM); }