int mainboard_smi_apmc(u8 apmc)
{
switch (apmc) {
case APMC_FINALIZE:
if (mainboard_finalized) {
printk(BIOS_DEBUG, "SMI#: Already finalized\n");
return 0;
}
intel_pch_finalize_smm();
intel_northbridge_haswell_finalize_smm();
intel_cpu_haswell_finalize_smm();
mainboard_finalized = 1;
break;
case APM_CNT_ACPI_ENABLE:
google_chromeec_set_smi_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0);
google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
break;
case APM_CNT_ACPI_DISABLE:
google_chromeec_set_sci_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0);
google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
break;
}
return 0;
}
int mainboard_smi_apmc(u8 apmc)
{
switch (apmc) {
case APMC_FINALIZE:
if (mainboard_finalized) {
printk(BIOS_DEBUG, "SMI#: Already finalized\n");
return 0;
}
intel_me_finalize_smm();
intel_pch_finalize_smm();
intel_sandybridge_finalize_smm();
intel_model_206ax_finalize_smm();
mainboard_finalized = 1;
break;
case APMC_ACPI_EN:
google_chromeec_set_smi_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0);
google_chromeec_set_sci_mask(LINK_EC_SCI_EVENTS);
break;
case APMC_ACPI_DIS:
google_chromeec_set_sci_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0);
google_chromeec_set_smi_mask(LINK_EC_SMI_EVENTS);
break;
}
return 0;
}
void chromeec_smi_apmc(int apmc, uint32_t sci_mask, uint32_t smi_mask)
{
switch (apmc) {
case APM_CNT_ACPI_ENABLE:
google_chromeec_set_smi_mask(0);
clear_pending_events();
google_chromeec_set_sci_mask(sci_mask);
break;
case APM_CNT_ACPI_DISABLE:
google_chromeec_set_sci_mask(0);
clear_pending_events();
google_chromeec_set_smi_mask(smi_mask);
break;
}
}
void mainboard_smi_sleep(u8 slp_typ)
{
/* Disable USB charging if required */
switch (slp_typ) {
case 3:
if (smm_get_gnvs()->s3u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
if (smm_get_gnvs()->s3u1 == 0)
google_chromeec_set_usb_charge_mode(
1, USB_CHARGE_MODE_DISABLED);
break;
case 5:
if (smm_get_gnvs()->s5u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
if (smm_get_gnvs()->s5u1 == 0)
google_chromeec_set_usb_charge_mode(
1, USB_CHARGE_MODE_DISABLED);
break;
}
/* Disable SCI and SMI events */
google_chromeec_set_smi_mask(0);
google_chromeec_set_sci_mask(0);
/* Clear pending events that may trigger immediate wake */
while (google_chromeec_get_event() != 0);
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
}
void mainboard_ec_init(void)
{
printk(BIOS_DEBUG, "mainboard: EC init\n");
if (acpi_is_wakeup_s3()) {
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
MAINBOARD_EC_S3_WAKE_EVENTS);
/* Disable SMI and wake events */
google_chromeec_set_smi_mask(0);
/* Clear pending events */
while (google_chromeec_get_event() != 0)
;
/* Restore SCI event mask */
google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
} else {
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
MAINBOARD_EC_S5_WAKE_EVENTS);
}
/* Clear wake event mask */
google_chromeec_set_wake_mask(0);
}
void mainboard_ec_init(void)
{
printk(BIOS_DEBUG, "mainboard_ec_init\n");
post_code(0xf0);
/* Restore SCI event mask on resume. */
if (acpi_is_wakeup_s3()) {
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
MAINBOARD_EC_S3_WAKE_EVENTS);
/* Disable SMI and wake events */
google_chromeec_set_smi_mask(0);
/* Clear pending events */
while (google_chromeec_get_event() != 0)
;
google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
} else {
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
MAINBOARD_EC_S5_WAKE_EVENTS);
}
/* Clear wake events, these are enabled on entry to sleep */
google_chromeec_set_wake_mask(0);
post_code(0xf1);
}
void mainboard_ec_init(void)
{
printk(BIOS_DEBUG, "mainboard_ec_init\n");
post_code(0xf0);
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
/* Restore SCI event mask on resume. */
if (acpi_slp_type == 3) {
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
MAINBOARD_EC_S3_WAKE_EVENTS);
/* Disable SMI and wake events */
google_chromeec_set_smi_mask(0);
/* Clear pending events */
while (google_chromeec_get_event() != 0)
;
/*
* Set SCI mask.OS may not generate the SMI event to
* set this on S3 resume
*/
google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
} else {
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
MAINBOARD_EC_S5_WAKE_EVENTS);
}
/* Clear wake event mask */
google_chromeec_set_wake_mask(0);
#endif
post_code(0xf1);
}
int mainboard_smi_apmc(uint8_t apmc)
{
switch (apmc) {
case APM_CNT_ACPI_ENABLE:
google_chromeec_set_smi_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0);
google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
break;
case APM_CNT_ACPI_DISABLE:
google_chromeec_set_sci_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0);
google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);;
break;
}
return 0;
}
int mainboard_smi_apmc(u8 apmc)
{
switch (apmc) {
case APMC_ACPI_EN:
google_chromeec_set_smi_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0);
google_chromeec_set_sci_mask(LINK_EC_SCI_EVENTS);
break;
case APMC_ACPI_DIS:
google_chromeec_set_sci_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0);
google_chromeec_set_smi_mask(LINK_EC_SMI_EVENTS);
break;
}
return 0;
}
int mainboard_smi_apmc(u8 apmc)
{
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
switch (apmc) {
case APM_CNT_ACPI_ENABLE:
google_chromeec_set_smi_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0)
;
google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
break;
case APM_CNT_ACPI_DISABLE:
google_chromeec_set_sci_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0)
;
google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
break;
}
#endif
return 0;
}
void mainboard_smi_sleep(uint8_t slp_typ)
{
/* Disable USB charging if required */
switch (slp_typ) {
case 3:
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
if (smm_get_gnvs()->s3u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
if (smm_get_gnvs()->s3u1 == 0)
google_chromeec_set_usb_charge_mode(
1, USB_CHARGE_MODE_DISABLED);
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
#endif
/* Enable wake pin in GPE block. */
enable_gpe(WAKE_GPIO_EN);
break;
case 5:
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
if (smm_get_gnvs()->s5u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
if (smm_get_gnvs()->s5u1 == 0)
google_chromeec_set_usb_charge_mode(
1, USB_CHARGE_MODE_DISABLED);
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
#endif
break;
}
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
/* Disable SCI and SMI events */
google_chromeec_set_smi_mask(0);
google_chromeec_set_sci_mask(0);
/* Clear pending events that may trigger immediate wake */
while (google_chromeec_get_event() != 0)
;
if (smm_get_gnvs()->bdid == BOARD_DVT) {
/* Set LPC lines to low power in S3/S5. */
if ((slp_typ == SLEEP_STATE_S3) || (slp_typ == SLEEP_STATE_S5))
lpc_set_low_power();
}
#endif
}
void mainboard_smi_sleep(u8 slp_typ)
{
/* Disable USB charging if required */
switch (slp_typ) {
case 3:
if (smm_get_gnvs()->s3u0 == 0) {
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
google_chromeec_set_usb_charge_mode(
1, USB_CHARGE_MODE_DISABLED);
}
/* Put SSD in reset to prevent leak. */
set_gpio(SAMUS_GPIO_SSD_RESET_L, 0);
/* Prevent leak from standby rail to WLAN rail in S3. */
set_gpio(SAMUS_GPIO_WLAN_DISABLE_L, 0);
/* Disable LTE */
set_gpio(SAMUS_GPIO_LTE_DISABLE_L, 0);
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
break;
case 5:
if (smm_get_gnvs()->s5u0 == 0) {
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
google_chromeec_set_usb_charge_mode(
1, USB_CHARGE_MODE_DISABLED);
}
/* Put SSD in reset to prevent leak. */
set_gpio(SAMUS_GPIO_SSD_RESET_L, 0);
/* Prevent leak from standby rail to WLAN rail in S5. */
set_gpio(SAMUS_GPIO_WLAN_DISABLE_L, 0);
/* Disable LTE */
set_gpio(SAMUS_GPIO_LTE_DISABLE_L, 0);
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
break;
}
/* Disable SCI and SMI events */
google_chromeec_set_smi_mask(0);
google_chromeec_set_sci_mask(0);
/* Clear pending events that may trigger immediate wake */
while (google_chromeec_get_event() != 0);
}
void chromeec_smi_sleep(int slp_type, uint32_t s3_mask, uint32_t s5_mask)
{
switch (slp_type) {
case ACPI_S3:
/* Enable wake events */
google_chromeec_set_wake_mask(s3_mask);
break;
case ACPI_S5:
/* Enable wake events */
google_chromeec_set_wake_mask(s5_mask);
break;
}
/* Disable SCI and SMI events */
google_chromeec_set_smi_mask(0);
google_chromeec_set_sci_mask(0);
/* Clear pending events that may trigger immediate wake */
clear_pending_events();
}
void mainboard_smi_sleep(u8 slp_typ)
{
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
switch (slp_typ) {
case 3:
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
break;
case 5:
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
break;
}
/* Disable SCI and SMI events */
google_chromeec_set_smi_mask(0);
google_chromeec_set_sci_mask(0);
/* Clear pending events that may trigger immediate wake */
while (google_chromeec_get_event() != 0)
;
#endif
}
void google_chromeec_events_init(const struct google_chromeec_event_info *info,
bool is_s3_wakeup)
{
if (is_s3_wakeup) {
google_chromeec_log_events(info->log_events |
info->s3_wake_events);
/* Log and clear device events that may wake the system. */
google_chromeec_log_device_events(info->s3_device_events);
/* Disable SMI and wake events. */
google_chromeec_set_smi_mask(0);
/* Clear pending events. */
while (google_chromeec_get_event() != 0)
;
/* Restore SCI event mask. */
google_chromeec_set_sci_mask(info->sci_events);
} else {
google_chromeec_set_smi_mask(info->smi_events);
google_chromeec_log_events(info->log_events |
info->s5_wake_events);
if (google_chromeec_is_uhepi_supported())
google_chromeec_set_lazy_wake_masks
(info->s5_wake_events,
info->s3_wake_events,
info->s0ix_wake_events);
}
/* Clear wake event mask. */
google_chromeec_set_wake_mask(0);
}
void mainboard_smi_sleep(uint8_t slp_typ)
{
void *addr;
uint32_t mask;
/* Disable USB charging if required */
switch (slp_typ) {
case 3:
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
if (smm_get_gnvs()->s3u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
if (smm_get_gnvs()->s3u1 == 0)
google_chromeec_set_usb_charge_mode(
1, USB_CHARGE_MODE_DISABLED);
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
#endif
/* Enable wake pin in GPE block. */
enable_gpe(WAKE_GPIO_EN);
break;
case 5:
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
if (smm_get_gnvs()->s5u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
if (smm_get_gnvs()->s5u1 == 0)
google_chromeec_set_usb_charge_mode(
1, USB_CHARGE_MODE_DISABLED);
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
#endif
/* Disabling wake from SUS_GPIO1 (TOUCH INT) and
* SUS_GPIO7 (TRACKPAD INT) in North bank as they are not
* valid S5 wake sources
*/
addr = (void *)(IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPNORTH +
GPIO_WAKE_MASK_REG0);
mask = ~(GPIO_SUS1_WAKE_MASK | GPIO_SUS7_WAKE_MASK);
write32(addr, read32(addr) & mask);
break;
}
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
/* Disable SCI and SMI events */
google_chromeec_set_smi_mask(0);
google_chromeec_set_sci_mask(0);
/* Clear pending events that may trigger immediate wake */
while (google_chromeec_get_event() != 0)
;
if (smm_get_gnvs()->bdid == BOARD_PRE_EVT) {
/* Set LPC lines to low power in S3/S5. */
if ((slp_typ == SLEEP_STATE_S3) || (slp_typ == SLEEP_STATE_S5))
lpc_set_low_power();
}
#endif
}
