/**
 * Sensor process initializer.
 *
 * Resets all global presets.
 */
void sensor_process_init(void)
{

	(void)gpc_setup_reg(GPROT_ADC_BATTERY_VOLTAGE_REG_ADDR,
			    (u16 *) & (sensors.battery_voltage));
	(void)gpc_setup_reg(GPROT_ADC_CURRENT_REG_ADDR,
			    (u16 *) & (sensors.current));
	(void)gpc_setup_reg(GPROT_ADC_TEMPERATURE_REG_ADDR,
			    (u16 *) & (sensors.temp));

	sensor_process_trigger = &adc_data.trigger;

	sensors.battery_voltage = 0;
	sensors.current = 0;
	sensors.temp = 0;

	sensor_params.bv.offset = 0;
	sensor_params.bv.iir = 20;
	sensor_params.c.offset = 0;
	sensor_params.c.iir = 20;
	sensor_params.t.offset = 0;
	sensor_params.t.iir = 20;

	sensor_trigger_debug_output = 0;
}
/**
 * Initialize internal state of the cpu load process.
 */
void cpu_load_process_init()
{
	(void)gpc_setup_reg(GPROT_CPU_LOAD, (u16 *)&cpu_load_process_state.mean_cycles);
	(void)gpc_setup_reg(GPROT_CPU_LOAD_MAX, (u16 *)&cpu_load_process_state.max_cycles);
	(void)gpc_setup_reg(GPROT_CPU_LOAD_MIN, (u16 *)&cpu_load_process_state.min_cycles);
	(void)sys_tick_timer_register(cpu_load_process_soft_timer_callback,
				CLP__TIME_BASE);
	cpu_load_process_reset();
}
Example #3
0
/**
 * Initialize all necessary registers and callback hooks.
 *
 * @todo All setup regs should be called from the respective module init
 * functions.
 */
void gprot_init()
{
	(void)gpc_init(gprot_trigger_output, NULL, gprot_register_changed, NULL);
	(void)gpc_set_get_version_callback(gprot_get_version, NULL);

	gprot_flag_reg = 0;
	gprot_flag_reg_old = 0;
	(void)gpc_setup_reg(GPROT_FLAG_REG_ADDR, &gprot_flag_reg);

	(void)gpc_setup_reg(GPROT_NEW_CYCLE_TIME, (u16 *) & new_cycle_time);

	(void)gpc_setup_reg(GPROT_PWM_VAL_REG_ADDR, (u16 *) & gprot_pwm_power);
}
Example #4
0
END_TEST

START_TEST(test_gprotc_handle_byte_read)
{
	u8 addr = 0;

	for(addr=0; addr<32; addr++){
		fail_unless(0 == gpc_setup_reg(addr, &gpc_dummy_register_map[addr]));
	}

	for(addr=0; addr<32; addr++){
		fail_unless(0 == gpc_handle_byte(addr | GP_MODE_READ | GP_MODE_PEEK));
		fail_unless(1 == gpc_dummy_trigger_output_triggered);
		fail_unless((void *)1 == gpc_dummy_trigger_output_data);
		fail_unless(addr == gpc_pickup_byte());
		fail_unless(0x55+addr == gpc_pickup_byte());
		fail_unless(0xAA == gpc_pickup_byte());
		fail_unless(-1 == gpc_pickup_byte());

		gpc_dummy_trigger_output_triggered = 0;
		gpc_dummy_trigger_output_data = 0;
	}

	for(addr=0; addr<32; addr++){
		fail_unless(1 == gpc_handle_byte(addr | GP_MODE_READ | GP_MODE_PEEK | GP_MODE_RESERVED));
		fail_unless(0 == gpc_dummy_trigger_output_triggered);
		fail_unless((void *)0 == gpc_dummy_trigger_output_data);
		fail_unless(-1 == gpc_pickup_byte());
	}
}
Example #5
0
END_TEST

START_TEST(test_gprotc_read_cont)
{
	u16 addr = 0;

	for(addr=0; addr<32; addr++){
		fail_unless(0 == gpc_setup_reg(addr, &gpc_dummy_register_map[addr]));
	}

	for(addr=0; addr<32; addr++){
		gpc_dummy_register_map[addr] = addr | ((addr+1) << 8);
	}

	for(addr=0; addr<256; addr++){
		fail_unless(1 == gpc_register_touched(addr));
		fail_unless(0 == gpc_dummy_register_changed);
		fail_unless(0 == gpc_dummy_register_changed_addr);
		fail_unless((void *)0 == gpc_dummy_register_changed_data);
	}

	for(addr=0; addr<31; addr++){
		fail_unless(0 == gpc_handle_byte(addr | GP_MODE_READ | GP_MODE_CONT));
		fail_unless(0 == gpc_register_touched(addr));
		fail_unless(addr == gpc_pickup_byte());
		fail_unless(addr == gpc_pickup_byte());
		fail_unless(addr+1 == gpc_pickup_byte());
		fail_unless(-1 == gpc_pickup_byte());
		fail_unless(0 == gpc_handle_byte(addr | GP_MODE_READ | GP_MODE_CONT));
		fail_unless(1 == gpc_register_touched(addr));
		fail_unless(0 == gpc_dummy_register_changed);
		fail_unless(0 == gpc_dummy_register_changed_addr);
		fail_unless((void *)0 == gpc_dummy_register_changed_data);
	}
}
Example #6
0
/**
 * Commutation timer hardware initialization.
 */
void comm_tim_init(void)
{
	NVIC_InitTypeDef nvic;
	TIM_TimeBaseInitTypeDef tim_base;
	TIM_OCInitTypeDef tim_oc;

	comm_tim_data.freq = 65535;

	(void)gpc_setup_reg(GPROT_COMM_TIM_FREQ_REG_ADDR, &(comm_tim_data.freq));

	/* TIM2 clock enable */
	RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);

	/* Enable the TIM2 gloabal interrupt */
	nvic.NVIC_IRQChannel = TIM2_IRQn;
	nvic.NVIC_IRQChannelPreemptionPriority = 0;
	nvic.NVIC_IRQChannelSubPriority = 1;
	nvic.NVIC_IRQChannelCmd = ENABLE;

	NVIC_Init(&nvic);

	/* TIM2 time base configuration */
	tim_base.TIM_Period = 65535;
	tim_base.TIM_Prescaler = 0;
	tim_base.TIM_ClockDivision = 0;
	tim_base.TIM_CounterMode = TIM_CounterMode_Up;
	tim_base.TIM_RepetitionCounter = 0;

	TIM_TimeBaseInit(TIM2, &tim_base);

	/* TIM2 prescaler configuration */
	TIM_PrescalerConfig(TIM2, 4, TIM_PSCReloadMode_Immediate);

	/* TIM2 Output Compare Timing Mode configuration: Channel1 */
	tim_oc.TIM_OCMode = TIM_OCMode_Timing;
	tim_oc.TIM_OutputState = TIM_OutputState_Enable;
	tim_oc.TIM_Pulse = comm_tim_data.freq;
	tim_oc.TIM_OCPolarity = TIM_OCPolarity_High;

	/* Not necessary for TIM2 because it is not an advanced timer
	 * but we are trying to make lint happy here.
	 */
	tim_oc.TIM_OutputNState = TIM_OutputNState_Disable;
	tim_oc.TIM_OCNPolarity = TIM_OCNPolarity_High;
	tim_oc.TIM_OCIdleState = TIM_OCIdleState_Set;
	tim_oc.TIM_OCNIdleState = TIM_OCNIdleState_Set;

	TIM_OC1Init(TIM2, &tim_oc);

	TIM_OC1PreloadConfig(TIM2, TIM_OCPreload_Disable);

	/* TIM2 Capture Compare 1 IT enable */
	TIM_ITConfig(TIM2, TIM_IT_CC1, ENABLE);
	/* TIM2 Update IT enable */
	TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE);

	TIM_Cmd(TIM2, ENABLE);

	comm_tim_reset();
}
Example #7
0
GovernorClient::GovernorClient()
{
    int i;
    gpc_init(gpc_output_trigger, static_cast<void *>(this), gpc_register_changed, static_cast<void *>(this));
    for(i=0; i<32; i++){
        register_map[i] = 0;
        gpc_setup_reg(i, &register_map[i]);
    }
}
Example #8
0
/* Function implementations */
void gprot_init(){
	int i;

	gpc_init(gprot_trigger_output, 0, gprot_register_changed, 0);

	for(i=0; i<32; i++){
		test_regs[i] = i*3;
		if(gpc_setup_reg(i, &test_regs[i])){
			LED_RED_ON();
		}
	}

}
Example #9
0
void init_gprot_tc(void)
{
	int i;

	gpm_init(gpm_trigger_output_hook, NULL, gpm_register_changed_hook, NULL);

	gpc_init(gpc_trigger_output_hook, NULL, NULL, NULL);

	for(i=0; i<32; i++){
		gp_register_map[i] = 0xAA55+i;
		gpc_setup_reg(i, &gp_register_map[i]);
	}
}
Example #10
0
/**
 * Initialize the Governor protocol subsystem.
 */
void gprot_init()
{
	int i;

	(void)gpc_init(gprot_trigger_output, 0, gprot_register_changed, 0);
	(void)gpc_set_get_version_callback(gprot_get_version, 0);

	gprot_get_version_triggered = false;

	for (i = 0; i < 32; i++) {
		test_regs[i] = (u16)(i * 3);
		if (gpc_setup_reg((u8)i, &test_regs[i]) != 0) {
			ON(LED_RED);
		}
	}

}
Example #11
0
END_TEST

START_TEST(test_gprotc_handle_byte_write)
{
	u8 addr = 0;
	u16 data = 0xDADE;

	for(addr=0; addr<32; addr++){
		fail_unless(0 == gpc_setup_reg(addr, &gpc_dummy_register_map[addr]));
	}

	for(addr=0; addr<32; addr++){
		fail_unless(0 == gpc_handle_byte(addr | GP_MODE_WRITE));
		fail_unless(0 == gpc_handle_byte(data & 0xFF));
		fail_unless(0 == gpc_handle_byte(data >> 8));
		fail_unless(1 == gpc_dummy_register_changed);
		fail_unless(addr == gpc_dummy_register_changed_addr);
		fail_unless((void *)1 == gpc_dummy_register_changed_data);
		fail_unless(data == gpc_dummy_register_map[addr]);

		gpc_dummy_register_changed = 0;
		gpc_dummy_register_changed_addr = 0;
		gpc_dummy_register_changed_data = 0;
	}

	for(addr=0; addr<32; addr++){
		fail_unless(1 == gpc_handle_byte(addr | GP_MODE_WRITE | GP_MODE_RESERVED));
		fail_unless(0 == gpc_dummy_register_changed);
		fail_unless(0 == gpc_dummy_register_changed_addr);
		fail_unless((void *)0 == gpc_dummy_register_changed_data);
		fail_unless(-1 == gpc_pickup_byte());

		gpc_dummy_register_changed = 0;
		gpc_dummy_register_changed_addr = 0;
		gpc_dummy_register_changed_data = 0;
	}
}
Example #12
0
/**
 * Initialize the three phase (6outputs) PWM peripheral and internal state.
 */
void pwm_init(void)
{
	NVIC_InitTypeDef nvic;
	GPIO_InitTypeDef gpio;
	TIM_TimeBaseInitTypeDef tim_base;
	TIM_OCInitTypeDef tim_oc;
	TIM_BDTRInitTypeDef tim_bdtr;

	(void)gpc_setup_reg(GPROT_PWM_OFFSET_REG_ADDR, &pwm_offset);

	/* Enable clock for TIM1 subsystem */
	RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1 |
			       RCC_APB2Periph_GPIOA |
			       RCC_APB2Periph_GPIOB, ENABLE);

	/* Enable TIM1 interrupt */
	nvic.NVIC_IRQChannel = TIM1_TRG_COM_IRQn;
	nvic.NVIC_IRQChannelPreemptionPriority = 0;
	nvic.NVIC_IRQChannelSubPriority = 1;
	nvic.NVIC_IRQChannelCmd = ENABLE;
	NVIC_Init(&nvic);

	/* Enable TIM1 interrupt */
	nvic.NVIC_IRQChannel = TIM1_CC_IRQn;
	nvic.NVIC_IRQChannelPreemptionPriority = 0;
	nvic.NVIC_IRQChannelSubPriority = 1;
	nvic.NVIC_IRQChannelCmd = ENABLE;
	NVIC_Init(&nvic);

	/* GPIOA: TIM1 channel 1, 2 and 3 as alternate function
	   push-pull */
	gpio.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
	gpio.GPIO_Mode = GPIO_Mode_AF_PP;
	gpio.GPIO_Speed = GPIO_Speed_50MHz;
	GPIO_Init(GPIOA, &gpio);

	/* GPIOB: TIM1 channel 1N, 2N and 3N as alternate function
	 * push-pull
	 */
	gpio.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
	GPIO_Init(GPIOB, &gpio);

	/* Time base configuration */
	tim_base.TIM_Period = PWM__BASE_CLOCK / PWM__FREQUENCY;
	tim_base.TIM_Prescaler = 0;
	tim_base.TIM_ClockDivision = 0;
	tim_base.TIM_CounterMode = TIM_CounterMode_Up;
	tim_base.TIM_RepetitionCounter = 0;

	TIM_TimeBaseInit(TIM1, &tim_base);

	/* TIM1 channel 1, 2 and 3 settings */
	tim_oc.TIM_OCMode = TIM_OCMode_Timing;
	tim_oc.TIM_OutputState = TIM_OutputState_Enable;
	tim_oc.TIM_OutputNState = TIM_OutputNState_Enable;
	tim_oc.TIM_Pulse = pwm_val;
	tim_oc.TIM_OCPolarity = TIM_OCPolarity_High;
	tim_oc.TIM_OCNPolarity = TIM_OCNPolarity_High;
	tim_oc.TIM_OCIdleState = TIM_OCIdleState_Set;
	tim_oc.TIM_OCNIdleState = TIM_OCNIdleState_Set;

	TIM_OC1Init(TIM1, &tim_oc);
	TIM_OC1PreloadConfig(TIM1, TIM_OCPreload_Enable);
	TIM_OC2Init(TIM1, &tim_oc);
	TIM_OC2PreloadConfig(TIM1, TIM_OCPreload_Enable);
	TIM_OC3Init(TIM1, &tim_oc);
	TIM_OC3PreloadConfig(TIM1, TIM_OCPreload_Enable);

	/* TIM1 configure channel 4 as adc trigger source */
	tim_oc.TIM_OCMode = TIM_OCMode_PWM2;
	tim_oc.TIM_Pulse = pwm_offset;
	TIM_OC4PreloadConfig(TIM1, TIM_OCPreload_Enable);
	TIM_OC4Init(TIM1, &tim_oc);

	/* Automatic Output enable, break, dead time and lock configuration */
	tim_bdtr.TIM_OSSRState = TIM_OSSRState_Enable;
	tim_bdtr.TIM_OSSIState = TIM_OSSIState_Enable;
	tim_bdtr.TIM_LOCKLevel = TIM_LOCKLevel_OFF;
	tim_bdtr.TIM_DeadTime = 10;
	tim_bdtr.TIM_Break = TIM_Break_Disable;
	tim_bdtr.TIM_BreakPolarity = TIM_BreakPolarity_High;
	tim_bdtr.TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;

	TIM_BDTRConfig(TIM1, &tim_bdtr);

	TIM_CCPreloadControl(TIM1, ENABLE);

	/* Enable COM and CC interrupt */
	TIM_ITConfig(TIM1, TIM_IT_COM, ENABLE);
	//TIM_ITConfig(TIM1, TIM_IT_COM | TIM_IT_CC4, ENABLE);

	/* TIM1 enable counter */
	TIM_Cmd(TIM1, ENABLE);

	/* Main output enable */
	TIM_CtrlPWMOutputs(TIM1, ENABLE);

	/* Setting default state of pwm to pwm_off */
	pwm_off();
}
Example #13
0
/**
 * Commutation timer hardware initialization.
 */
void comm_tim_init(void)
{

	comm_tim_data.freq = 65535;

	(void)gpc_setup_reg(GPROT_COMM_TIM_FREQ_REG_ADDR, &(comm_tim_data.freq));

	/* TIM2 clock enable */
	rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM2EN);

	/* Enable the TIM2 gloabal interrupt. */
	nvic_enable_irq(NVIC_TIM2_IRQ);

	/* Reset TIM2 peripheral. */
	timer_reset(TIM2);

	/* TIM2 time base configuration */
	timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT,
		       TIM_CR1_CMS_EDGE,
		       TIM_CR1_DIR_UP);

	/* Set prescaler value */
	timer_set_prescaler(TIM2, 4);

	/* Disable preload. */
	timer_disable_preload(TIM2);

	/* Set continous mode. */
	timer_continuous_mode(TIM2);

	/* Set period to maximum */
	timer_set_period(TIM2, 65535);

	/* Disable outputs. */
	timer_disable_oc_output(TIM2, TIM_OC1);
	timer_disable_oc_output(TIM2, TIM_OC2);
	timer_disable_oc_output(TIM2, TIM_OC3);
	timer_disable_oc_output(TIM2, TIM_OC4);

	/* TIM2 Output Compare Timing Mode configuration: Channel1 */
	timer_disable_oc_clear(TIM2, TIM_OC1);
	timer_disable_oc_preload(TIM2, TIM_OC1);
	timer_set_oc_slow_mode(TIM2, TIM_OC1);
	timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN);
	//timer_set_oc_polarity_high(TIM2, TIM_OC1);

	/* Set initial capture compare value for OC1 */
	timer_set_oc_value(TIM2, TIM_OC1, comm_tim_data.freq);

	/* ARR reload enable */
	timer_disable_preload(TIM2);

	/* Counter enable */
	timer_enable_counter(TIM2);

	/* TIM2 Capture Compare 1 IT enable */
	timer_enable_irq(TIM2, TIM_DIER_CC1IE);
	/* TIM2 Update IT enable */
	timer_enable_irq(TIM2, TIM_DIER_UIE);

	comm_tim_reset();
}