void cts_task(void)
{
enum cts_rc rc;
int i;
gpio_enable_interrupt(GPIO_CTS_IRQ1);
gpio_enable_interrupt(GPIO_CTS_IRQ2);
interrupt_enable();
for (i = 0; i < CTS_TEST_ID_COUNT; i++) {
clear_state();
sync();
rc = tests[i].run();
interrupt_enable();
CPRINTF("\n%s %d\n", tests[i].name, rc);
cflush();
}
CPRINTS("Interrupt test suite finished");
cflush();
while (1) {
watchdog_reload();
sleep(1);
}
}
/* Initialize board. */
static void board_init(void)
{
/* Enable PD MCU interrupt */
gpio_enable_interrupt(GPIO_PD_MCU_INT);
/* Enable VBUS interrupt */
gpio_enable_interrupt(GPIO_USB_C0_VBUS_WAKE_L);
gpio_enable_interrupt(GPIO_USB_C1_VBUS_WAKE_L);
/* Enable pericom BC1.2 interrupts */
gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
/* Provide AC status to the PCH */
gpio_set_level(GPIO_PCH_ACOK, extpower_is_present());
/* Proto board workarounds */
if (system_get_board_version() == 0) {
/* Disable interrupt for SLP_S0 */
gpio_set_flags(GPIO_PCH_SLP_S0_L,
GPIO_INPUT | GPIO_PULL_DOWN);
/* Add internal pullup on PLATFORM_EC_PROCHOT */
gpio_set_flags(GPIO_PLATFORM_EC_PROCHOT,
GPIO_INPUT | GPIO_PULL_UP);
}
}
static void switch_init(void)
{
/* Set up memory-mapped switch positions */
memmap_switches = host_get_memmap(EC_MEMMAP_SWITCHES);
*memmap_switches = 0;
switch_update();
/* Switch data is now present */
*host_get_memmap(EC_MEMMAP_SWITCHES_VERSION) = 1;
#ifdef CONFIG_SWITCH_DEDICATED_RECOVERY
/* Enable interrupts, now that we've initialized */
gpio_enable_interrupt(GPIO_RECOVERY_L);
#endif
/*
* TODO(crosbug.com/p/23793): It's weird that flash_common.c owns
* reading the write protect signal, but we enable the interrupt for it
* here. Take ownership of WP back, or refactor it to its own module.
*/
#ifdef CONFIG_WP_ACTIVE_HIGH
gpio_enable_interrupt(GPIO_WP);
#else
gpio_enable_interrupt(GPIO_WP_L);
#endif
}
/* Initialize board. */
static void board_init(void)
{
/* Enable PD MCU interrupt */
gpio_enable_interrupt(GPIO_PD_MCU_INT);
/* Enable VBUS interrupt */
gpio_enable_interrupt(GPIO_USB_C0_VBUS_WAKE_L);
/* Enable pericom BC1.2 interrupts */
gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
}
/* Initialize board. */
static void board_init(void)
{
int i, bc12_status;
struct charge_port_info charge_none, charge_vbus;
struct charge_port_info *charge_sel;
/* Enable rev1 testing GPIOs */
gpio_set_level(GPIO_SYSTEM_POWER_H, 1);
/* Enable PD MCU interrupt */
gpio_enable_interrupt(GPIO_PD_MCU_INT);
/* Enable VBUS interrupt */
gpio_enable_interrupt(GPIO_VBUS_WAKE_L);
charge_none.voltage = USB_CHARGER_VOLTAGE_MV;
charge_none.current = 0;
charge_vbus.voltage = USB_CHARGER_VOLTAGE_MV;
charge_vbus.current = USB_CHARGER_MIN_CURR_MA;
for (i = 0; i < CONFIG_USB_PD_PORT_COUNT; i++) {
/* Initialize all pericom charge suppliers to 0 */
charge_manager_update_charge(
CHARGE_SUPPLIER_PROPRIETARY,
i,
&charge_none);
charge_manager_update_charge(
CHARGE_SUPPLIER_BC12_CDP,
i,
&charge_none);
charge_manager_update_charge(
CHARGE_SUPPLIER_BC12_DCP,
i,
&charge_none);
charge_manager_update_charge(
CHARGE_SUPPLIER_BC12_SDP,
i,
&charge_none);
charge_manager_update_charge(
CHARGE_SUPPLIER_OTHER,
i,
&charge_none);
/* Initialize VBUS supplier based on VBUS */
/* TODO(crbug.com/498974): Don't do i2c from hook_init. */
bc12_status = pi3usb9281_get_charger_status(i);
charge_sel = PI3USB9281_CHG_STATUS_ANY(bc12_status) ?
&charge_vbus : &charge_none;
charge_manager_update_charge(
CHARGE_SUPPLIER_VBUS,
i,
charge_sel);
}
}
/* Initialize board. */
static void board_init(void)
{
/* Enable PD MCU interrupt */
gpio_enable_interrupt(GPIO_PD_MCU_INT);
/* Enable VBUS interrupt */
gpio_enable_interrupt(GPIO_USB_C0_VBUS_WAKE_L);
/* Enable pericom BC1.2 interrupts */
gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
/* Provide AC status to the PCH */
gpio_set_level(GPIO_PCH_ACOK, extpower_is_present());
}
static void siglog_deferred(void)
{
const struct gpio_info *g = gpio_list;
unsigned int i;
timestamp_t tdiff = {.val = 0};
/* Disable interrupts for input signals while we print stuff.*/
for (i = 0; i < POWER_SIGNAL_COUNT; i++)
gpio_disable_interrupt(power_signal_list[i].gpio);
CPRINTF("%d signal changes:\n", siglog_entries);
for (i = 0; i < siglog_entries; i++) {
if (i)
tdiff.val = siglog[i].time.val - siglog[i-1].time.val;
CPRINTF(" %.6ld +%.6ld %s => %d\n",
siglog[i].time.val, tdiff.val,
g[siglog[i].signal].name,
siglog[i].level);
}
if (siglog_truncated)
CPRINTF(" SIGNAL LOG TRUNCATED...\n");
siglog_entries = siglog_truncated = 0;
/* Okay, turn 'em on again. */
for (i = 0; i < POWER_SIGNAL_COUNT; i++)
gpio_enable_interrupt(power_signal_list[i].gpio);
}
DECLARE_DEFERRED(siglog_deferred);
static void siglog_add(enum gpio_signal signal)
{
if (siglog_entries >= MAX_SIGLOG_ENTRIES) {
siglog_truncated = 1;
return;
}
siglog[siglog_entries].time = get_time();
siglog[siglog_entries].signal = signal;
siglog[siglog_entries].level = gpio_get_level(signal);
siglog_entries++;
hook_call_deferred(siglog_deferred, SECOND);
}
#define SIGLOG(S) siglog_add(S)
#else
#define SIGLOG(S)
#endif /* CONFIG_BRINGUP */
void power_signal_interrupt(enum gpio_signal signal)
{
SIGLOG(signal);
/* Shadow signals and compare with our desired signal state. */
power_update_signals();
/* Wake up the task */
task_wake(TASK_ID_CHIPSET);
}
static void spi_init(void)
{
stm32_spi_regs_t *spi = STM32_SPI1_REGS;
/* Reset the SPI Peripheral to clear any existing weird states. */
/* Fix for bug chrome-os-partner:31390 */
enabled = 0;
state = SPI_STATE_DISABLED;
STM32_RCC_APB2RSTR |= (1 << 12);
STM32_RCC_APB2RSTR &= ~(1 << 12);
/* 40 MHz pin speed */
STM32_GPIO_OSPEEDR(GPIO_A) |= 0xff00;
/* Enable clocks to SPI1 module */
STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
/*
* Enable rx/tx DMA and get ready to receive our first transaction and
* "disable" FIFO by setting event to happen after only 1 byte
*/
spi->cr2 = STM32_SPI_CR2_RXDMAEN | STM32_SPI_CR2_TXDMAEN |
STM32_SPI_CR2_FRXTH;
/* Enable the SPI peripheral */
spi->cr1 |= STM32_SPI_CR1_SPE;
gpio_enable_interrupt(GPIO_SPI1_NSS);
/* If chipset is already on, prepare for transactions */
if (chipset_in_state(CHIPSET_STATE_ON))
spi_chipset_startup();
}
static enum cts_rc timer_calibration_test(void)
{
/* Error margin: +/-2 msec (0.2% for one second) */
const int32_t margin = 2 * MSEC;
int32_t elapsed, delta;
timestamp_t t0, t1;
gpio_enable_interrupt(GPIO_CTS_NOTIFY);
interrupt_enable();
sync();
t0 = get_time();
/* Wait for interrupt */
task_wait_event(-1);
t1 = get_time();
elapsed = (int32_t)(t1.val - t0.val);
delta = elapsed - SECOND;
if (delta < -margin) {
CPRINTS("DUT clock runs too fast: %+d usec", delta);
return CTS_RC_FAILURE;
}
if (margin < delta) {
CPRINTS("DUT clock runs too slow: %+d usec", delta);
return CTS_RC_FAILURE;
}
return CTS_RC_SUCCESS;
}
static void extpower_init(void)
{
extpower_buffer_to_soc();
/* Enable interrupts, now that we've initialized */
gpio_enable_interrupt(GPIO_AC_PRESENT);
}
/* Initialize board. */
static void board_init(void)
{
/* FIXME: Handle tablet mode */
/* gpio_enable_interrupt(GPIO_TABLET_MODE_L); */
/* Enable charger interrupts */
gpio_enable_interrupt(GPIO_CHARGER_INT_L);
}
/**
* Initialize backlight module.
*/
static void backlight_init(void)
{
update_backlight();
#ifdef CONFIG_BACKLIGHT_REQ_GPIO
gpio_enable_interrupt(CONFIG_BACKLIGHT_REQ_GPIO);
#endif
}
/**
* Handle power button initialization.
*/
static void power_button_init(void)
{
if (raw_power_button_pressed())
debounced_power_pressed = 1;
/* Enable interrupts, now that we've initialized */
gpio_enable_interrupt(GPIO_POWER_BUTTON_L);
}
/* Initialize board. */
static void board_init(void)
{
timestamp_t now = get_time();
hpd_prev_level = gpio_get_level(GPIO_DP_HPD);
hpd_prev_ts = now.val;
gpio_enable_interrupt(GPIO_DP_HPD);
gpio_set_level(GPIO_STM_READY, 1); /* factory test only */
}
static void init_interrupts(void)
{
int i;
/* Enable all GPIO interrupts */
for (i = 0; i < gpio_ih_count; i++)
if (gpio_list[i].flags & GPIO_INT_ANY)
gpio_enable_interrupt(i);
}
/******************************************************************************
* Initialize board.
*/
static void board_init(void)
{
gpio_enable_interrupt(GPIO_USER_BUTTON);
queue_init(&loopback_queue);
queue_init(&usart_to_usb);
queue_init(&usb_to_usart);
usart_init(&loopback_usart);
usart_init(&forward_usart);
usb_spi_enable(&usb_spi, 1);
}
void elan_tp_task(void)
{
elan_tp_init();
gpio_enable_interrupt(GPIO_TOUCHPAD_INT);
while (1) {
task_wait_event(-1);
elan_tp_read_report();
}
}
void board_tcpc_init(void)
{
int port, reg;
/* Only reset TCPC if not sysjump */
if (!system_jumped_to_this_image())
board_reset_pd_mcu();
/*
* TODO: Remove when Reef is updated with PS8751 A3.
*
* Force PS8751 A2 to wake from low power mode.
* If PS8751 remains in low power mode after sysjump,
* TCPM_INIT will fail due to not able to access PS8751.
*
* NOTE: PS8751 A3 will wake on any I2C access.
*/
i2c_read8(NPCX_I2C_PORT0_1, 0x10, 0xA0, ®);
/* Enable TCPC0 interrupt */
gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
/* Enable TCPC1 interrupt */
gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
/* Enable CABLE_DET interrupt for ANX3429 wake from standby */
gpio_enable_interrupt(GPIO_USB_C0_CABLE_DET);
#endif
/*
* Initialize HPD to low; after sysjump SOC needs to see
* HPD pulse to enable video path
*/
for (port = 0; port < CONFIG_USB_PD_PORT_COUNT; port++) {
const struct usb_mux *mux = &usb_muxes[port];
mux->hpd_update(port, 0, 0);
}
}
void accel_gpio_init(void)
{
//gpio_pull_set(ACCEL_INT_PIN, GPIO_PULL_DOWN);
gpio_set_direction_field(ACCEL_INT_PIN, GPIO_INPUT);
gpio_set_interrupt(ACCEL_INT_PIN, GPIO_INT_RISING_EDGE);
gpio_enable_interrupt(ACCEL_INT_PIN);
//Accelerometer interrupt
//wakeup_by_gpio(ACCEL_INT_PIN, GPIO_WKUP_BY_HIGH); // does gpio_wakeup_config automatically
gpio_wakeup_config(ACCEL_INT_PIN, GPIO_WKUP_BY_HIGH); //sets direction to input automatically
}
/*
* configures switch as interrupt
*/
void uc_sw_init_int(switch_t p_switch, callback_t p_callback)
{
if(p_switch == switch_1)
{
//setup GPIO for relevant pin
gpio_port_init(port_C, pin_3, alt_1, input);
//enable pullup res
PORTC_PCR3 |= 1 << 1;
gpio_enable_interrupt(port_C, pin_3, trig_int_negedge, p_callback);
}
if(p_switch == switch_3)
{
gpio_port_init(port_C, pin_12, alt_1, input);
PORTC_PCR12 |= 1 << 1;
gpio_enable_interrupt(port_C, pin_12, trig_int_negedge, p_callback);
}
}
/* Initialize board. */
static void board_init(void)
{
int i;
/* Initialize all BC1.2 charge suppliers to 0 */
for (i = 0; i < CONFIG_USB_PD_PORT_COUNT; i++)
reset_charge(i);
/* Enable charge status interrupt */
gpio_enable_interrupt(GPIO_CHARGE_STATUS);
/* Initialize VBUS supplier based on whether or not VBUS is present */
update_vbus_supplier(gpio_get_level(GPIO_AC_PRESENT));
}
/* Initialize board. */
static void board_init(void)
{
timestamp_t now;
#ifdef CONFIG_SPI_FLASH
board_init_spi2();
#endif
now = get_time();
hpd_prev_level = gpio_get_level(GPIO_DP_HPD);
hpd_prev_ts = now.val;
gpio_enable_interrupt(GPIO_DP_HPD);
gpio_set_level(GPIO_STM_READY, 1); /* factory test only */
/* Delay needed to allow HDMI MCU to boot. */
hook_call_deferred(factory_validation_deferred, 200*MSEC);
}
static void extpower_init(void)
{
uint8_t *memmap_batt_flags = host_get_memmap(EC_MEMMAP_BATT_FLAG);
debounced_extpower_presence = gpio_get_level(GPIO_AC_PRESENT);
/* Initialize the memory-mapped AC_PRESENT flag */
if (debounced_extpower_presence)
*memmap_batt_flags |= EC_BATT_FLAG_AC_PRESENT;
else
*memmap_batt_flags &= ~EC_BATT_FLAG_AC_PRESENT;
/* Enable interrupts, now that we've initialized */
gpio_enable_interrupt(GPIO_AC_PRESENT);
}
/**
****************************************************************************************
* @brief Set GPIO wakeup
* @param[in] pin wakeup pin: P0 and P1
* @param[in] type Wakeup type: high, low, change
* @description
* This function is used to set MCU wakeup by gpio pin.
*****************************************************************************************
*/
void wakeup_by_gpio(enum gpio_pin pin, enum gpio_wakeup_type type)
{
if (sleep_env.wakeup_by_sleeptimer == 0) {
// Disable sleep timer wakeup
syscon_SetPGCR2WithMask(QN_SYSCON, SYSCON_MASK_OSC_WAKEUP_EN, MASK_DISABLE);
}
// configure gpio wakeup pin
gpio_wakeup_config(pin, type);
gpio_enable_interrupt(pin);
// Ensure gpio interrupt is not pending before the test
NVIC_ClearPendingIRQ(GPIO_IRQn);
// Enable Interrupts
NVIC_EnableIRQ(GPIO_IRQn);
}
/**
* Initialize panel module.
*/
static void panel_init(void)
{
/* Set initial deferred value and signal to the current PCH signal. */
backlight_deferred_value = gpio_get_level(GPIO_PCH_BKLTEN);
set_backlight_value();
update_backlight();
gpio_enable_interrupt(GPIO_PCH_BKLTEN);
/* The interrupt is enabled for the GPIO_PCH_EDP_VDD_EN in the
* chipset_haswell.c compilation unit. Initially set the value
* to whatever it current is reading. */
lcdvcc_en_deferred_value = gpio_get_level(GPIO_PCH_EDP_VDD_EN);
set_lcdvcc_en_value();
}
/*
****************************************************************************************
* @brief com_gpio_init
* @param[in] None
* @response None
* @return None
* @description Init GPIO and Init the event and it's callback function
*****************************************************************************************/
void com_gpio_init(void)
{
//set wakeup config,when GPIO low and trigger interrupt
gpio_wakeup_config(COM_AT_ENABLE,GPIO_WKUP_BY_LOW);
gpio_enable_interrupt(COM_AT_ENABLE);
if(KE_EVENT_OK != ke_evt_callback_set(EVENT_AT_ENABLE_PRESS_ID,
app_event_at_enable_press_handler))
{
ASSERT_ERR(0);
}
if(KE_EVENT_OK != ke_evt_callback_set(EVENT_AT_COMMAND_PROC_ID,
app_com_at_command_handler))
{
ASSERT_ERR(0);
}
}
static void power_common_init(void)
{
const struct power_signal_info *s = power_signal_list;
int i;
/* Update input state */
power_update_signals();
/* Call chipset-specific init to set initial state */
power_set_state(power_chipset_init());
/* Enable interrupts for input signals */
for (i = 0; i < POWER_SIGNAL_COUNT; i++, s++)
gpio_enable_interrupt(s->gpio);
/*
* Update input state again since there is a small window
* before GPIO is enabled.
*/
power_update_signals();
}
void system_hibernate(uint32_t seconds, uint32_t microseconds)
{
int i;
#ifdef CONFIG_HOSTCMD_PD
/* Inform the PD MCU that we are going to hibernate. */
host_command_pd_request_hibernate();
/* Wait to ensure exchange with PD before hibernating. */
msleep(100);
#endif
cflush();
if (board_hibernate)
board_hibernate();
/* Disable interrupts */
interrupt_disable();
for (i = 0; i <= 92; ++i) {
task_disable_irq(i);
task_clear_pending_irq(i);
}
for (i = 8; i <= 23; ++i)
MEC1322_INT_DISABLE(i) = 0xffffffff;
MEC1322_INT_BLK_DIS |= 0xffff00;
/* Power down ADC VREF */
MEC1322_EC_ADC_VREF_PD |= 1;
/* Assert nSIO_RESET */
MEC1322_PCR_PWR_RST_CTL |= 1;
/* Disable UART */
MEC1322_UART_ACT &= ~0x1;
MEC1322_LPC_ACT &= ~0x1;
/* Disable JTAG */
MEC1322_EC_JTAG_EN &= ~1;
/* Disable 32KHz clock */
MEC1322_VBAT_CE &= ~0x2;
/* Stop watchdog */
MEC1322_WDG_CTL &= ~1;
/* Stop timers */
MEC1322_TMR32_CTL(0) &= ~1;
MEC1322_TMR32_CTL(1) &= ~1;
MEC1322_TMR16_CTL(0) &= ~1;
/* Power down ADC */
MEC1322_ADC_CTRL &= ~1;
/* Disable blocks */
MEC1322_PCR_CHIP_SLP_EN |= 0x3;
MEC1322_PCR_EC_SLP_EN |= MEC1322_PCR_EC_SLP_EN_SLEEP;
MEC1322_PCR_HOST_SLP_EN |= MEC1322_PCR_HOST_SLP_EN_SLEEP;
MEC1322_PCR_EC_SLP_EN2 |= MEC1322_PCR_EC_SLP_EN2_SLEEP;
MEC1322_PCR_SLOW_CLK_CTL &= 0xfffffc00;
/* Set sleep state */
MEC1322_PCR_SYS_SLP_CTL = (MEC1322_PCR_SYS_SLP_CTL & ~0x7) | 0x2;
CPU_SCB_SYSCTRL |= 0x4;
/* Setup GPIOs for hibernate */
if (board_hibernate_late)
board_hibernate_late();
#ifdef CONFIG_USB_PD_PORT_COUNT
/*
* Leave USB-C charging enabled in hibernate, in order to
* allow wake-on-plug. 5V enable must be pulled low.
*/
#if CONFIG_USB_PD_PORT_COUNT > 0
gpio_set_flags(GPIO_USB_C0_5V_EN, GPIO_PULL_DOWN | GPIO_INPUT);
gpio_set_level(GPIO_USB_C0_CHARGE_EN_L, 0);
#endif
#if CONFIG_USB_PD_PORT_COUNT > 1
gpio_set_flags(GPIO_USB_C1_5V_EN, GPIO_PULL_DOWN | GPIO_INPUT);
gpio_set_level(GPIO_USB_C1_CHARGE_EN_L, 0);
#endif
#endif /* CONFIG_USB_PD_PORT_COUNT */
if (hibernate_wake_pins_used > 0) {
for (i = 0; i < hibernate_wake_pins_used; ++i) {
const enum gpio_signal pin = hibernate_wake_pins[i];
gpio_reset(pin);
gpio_enable_interrupt(pin);
}
interrupt_enable();
task_enable_irq(MEC1322_IRQ_GIRQ8);
task_enable_irq(MEC1322_IRQ_GIRQ9);
task_enable_irq(MEC1322_IRQ_GIRQ10);
task_enable_irq(MEC1322_IRQ_GIRQ11);
task_enable_irq(MEC1322_IRQ_GIRQ20);
}
if (seconds || microseconds) {
MEC1322_INT_BLK_EN |= 1 << 17;
MEC1322_INT_ENABLE(17) |= 1 << 20;
interrupt_enable();
task_enable_irq(MEC1322_IRQ_HTIMER);
if (seconds > 2) {
ASSERT(seconds <= 0xffff / 8);
MEC1322_HTIMER_CONTROL = 1;
MEC1322_HTIMER_PRELOAD =
(seconds * 8 + microseconds / 125000);
} else {
MEC1322_HTIMER_CONTROL = 0;
MEC1322_HTIMER_PRELOAD =
(seconds * 1000000 + microseconds) * 2 / 71;
}
}
asm("wfi");
/* Use 48MHz clock to speed through wake-up */
MEC1322_PCR_PROC_CLK_CTL = 1;
/* Reboot */
_system_reset(0, 1);
/* We should never get here. */
while (1)
;
}
static void lpc_init(void)
{
/*
* DLM 52k~56k size select enable.
* For mapping LPC I/O cycle 800h ~ 9FFh to DLM 8D800 ~ 8D9FF.
*/
IT83XX_GCTRL_MCCR2 |= 0x10;
IT83XX_GPIO_GCR = 0x06;
/* The register pair to access PNPCFG is 004Eh and 004Fh */
IT83XX_GCTRL_BADRSEL = 0x01;
/* Disable KBC IRQ */
IT83XX_KBC_KBIRQR = 0x00;
/*
* bit2, Output Buffer Empty CPU Interrupt Enable.
* bit3, Input Buffer Full CPU Interrupt Enable.
*/
IT83XX_KBC_KBHICR |= 0x0C;
/* PM1 Input Buffer Full Interrupt Enable for 62h/66 port */
pm_set_ctrl(LPC_ACPI_CMD, PM_CTRL_IBFIE, 1);
/* PM2 Input Buffer Full Interrupt Enable for 200h/204 port */
pm_set_ctrl(LPC_HOST_CMD, PM_CTRL_IBFIE, 1);
memset(lpc_get_memmap_range(), 0, EC_MEMMAP_SIZE);
memset(lpc_host_args, 0, sizeof(*lpc_host_args));
/* Host LPC I/O cycle mapping to RAM */
/*
* bit[4], H2RAM through LPC IO cycle.
* bit[1], H2RAM window 1 enabled.
* bit[0], H2RAM window 0 enabled.
*/
IT83XX_SMFI_HRAMWC |= 0x13;
/*
* bit[7:6]
* Host RAM Window[x] Read Protect Enable
* 00b: Disabled
* 01b: Lower half of RAM window protected
* 10b: Upper half of RAM window protected
* 11b: All protected
*
* bit[5:4]
* Host RAM Window[x] Write Protect Enable
* 00b: Disabled
* 01b: Lower half of RAM window protected
* 10b: Upper half of RAM window protected
* 11b: All protected
*
* bit[2:0]
* Host RAM Window 1 Size (HRAMW1S)
* 0h: 16 bytes
* 1h: 32 bytes
* 2h: 64 bytes
* 3h: 128 bytes
* 4h: 256 bytes
* 5h: 512 bytes
* 6h: 1024 bytes
* 7h: 2048 bytes
*/
/* H2RAM Win 0 Base Address 800h allow r/w for host_cmd_memmap */
IT83XX_SMFI_HRAMW0BA = 0x80;
IT83XX_SMFI_HRAMW0AAS = 0x04;
/* H2RAM Win 1 Base Address 900h allow r for acpi_ec_memmap */
IT83XX_SMFI_HRAMW1BA = 0x90;
IT83XX_SMFI_HRAMW1AAS = 0x34;
/* We support LPC args and version 3 protocol */
*(lpc_get_memmap_range() + EC_MEMMAP_HOST_CMD_FLAGS) =
EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED |
EC_HOST_CMD_FLAG_VERSION_3;
/*
* bit[5], Dedicated interrupt
* INT3: PMC1 Output Buffer Empty Int
* INT25: PMC1 Input Buffer Full Int
* INT26: PMC2 Output Buffer Empty Int
* INT27: PMC2 Input Buffer Full Int
*/
IT83XX_PMC_MBXCTRL |= 0x20;
/* PM3 Input Buffer Full Interrupt Enable for 80h port */
pm_set_ctrl(LPC_HOST_PORT_80H, PM_CTRL_IBFIE, 1);
gpio_enable_interrupt(GPIO_PCH_PLTRST_L);
task_clear_pending_irq(IT83XX_IRQ_KBC_OUT);
task_disable_irq(IT83XX_IRQ_KBC_OUT);
task_clear_pending_irq(IT83XX_IRQ_KBC_IN);
task_enable_irq(IT83XX_IRQ_KBC_IN);
task_clear_pending_irq(IT83XX_IRQ_PMC_IN);
task_enable_irq(IT83XX_IRQ_PMC_IN);
task_clear_pending_irq(IT83XX_IRQ_PMC2_IN);
task_enable_irq(IT83XX_IRQ_PMC2_IN);
task_clear_pending_irq(IT83XX_IRQ_PMC3_IN);
task_enable_irq(IT83XX_IRQ_PMC3_IN);
/* Sufficiently initialized */
init_done = 1;
/* Update host events now that we can copy them to memmap */
update_host_event_status();
}
void system_hibernate(uint32_t seconds, uint32_t microseconds)
{
int i;
cflush();
/* Disable interrupts */
interrupt_disable();
for (i = 0; i <= 92; ++i) {
task_disable_irq(i);
task_clear_pending_irq(i);
}
for (i = 8; i <= 23; ++i)
MEC1322_INT_DISABLE(i) = 0xffffffff;
MEC1322_INT_BLK_DIS |= 0xffff00;
/* Set processor clock to lowest, 1MHz */
MEC1322_PCR_PROC_CLK_CTL = 48;
/* Power down ADC VREF */
MEC1322_EC_ADC_VREF_PD |= 1;
/* Assert nSIO_RESET */
MEC1322_PCR_PWR_RST_CTL |= 1;
/* Disable UART */
MEC1322_UART_ACT &= ~0x1;
MEC1322_LPC_ACT &= ~0x1;
/* Disable JTAG */
MEC1322_EC_JTAG_EN &= ~1;
/* Disable 32KHz clock */
MEC1322_VBAT_CE &= ~0x2;
/* Stop watchdog */
MEC1322_WDG_CTL &= ~1;
/* Stop timers */
MEC1322_TMR32_CTL(0) &= ~1;
MEC1322_TMR32_CTL(1) &= ~1;
MEC1322_TMR16_CTL(0) &= ~1;
/* Power down ADC */
MEC1322_ADC_CTRL &= ~1;
/* Disable blocks */
MEC1322_PCR_CHIP_SLP_EN |= 0x3;
MEC1322_PCR_EC_SLP_EN |= 0xe0700ff7;
MEC1322_PCR_HOST_SLP_EN |= 0x5f003;
MEC1322_PCR_EC_SLP_EN2 |= 0x1ffffff8;
MEC1322_PCR_SYS_SLP_CTL = (MEC1322_PCR_SYS_SLP_CTL & ~0x7) | 0x2;
MEC1322_PCR_SLOW_CLK_CTL &= 0xfffffc00;
CPU_SCB_SYSCTRL |= 0x4;
system_unpower_gpio();
#ifdef CONFIG_WAKE_PIN
gpio_set_flags_by_mask(gpio_list[CONFIG_WAKE_PIN].port,
gpio_list[CONFIG_WAKE_PIN].mask,
gpio_list[CONFIG_WAKE_PIN].flags);
gpio_enable_interrupt(CONFIG_WAKE_PIN);
interrupt_enable();
task_enable_irq(MEC1322_IRQ_GIRQ8);
task_enable_irq(MEC1322_IRQ_GIRQ9);
task_enable_irq(MEC1322_IRQ_GIRQ10);
task_enable_irq(MEC1322_IRQ_GIRQ11);
task_enable_irq(MEC1322_IRQ_GIRQ20);
#endif
if (seconds || microseconds) {
MEC1322_INT_BLK_EN |= 1 << 17;
MEC1322_INT_ENABLE(17) |= 1 << 20;
interrupt_enable();
task_enable_irq(MEC1322_IRQ_HTIMER);
if (seconds > 2) {
ASSERT(seconds <= 0xffff / 8);
MEC1322_HTIMER_CONTROL = 1;
MEC1322_HTIMER_PRELOAD =
(seconds * 8 + microseconds / 125000);
} else {
MEC1322_HTIMER_CONTROL = 0;
MEC1322_HTIMER_PRELOAD =
(seconds * 1000000 + microseconds) * 2 / 71;
}
}
asm("wfi");
/* We lost states of most modules, let's just reboot */
_system_reset(0, 1);
}
