static int do_mmc_init(int dev_index, bool removable)
{
struct mmc_host *host;
struct mmc *mmc;
/* DT should have been read & host config filled in */
host = &mmc_host[dev_index];
if (!host->enabled)
return -1;
debug(" do_mmc_init: index %d, bus width %d pwr_gpio %d cd_gpio %d\n",
dev_index, host->width, gpio_get_number(&host->pwr_gpio),
gpio_get_number(&host->cd_gpio));
host->clock = 0;
clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
if (dm_gpio_is_valid(&host->pwr_gpio))
dm_gpio_set_value(&host->pwr_gpio, 1);
memset(&host->cfg, 0, sizeof(host->cfg));
host->cfg.name = "Tegra SD/MMC";
host->cfg.ops = &tegra_mmc_ops;
host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
host->cfg.host_caps = 0;
if (host->width == 8)
host->cfg.host_caps |= MMC_MODE_8BIT;
if (host->width >= 4)
host->cfg.host_caps |= MMC_MODE_4BIT;
host->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
/*
* min freq is for card identification, and is the highest
* low-speed SDIO card frequency (actually 400KHz)
* max freq is highest HS eMMC clock as per the SD/MMC spec
* (actually 52MHz)
*/
host->cfg.f_min = 375000;
host->cfg.f_max = 48000000;
host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
mmc = mmc_create(&host->cfg, host);
mmc->block_dev.removable = removable;
if (mmc == NULL)
return -1;
return 0;
}
static void board_enable_audio_codec(void)
{
int node, ret;
struct gpio_desc en_gpio;
node = fdtdec_next_compatible(gd->fdt_blob, 0,
COMPAT_SAMSUNG_EXYNOS5_SOUND);
if (node <= 0)
return;
ret = gpio_request_by_name_nodev(gd->fdt_blob, node,
"codec-enable-gpio", 0, &en_gpio,
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
if (ret == -FDT_ERR_NOTFOUND)
return;
/* Turn on the GPIO which connects to the codec's "enable" line. */
gpio_set_pull(gpio_get_number(&en_gpio), S5P_GPIO_PULL_NONE);
#ifdef CONFIG_SOUND_MAX98095
/* Enable MAX98095 Codec */
gpio_request(EXYNOS5_GPIO_X17, "max98095_enable");
gpio_direction_output(EXYNOS5_GPIO_X17, 1);
gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE);
#endif
}
/* Set up VBUS for host/device mode */
static void set_up_vbus(struct fdt_usb *config, enum usb_init_type init)
{
/*
* If we are an OTG port initializing in host mode,
* check if remote host is driving VBus and bail out in this case.
*/
if (init == USB_INIT_HOST &&
config->dr_mode == DR_MODE_OTG &&
(readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) {
printf("tegrausb: VBUS input active; not enabling as host\n");
return;
}
if (dm_gpio_is_valid(&config->vbus_gpio)) {
int vbus_value;
vbus_value = (init == USB_INIT_HOST);
dm_gpio_set_value(&config->vbus_gpio, vbus_value);
debug("set_up_vbus: GPIO %d %d\n",
gpio_get_number(&config->vbus_gpio), vbus_value);
}
}
int display_init(void *lcdbase, int fb_bits_per_pixel,
struct display_timing *timing)
{
struct dc_ctlr *dc_ctlr;
const void *blob = gd->fdt_blob;
struct udevice *dp_dev;
const int href_to_sync = 1, vref_to_sync = 1;
int panel_bpp = 18; /* default 18 bits per pixel */
u32 plld_rate;
struct gpio_desc vdd_gpio, enable_gpio;
int pwm;
int node;
int ret;
ret = uclass_get_device(UCLASS_DISPLAY, 0, &dp_dev);
if (ret)
return ret;
node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_DC);
if (node < 0)
return -ENOENT;
dc_ctlr = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
if (fdtdec_decode_display_timing(blob, node, 0, timing))
return -EINVAL;
ret = display_update_config_from_edid(dp_dev, &panel_bpp, timing);
if (ret) {
debug("%s: Failed to decode EDID, using defaults\n", __func__);
dump_config(panel_bpp, timing);
}
if (!get_backlight_info(blob, &vdd_gpio, &enable_gpio, &pwm)) {
dm_gpio_set_value(&vdd_gpio, 1);
debug("%s: backlight vdd setting gpio %08x to %d\n",
__func__, gpio_get_number(&vdd_gpio), 1);
}
/*
* The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER
* and PIXEL_CLK_DIVIDER are zero (divide by 1). See the
* update_display_mode() for detail.
*/
plld_rate = clock_set_display_rate(timing->pixelclock.typ * 2);
if (plld_rate == 0) {
printf("dc: clock init failed\n");
return -EIO;
} else if (plld_rate != timing->pixelclock.typ * 2) {
debug("dc: plld rounded to %u\n", plld_rate);
timing->pixelclock.typ = plld_rate / 2;
}
/* Init dc */
ret = tegra_dc_init(dc_ctlr);
if (ret) {
debug("dc: init failed\n");
return ret;
}
/* Configure dc mode */
ret = update_display_mode(dc_ctlr, timing, href_to_sync, vref_to_sync);
if (ret) {
debug("dc: failed to configure display mode\n");
return ret;
}
/* Enable dp */
ret = display_enable(dp_dev, panel_bpp, timing);
if (ret)
return ret;
ret = update_window(dc_ctlr, (ulong)lcdbase, fb_bits_per_pixel, timing);
if (ret)
return ret;
/* Set up Tegra PWM to drive the panel backlight */
pwm_enable(pwm, 0, 220, 0x2e);
udelay(10 * 1000);
if (dm_gpio_is_valid(&enable_gpio)) {
dm_gpio_set_value(&enable_gpio, 1);
debug("%s: backlight enable setting gpio %08x to %d\n",
__func__, gpio_get_number(&enable_gpio), 1);
}
return 0;
}
