/*
* Routine: board_init
* Description: Early hardware init.
*/
int board_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* board id for Linux */
gd->bd->bi_arch_number = MACH_TYPE_OVERO;
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
return 0;
}
static void __init omap3_stalker_init_irq(void)
{
omap_board_config = omap3_stalker_config;
omap_board_config_size = ARRAY_SIZE(omap3_stalker_config);
omap2_init_common_infrastructure();
omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
omap_init_irq();
gpmc_init();
#ifdef CONFIG_OMAP_32K_TIMER
omap2_gp_clockevent_set_gptimer(12);
#endif
}
static void __init omap_4430sdp_init_irq(void)
{
omap_board_config = sdp4430_config;
omap_board_config_size = ARRAY_SIZE(sdp4430_config);
omap2_init_common_infrastructure();
omap2_init_common_devices(NULL, NULL);
#ifdef CONFIG_OMAP_32K_TIMER
omap2_gp_clockevent_set_gptimer(1);
#endif
gic_init_irq();
gpmc_init();
}
/*
* Basic board specific setup. Pinmux has been handled already.
*/
int board_init(void)
{
#if defined(CONFIG_HW_WATCHDOG)
hw_watchdog_init();
#endif
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
gpmc_init();
#endif
return 0;
}
static void __init omap3_evm_init_irq(void)
{
omap_board_config = omap3_evm_config;
omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
omap2_init_common_infrastructure();
if (cpu_is_omap3630())
omap2_init_common_devices(h8kds0un0mer4em_sdrc_params, NULL);
else
omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
omap_init_irq();
gpmc_init();
}
void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1)
{
omap2_mux_init();
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
pwrdm_init(powerdomains_omap);
clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
omap2_clk_init();
omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
_omap2_init_reprogram_sdrc();
#endif
gpmc_init();
}
int board_init(void)
{
/* GPMC init */
gpmc_init();
/* MACH number */
gd->bd->bi_arch_number = 3000;
/* ATAGs location */
gd->bd->bi_boot_params = OMAP34XX_SDRC_CS0 + 0x100;
return 0;
}
/*
* Routine: board_init
* Description: Early hardware init.
*/
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* CS1 is Ethernet LAN9211 */
enable_gpmc_cs_config(gpmc_lab_enet, &gpmc_cfg->cs[1],
DEBUG_BASE, GPMC_SIZE_16M);
/* board id for Linux */
gd->bd->bi_arch_number = MACH_TYPE_OMAP_LDP;
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
return 0;
}
static void __init omap3_beagle_init_irq(void)
{
omap2_init_common_infrastructure();
omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
omap_init_irq();
gpmc_init();
#ifdef CONFIG_OMAP_32K_TIMER
if (omap3_beagle_version == OMAP3BEAGLE_BOARD_AXBX)
omap2_gp_clockevent_set_gptimer(12);
else
omap2_gp_clockevent_set_gptimer(1);
#endif
}
/*
* Routine: board_init
* Description: Early hardware init.
*/
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* board id for Linux */
gd->bd->bi_arch_number = MACH_TYPE_OMAP3_BEAGLE;
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
status_led_set (STATUS_LED_BOOT, STATUS_LED_ON);
#endif
return 0;
}
void spl_board_init(void)
{
#ifdef CONFIG_SPL_NAND_SUPPORT
gpmc_init();
#endif
#if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT)
arch_misc_init();
#endif
#if defined(CONFIG_HW_WATCHDOG)
hw_watchdog_init();
#endif
#ifdef CONFIG_AM33XX
am33xx_spl_board_init();
#endif
}
void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1)
{
omap_serial_early_init();
omap_hwmod_late_init();
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
_omap2_init_reprogram_sdrc();
}
gpmc_init();
omap_irq_base_init();
}
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
#endif
cm_t3517_musb_init();
return 0;
}
int board_init(void)
{
configure_evm_pin_mux(board_id, profile, daughter_board_connected);
#ifdef CONFIG_AM335X_MIN_CONFIG
board_min_init();
#else
board_evm_init();
#endif
gpmc_init();
return 0;
}
int board_init(void)
{
struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
modena_init0_bw_integer, modena_init0_watermark_0;
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gpmc_init();
/*
* Call this to initialize *ctrl again
*/
hw_data_init();
/* Clear all important bits for DSS errata that may need to be tweaked*/
mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
MREQPRIO_0_SAB_INIT0_MASK;
mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
BW_LIMITER_BW_FRAC_MASK;
modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
BW_LIMITER_BW_INT_MASK;
modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
BW_LIMITER_BW_WATERMARK_MASK;
/* Setting MReq Priority of the DSS*/
mreqprio_0 |= 0x77;
/*
* Set L3 Fast Configuration Register
* Limiting bandwith for ARM core to 700 MBPS
*/
modena_init0_bw_fractional |= 0x10;
modena_init0_bw_integer |= 0x3;
writel(mreqprio_0, &cdev->mreqprio_0);
writel(mreqprio_1, &cdev->mreqprio_1);
writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
return 0;
}
/*****************************************
* Routine: board_init
* Description: Early hardware init.
*****************************************/
int board_init(void)
{
u32 rev ;
DECLARE_GLOBAL_DATA_PTR;
gpmc_init(); /* in SRAM or SDRM, finish GPMC */
rev = get_board_type();
if ((rev == BOARD_H4_SDP)) {
gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4; /* board id for linux */
} else {
gd->bd->bi_arch_number = MACH_TYPE_OMAP_2430SDP; /* board id for linux */
}
gd->bd->bi_boot_params = (OMAP24XX_SDRC_CS0 + 0x100); /* adress of boot parameters */
return 0;
}
void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1)
{
u8 skip_setup_idle = 0;
if (cpu_is_omap24xx() || cpu_is_omap34xx())
pwrdm_init(powerdomains_omap, &omap2_pwrdm_functions);
else if (cpu_is_omap44xx())
pwrdm_init(powerdomains_omap, &omap4_pwrdm_functions);
clkdm_init(clockdomains_omap, clkdm_autodeps);
if (cpu_is_omap242x())
omap2420_hwmod_init();
else if (cpu_is_omap243x())
omap2430_hwmod_init();
else if (cpu_is_omap34xx())
omap3xxx_hwmod_init();
else if (cpu_is_omap44xx())
omap44xx_hwmod_init();
omap_pm_if_early_init();
if (cpu_is_omap2420())
omap2420_clk_init();
else if (cpu_is_omap2430())
omap2430_clk_init();
else if (cpu_is_omap34xx())
omap3xxx_clk_init();
else if (cpu_is_omap44xx())
omap4xxx_clk_init();
else
pr_err("Could not init clock framework - unknown CPU\n");
omap_serial_early_init();
#ifndef CONFIG_PM_RUNTIME
skip_setup_idle = 1;
#endif
omap_hwmod_late_init(skip_setup_idle);
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
#ifndef CONFIG_FB_OMAP_BOOTLOADER_INIT
_omap2_init_reprogram_sdrc();
#endif
}
gpmc_init();
omap2_dm_timer_early_init();
}
void aboot(unsigned *info)
{
unsigned bootdevice, n, len;
board_mux_init();
sdelay(100);
scale_vcores();
prcm_init();
board_ddr_init();
gpmc_init();
board_late_init();
serial_init();
serial_puts("\n[ aboot second-stage loader ]\n\n");
if (info) {
bootdevice = info[2] & 0xFF;
} else {
bootdevice = 0x45;
}
switch (bootdevice) {
case 0x45: /* USB */
serial_puts("boot device: USB\n\n");
n = load_from_usb(&len);
break;
case 0x05:
case 0x06:
serial_puts("boot device: MMC\n\n");
n = load_from_mmc(bootdevice, &len);
break;
default:
serial_puts("boot device: unknown\n");
for (;;) ;
}
if (n) {
serial_puts("io error\n");
} else {
boot_image(cfg_machine_type, CONFIG_ADDR_DOWNLOAD, len);
serial_puts("invalid image\n");
}
}
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
/* Chip select 1 and 3 are used for XR16L2751 UART controller */
enable_gpmc_cs_config(gpmc_XR16L2751, &gpmc_cfg->cs[1],
XR16L2751_UART1_BASE, GPMC_SIZE_16M);
enable_gpmc_cs_config(gpmc_XR16L2751, &gpmc_cfg->cs[3],
XR16L2751_UART2_BASE, GPMC_SIZE_16M);
gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB_PHY1_RESET");
gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, 1);
return 0;
}
/*
* Routine: board_init
* Description: hardware init.
*/
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* board id for Linux */
if (get_cpu_family() == CPU_OMAP34XX)
gd->bd->bi_arch_number = MACH_TYPE_CM_T35;
else
gd->bd->bi_arch_number = MACH_TYPE_CM_T3730;
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
#endif
return 0;
}
/**
* @brief board_init - gpmc and basic setup as phase1 of boot sequence
*
* @return 0
*/
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* TODO: Dynamically pop out CS mapping and program accordingly */
/* Configure devices for default ON ON ON settings */
enable_gpmc_cs_config(gpmc_sdp_nor, &gpmc_cfg->cs[0],
CONFIG_SYS_FLASH_BASE, GPMC_SIZE_128M);
enable_gpmc_cs_config(gpmc_sdp_nand, &gpmc_cfg->cs[1], 0x28000000,
GPMC_SIZE_16M);
enable_gpmc_cs_config(gpmc_sdp_onenand, &gpmc_cfg->cs[2], 0x20000000,
GPMC_SIZE_16M);
enable_gpmc_cs_config(gpmc_sdp_debug, &gpmc_cfg->cs[3], DEBUG_BASE,
GPMC_SIZE_16M);
/* board id for Linux */
gd->bd->bi_arch_number = MACH_TYPE_OMAP_3430SDP;
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
return 0;
}
void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1)
{
u8 skip_setup_idle = 0;
pwrdm_init(powerdomains_omap);
clkdm_init(clockdomains_omap, clkdm_autodeps);
if (cpu_is_omap242x())
omap2420_hwmod_init();
else if (cpu_is_omap243x())
omap2430_hwmod_init();
else if (cpu_is_omap34xx())
omap3xxx_hwmod_init();
/* The OPP tables have to be registered before a clk init */
omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
if (cpu_is_omap2420())
omap2420_clk_init();
else if (cpu_is_omap2430())
omap2430_clk_init();
else if (cpu_is_omap34xx())
omap3xxx_clk_init();
else if (cpu_is_omap44xx())
omap4xxx_clk_init();
else
pr_err("Could not init clock framework - unknown CPU\n");
omap_serial_early_init();
#ifndef CONFIG_PM_RUNTIME
skip_setup_idle = 1;
#endif
if (cpu_is_omap24xx() || cpu_is_omap34xx()) /* FIXME: OMAP4 */
omap_hwmod_late_init(skip_setup_idle);
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
_omap2_init_reprogram_sdrc();
}
gpmc_init();
}
/*
* Routine: board_init
* Description: Early hardware init.
*/
int board_init (void)
{
u32 *gpmc_config;
gpmc_init (); /* in SRAM or SDRAM, finish GPMC */
/* Configure console support on zoom2 */
gpmc_config = gpmc_serial_TL16CP754C;
enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[3],
SERIAL_TL16CP754C_BASE, GPMC_SIZE_16M);
/* board id for Linux */
gd->bd->bi_arch_number = MACH_TYPE_OMAP_ZOOM2;
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
status_led_set (STATUS_LED_BOOT, STATUS_LED_ON);
#endif
return 0;
}
void spl_nand_load_image(void)
{
struct image_header *header;
switch (omap_boot_mode()) {
case NAND_MODE_HW_ECC:
debug("spl: nand - using hw ecc\n");
gpmc_init();
nand_init();
break;
default:
puts("spl: ERROR: This bootmode is not implemented - hanging");
hang();
}
/*use CONFIG_SYS_TEXT_BASE as temporary storage area */
header = (struct image_header *)(CONFIG_SYS_TEXT_BASE);
#ifdef CONFIG_NAND_ENV_DST
nand_spl_load_image(CONFIG_ENV_OFFSET,
CONFIG_SYS_NAND_PAGE_SIZE, (void *)header);
spl_parse_image_header(header);
nand_spl_load_image(CONFIG_ENV_OFFSET, spl_image.size,
(void *)image_load_addr);
#ifdef CONFIG_ENV_OFFSET_REDUND
nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND,
CONFIG_SYS_NAND_PAGE_SIZE, (void *)header);
spl_parse_image_header(header);
nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, spl_image.size,
(void *)image_load_addr);
#endif
#endif
/* Load u-boot */
nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
CONFIG_SYS_NAND_PAGE_SIZE, (void *)header);
spl_parse_image_header(header);
nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
spl_image.size, (void *)spl_image.load_addr);
nand_deselect();
}
/*
* Routine: board_init
* Description: hardware init.
*/
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0],
CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M);
/* board id for Linux */
if (get_cpu_family() == CPU_OMAP34XX)
gd->bd->bi_arch_number = MACH_TYPE_CM_T35;
else
gd->bd->bi_arch_number = MACH_TYPE_CM_T3730;
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
#endif
return 0;
}
/*****************************************
* Routine: board_init
* Description: Early hardware init.
*****************************************/
int board_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
gpmc_init();
#if 0 /* No eMMC env partition for now */
/* Intializing env functional pointers with eMMC */
boot_env_get_char_spec = mmc_env_get_char_spec;
boot_env_init = mmc_env_init;
boot_saveenv = mmc_saveenv;
boot_env_relocate_spec = mmc_env_relocate_spec;
env_ptr = (env_t *) (CFG_FLASH_BASE + CFG_ENV_OFFSET);
env_name_spec = mmc_env_name_spec;
#endif
/* board id for Linux */
gd->bd->bi_arch_number = MACH_TYPE_OMAP4_OVATION;
gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
gd->bd->bi_board_revision = identify_board_revision();
return 0;
}
/*
* Basic board specific setup. Pinmux has been handled already.
*/
int board_init(void)
{
#if defined(CONFIG_HW_WATCHDOG)
hw_watchdog_init();
#endif /* defined(CONFIG_HW_WATCHDOG) */
i2c_set_bus_num(0);
if (read_eeprom() < 0)
puts("Could not get board ID.\n");
gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_FACTORYSET
factoryset_read_eeprom(CONFIG_SYS_I2C_EEPROM_ADDR);
#endif
gpmc_init();
#ifdef CONFIG_VIDEO
board_video_init();
#endif
return 0;
}
void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1,
struct omap_opp *mpu_opps,
struct omap_opp *dsp_opps,
struct omap_opp *l3_opps)
{
struct omap_hwmod **hwmods = NULL;
if (cpu_is_omap2420())
hwmods = omap2420_hwmods;
else if (cpu_is_omap2430())
hwmods = omap2430_hwmods;
else if (cpu_is_omap34xx())
hwmods = omap34xx_hwmods;
else if (cpu_is_omap44xx())
hwmods = omap44xx_hwmods;
pwrdm_init(powerdomains_omap);
clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
omap_hwmod_init(hwmods);
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
/* The OPP tables have to be registered before a clk init */
omap2_mux_init();
omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
#endif
omap2_clk_init();
omap_serial_early_init();
omap_hwmod_late_init();
#ifndef CONFIG_ARCH_OMAP4
omap_pm_if_init();
omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
_omap2_init_reprogram_sdrc();
#endif
gpmc_init();
omap_gpio_early_init();
omap2_dm_timer_early_init();
}
/*****************************************
* Routine: board_init
* Description: Early hardware init.
*****************************************/
int board_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
enum hw_board_id bid;
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
#if defined(CONFIG_3621EVT1A)
gd->bd->bi_arch_number = MACH_TYPE_OMAP3621_EVT1A; /* Linux mach id */
bid = read_board_id();
switch(bid) {
case NONE:
gd->bd->bi_board_revision = BOARD_ENCORE_REV_EVT1A;
break;
case EVT1B:
gd->bd->bi_board_revision = BOARD_ENCORE_REV_EVT1B;
break;
case EVT2:
gd->bd->bi_board_revision = BOARD_ENCORE_REV_EVT2;
break;
case DVT:
gd->bd->bi_board_revision = BOARD_ENCORE_REV_DVT;
break;
case PVT:
gd->bd->bi_board_revision = BOARD_ENCORE_REV_PVT;
break;
default:
gd->bd->bi_arch_number = BOARD_ENCORE_REV_UNKNOWN;
}
#else
gd->bd->bi_arch_number = MACH_TYPE_OMAP3621_BOXER; /* Linux mach id*/
#endif
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); /* boot param addr */
return 0;
}
void __init omap2_init_common_hw(void)
{
omap2_mux_init();
omap2_clk_init();
gpmc_init();
}