int owl_gpu_fun_active(enum gpu_clk_mode mode)
{
int ret = 0;
#ifdef ENABLE_COOLING
if(owl_gpu.is_cooling)
{
owl_gpu.reset_policy = mode;
return ret;
}
#endif
#if SUPPORT_GPU_DVFS
if(mode !=owl_gpu.normal_policy)
{
gpu_dvfs_deinit(&(g_gpu_dvfs_data));
}
#endif
ret = pvr_set_policy(mode);
#if SUPPORT_GPU_DVFS
if(mode ==owl_gpu.normal_policy)
{
gpu_dvfs_init(&(g_gpu_dvfs_data));
}
#endif
return ret;
}
int gpu_clock_init(struct device *dev)
{
int ret=0;
struct device_node *dn;
u32 normal_value;
int iclevel = 0; /* need to get from system, default value: IC_7059_0_0 */
owl_gpu.current_gpu_config = &gpu_policy_list_configs[iclevel]; /* set current gpu config*/
owl_gpu_fun_add_attr(&dev->kobj); /* add clock attribute configured by user,such as policy*/
owl_gpu_regulator_init(dev); /* get gpu regulator */
owl_gpu.normal_policy = GPU_NORMAL; /* config normal_policy by dts */
dn = dev->of_node;
ret = of_property_read_u32(dn,"normal_value",&normal_value); /* tmp do it */
if((ret == 0) && (normal_value == 2))
owl_gpu.normal_policy = GPU_PERFORMANCE_L1;
owl_gpu.clk_mode = GPU_POWERSAVE;
owl_gpu.current_coreclk = owl_gpu.current_gpu_config->gpu_policy[GPU_POWERSAVE].freq;
owl_gpu.bactive_clk = 0;
owl_gpu.ClockChangeCounter = 0;
owl_gpu.bSysInited = 0;
pvr_set_policy(owl_gpu.normal_policy); /* force set gpu clk rate one time at gpu initial time */
/* open to let other module change pll */
owl_pllsub_set_putaway(CLOCK__GPU3D_CORECLK, CLOCK__DEV_CLK);
owl_pllsub_set_putaway(CLOCK__GPU3D_NIC_MEMCLK, CLOCK__DEV_CLK);
owl_pllsub_set_putaway(CLOCK__GPU3D_SYSCLK, CLOCK__DEV_CLK);
owl_pllsub_set_putaway(CLOCK__GPU3D_HYDCLK, CLOCK__DEV_CLK);
owl_gpu_clk_notifier_register(&owl_gpu_clk_notifier);
#if SUPPORT_GPU_DVFS
gpu_dvfs_init(&(g_gpu_dvfs_data));
#endif
#ifdef ENABLE_COOLING
cputherm_register_notifier(&thermal_notifier_block, CPUFREQ_COOLING_START);
owl_gpu.is_cooling = 0;
owl_gpu.reset_policy = owl_gpu.normal_policy;
#endif
DEBUG_PRINTK("GPU Init success!\n");
DEBUG_PRINTK("In normal mode %d\n",owl_gpu.normal_policy);
return 0;
}
int k3v2_dcdc_gpu_probe(struct platform_device *pdev)
{
int err = 0;
struct plat_data *ipps_init_data = NULL;
struct resource *pmctrl_res = NULL;
struct device *dev = NULL;
struct ipps_gpu *ipps_gpu = NULL;
#ifdef CONFIG_EXTRAL_DYNAMIC_DCDC
if(!get_product_feature(PROD_FEATURE_GPU_DCDC_SUPPLY)) {
dev_err(&pdev->dev, "hardware version is invalid.\n");
return -EINVAL;
}
#endif
dev = &pdev->dev;
ipps_init_data = pdev->dev.platform_data;
if (!ipps_init_data) {
dev_err(&pdev->dev, "failed to get driver data.\n");
return -EINVAL;
}
pmctrl_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!pmctrl_res) {
dev_err(&pdev->dev, "failed to get pm I/O memory.\n");
return -ENXIO;
}
ipps_gpu = kzalloc(sizeof(struct ipps_gpu), GFP_KERNEL);
if (!ipps_gpu) {
dev_err(&pdev->dev, "failed to kzalloc memory for dcdc gpu.\n");
return -ENOMEM;
}
ipps_gpu->pmctrl_base = ioremap(pmctrl_res->start, resource_size(pmctrl_res));
if (!ipps_gpu->pmctrl_base) {
dev_err(&pdev->dev, "failed to remap pm_base I/O memory.\n");
err = -ENXIO;
goto err_free_mem;
}
ipps_gpu->regulator_dcdc = regulator_get(NULL, "gpu-vcc");
if (IS_ERR(ipps_gpu->regulator_dcdc)) {
dev_err(&pdev->dev, "regulator_get gpu dcdc failed.\n");
err = PTR_ERR(ipps_gpu->regulator_dcdc);
goto err_iounmap_pmsctrl_base;
}
/*get gpu dcdc*/
ipps_gpu->clk_hdmipll = clk_get(NULL, "clk_pll4");
if (IS_ERR(ipps_gpu->clk_hdmipll)) {
dev_err(&pdev->dev, "hdmipll clock get failed.\n");
err = PTR_ERR(ipps_gpu->clk_hdmipll);
goto err_regulator_put;
}
ipps_gpu->curr_profile = ipps_init_data->cur_profile;
ipps_gpu->curr_mode = ipps_init_data->mode;
ipps_gpu->curr_policy = ipps_init_data->policy;
ipps_gpu->gpu.freq.max = ipps_init_data->max;
ipps_gpu->gpu.freq.min = ipps_init_data->min;
ipps_gpu->gpu.freq.safe = ipps_init_data->safe;
ipps_gpu->temp_enable = TEMP_MON_DISABLE;
ipps_gpu->uptimes = 0;
ipps_gpu->downtimes = 0;
ipps_gpu->idev = ipps_alloc_device(sizeof(struct ipps_device));
if (NULL == ipps_gpu->idev) {
dev_err(&pdev->dev, "failed to alloc idev mem!\n");
err = PTR_ERR(ipps_gpu->idev);
goto err_regulator_put;
}
ipps_gpu->idev->command = k3v2_dcdc_gpu_cmd;
ipps_gpu->idev->object = ipps_init_data->obj;
ipps_gpu->idev->dev = dev;
g_ipps_gpu = ipps_gpu;
if (((POWERSAVE_POLICY <= ipps_gpu->curr_policy) && (ipps_gpu->curr_policy <=SPEC0B_POLICY)) ||
(ipps_gpu->curr_policy == NORMAL_POLICY) || (ipps_gpu->curr_policy == PERF_POLICY)) {
g_ipps_policy = policy_table[ipps_gpu->curr_policy];
} else {
err = -EINVAL;
WARN(1, "K3V2 DCDC GPU:policy is invalid.\n");
goto err_free_idev;
}
/*
*ipps_register_device() uses g_ipps_gpu pointer
*to excute client->add()
*/
err = ipps_register_device(ipps_gpu->idev);
if (err) {
dev_err(&pdev->dev, "ipps device register failed!\n");
goto err_free_idev;
}
err = sysfs_create_group(&dev->kobj, &k3_dcdc_gpu_attr_group);
if (err) {
dev_err(dev, "failed to creat sysfs file\n");
goto err_idev_unregister;
}
#if 1
ipps_gpu->gpu_dvfs_wq = create_singlethread_workqueue("gpudvfs");
if (ipps_gpu->gpu_dvfs_wq == NULL) {
dev_err(&pdev->dev, "create_workqueue failed for gpu dcdc\n");
err = PTR_ERR(ipps_gpu->gpu_dvfs_wq);
goto err_remove_sysfs_group;
}
#endif
mutex_init(®_lock_mutex);
gpu_dvfs_init();
return 0;
err_remove_sysfs_group:
sysfs_remove_group(&pdev->dev.kobj, &k3_dcdc_gpu_attr_group);
err_idev_unregister:
ipps_unregister_device(ipps_gpu->idev);
err_free_idev:
ipps_dealloc_device(ipps_gpu->idev);
err_regulator_put:
regulator_put(ipps_gpu->regulator_dcdc);
err_iounmap_pmsctrl_base:
iounmap(ipps_gpu->pmctrl_base);
err_free_mem:
kfree(ipps_gpu);
return err;
}