void CPU::hdma_update(unsigned i) { add_clocks(4); regs.mdr = dma_read((channel[i].source_bank << 16) | channel[i].hdma_addr); add_clocks(4); if((channel[i].line_counter & 0x7f) == 0) { channel[i].line_counter = regs.mdr; channel[i].hdma_addr++; channel[i].hdma_completed = (channel[i].line_counter == 0); channel[i].hdma_do_transfer = !channel[i].hdma_completed; if(channel[i].indirect) { add_clocks(4); regs.mdr = dma_read(hdma_addr(i)); add_clocks(4); channel[i].indirect_addr = regs.mdr << 8; if(!channel[i].hdma_completed || hdma_active_after(i)) { add_clocks(4); regs.mdr = dma_read(hdma_addr(i)); add_clocks(4); channel[i].indirect_addr >>= 8; channel[i].indirect_addr |= regs.mdr << 8; }
void sCPU::hdma_update(uint8 i) { channel[i].hdma_line_counter = dma_read(hdma_addr(i)); dma_add_clocks(8); channel[i].hdma_completed = (channel[i].hdma_line_counter == 0); channel[i].hdma_do_transfer = !channel[i].hdma_completed; if(channel[i].hdma_indirect) { channel[i].hdma_iaddr = dma_read(hdma_addr(i)) << 8; dma_add_clocks(8); if(!channel[i].hdma_completed || hdma_active_after(i)) { channel[i].hdma_iaddr >>= 8; channel[i].hdma_iaddr |= dma_read(hdma_addr(i)) << 8; dma_add_clocks(8); }