int hdmi_pll_enable(void)
{
u32 status;
u32 max_reads, timeout_us;
clk_enable(mdss_dsi_ahb_clk);
/* Global Enable */
REG_W(0x81, hdmi_phy_base + HDMI_PHY_GLB_CFG);
/* Power up power gen */
REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
udelay(350);
/* PLL Power-Up */
REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(5);
/* Power up PLL LDO */
REG_W(0x03, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(350);
/* PLL Power-Up */
REG_W(0x0F, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
udelay(350);
/* poll for PLL ready status */
max_reads = 20;
timeout_us = 100;
if (readl_poll_timeout_noirq((hdmi_phy_pll_base + HDMI_UNI_PLL_STATUS),
status, ((status & BIT(0)) == 1), max_reads, timeout_us)) {
pr_err("%s: hdmi phy pll status=%x failed to Lock\n",
__func__, status);
hdmi_pll_disable();
clk_disable(mdss_dsi_ahb_clk);
return -EINVAL;
}
pr_debug("%s: hdmi phy pll is locked\n", __func__);
udelay(350);
/* poll for PHY ready status */
max_reads = 20;
timeout_us = 100;
if (readl_poll_timeout_noirq((hdmi_phy_base + HDMI_PHY_STATUS),
status, ((status & BIT(0)) == 1), max_reads, timeout_us)) {
pr_err("%s: hdmi phy status=%x failed to Lock\n",
__func__, status);
hdmi_pll_disable();
clk_disable(mdss_dsi_ahb_clk);
return -EINVAL;
}
pr_debug("%s: hdmi phy is locked\n", __func__);
clk_disable(mdss_dsi_ahb_clk);
hdmi_pll_on = 1;
return 0;
} /* hdmi_pll_enable */
int hdmi_pll_set_rate(unsigned long rate)
{
unsigned int set_power_dwn = 0;
if (hdmi_pll_on) {
hdmi_pll_disable();
set_power_dwn = 1;
}
clk_enable(mdss_dsi_ahb_clk);
pr_debug("%s: rate=%ld\n", __func__, rate);
switch (rate) {
case 0:
/* This case is needed for suspend/resume. */
break;
case 25200000:
/* 640x480p60 */
REG_W(0x81, hdmi_phy_base + HDMI_PHY_GLB_CFG);
REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_REFCLK_CFG);
REG_W(0x19, hdmi_phy_pll_base + HDMI_UNI_PLL_VCOLPF_CFG);
REG_W(0x0E, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFR_CFG);
REG_W(0x20, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFC1_CFG);
REG_W(0x0D, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFC2_CFG);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG0);
REG_W(0x52, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG1);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG2);
REG_W(0xB0, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG3);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG4);
REG_W(0x10, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG0);
REG_W(0x1A, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG1);
REG_W(0x05, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG2);
REG_W(0x03, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV1_CFG);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV2_CFG);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV3_CFG);
REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG2);
REG_W(0x60, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG8);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG9);
REG_W(0xF4, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG10);
REG_W(0x02, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG11);
REG_W(0x1F, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
udelay(50);
REG_W(0x0F, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL1);
REG_W(0x10, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
REG_W(0xDB, hdmi_phy_base + HDMI_PHY_ANA_CFG0);
REG_W(0x43, hdmi_phy_base + HDMI_PHY_ANA_CFG1);
REG_W(0x02, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_ANA_CFG3);
REG_W(0x04, hdmi_phy_pll_base + HDMI_UNI_PLL_VREG_CFG);
REG_W(0xD0, hdmi_phy_base + HDMI_PHY_DCC_CFG0);
REG_W(0x1A, hdmi_phy_base + HDMI_PHY_DCC_CFG1);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG0);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG1);
REG_W(0x02, hdmi_phy_base + HDMI_PHY_TXCAL_CFG2);
REG_W(0x05, hdmi_phy_base + HDMI_PHY_TXCAL_CFG3);
udelay(200);
break;
case 27000000:
/* 576p50/576i50 case */
REG_W(0x81, hdmi_phy_base + HDMI_PHY_GLB_CFG);
REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_REFCLK_CFG);
REG_W(0x19, hdmi_phy_pll_base + HDMI_UNI_PLL_VCOLPF_CFG);
REG_W(0X0E, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFR_CFG);
REG_W(0x20, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFC1_CFG);
REG_W(0X0D, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFC2_CFG);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG0);
REG_W(0x54, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG1);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG2);
REG_W(0x18, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG3);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG4);
REG_W(0x10, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG0);
REG_W(0X1A, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG1);
REG_W(0x05, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG2);
REG_W(0x03, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV1_CFG);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV2_CFG);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV3_CFG);
REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG2);
REG_W(0x60, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG8);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG9);
REG_W(0x2a, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG10);
REG_W(0x03, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG11);
REG_W(0X1F, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
udelay(50);
REG_W(0X0F, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL1);
REG_W(0x10, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
REG_W(0XDB, hdmi_phy_base + HDMI_PHY_ANA_CFG0);
REG_W(0x43, hdmi_phy_base + HDMI_PHY_ANA_CFG1);
REG_W(0x02, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_ANA_CFG3);
REG_W(0x04, hdmi_phy_pll_base + HDMI_UNI_PLL_VREG_CFG);
REG_W(0XD0, hdmi_phy_base + HDMI_PHY_DCC_CFG0);
REG_W(0X1A, hdmi_phy_base + HDMI_PHY_DCC_CFG1);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG0);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG1);
REG_W(0x02, hdmi_phy_base + HDMI_PHY_TXCAL_CFG2);
REG_W(0x05, hdmi_phy_base + HDMI_PHY_TXCAL_CFG3);
udelay(200);
break;
case 27030000:
/* 480p60/480i60 case */
REG_W(0x81, hdmi_phy_base + HDMI_PHY_GLB_CFG);
REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_REFCLK_CFG);
REG_W(0x19, hdmi_phy_pll_base + HDMI_UNI_PLL_VCOLPF_CFG);
REG_W(0x0E, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFR_CFG);
REG_W(0x20, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFC1_CFG);
REG_W(0x0D, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFC2_CFG);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG0);
REG_W(0x54, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG1);
REG_W(0x66, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG2);
REG_W(0x1D, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG3);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG4);
REG_W(0x10, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG0);
REG_W(0x1A, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG1);
REG_W(0x05, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG2);
REG_W(0x03, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV1_CFG);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV2_CFG);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV3_CFG);
REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG2);
REG_W(0x60, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG8);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG9);
REG_W(0x2A, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG10);
REG_W(0x03, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG11);
REG_W(0x1F, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
udelay(50);
REG_W(0x0F, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL1);
REG_W(0x10, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
REG_W(0xDB, hdmi_phy_base + HDMI_PHY_ANA_CFG0);
REG_W(0x43, hdmi_phy_base + HDMI_PHY_ANA_CFG1);
REG_W(0x02, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_ANA_CFG3);
REG_W(0x04, hdmi_phy_pll_base + HDMI_UNI_PLL_VREG_CFG);
REG_W(0xD0, hdmi_phy_base + HDMI_PHY_DCC_CFG0);
REG_W(0x1A, hdmi_phy_base + HDMI_PHY_DCC_CFG1);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG0);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG1);
REG_W(0x02, hdmi_phy_base + HDMI_PHY_TXCAL_CFG2);
REG_W(0x05, hdmi_phy_base + HDMI_PHY_TXCAL_CFG3);
udelay(200);
break;
case 74250000:
/*
* 720p60/720p50/1080i60/1080i50
* 1080p24/1080p30/1080p25 case
*/
REG_W(0x81, hdmi_phy_base + HDMI_PHY_GLB_CFG);
REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_REFCLK_CFG);
REG_W(0x19, hdmi_phy_pll_base + HDMI_UNI_PLL_VCOLPF_CFG);
REG_W(0x0E, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFR_CFG);
REG_W(0x20, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFC1_CFG);
REG_W(0x0D, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFC2_CFG);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG0);
REG_W(0x52, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG1);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG2);
REG_W(0x56, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG3);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG4);
REG_W(0x10, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG0);
REG_W(0x1A, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG1);
REG_W(0x05, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG2);
REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV1_CFG);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV2_CFG);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV3_CFG);
REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG2);
REG_W(0x60, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG8);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG9);
REG_W(0xE6, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG10);
REG_W(0x02, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG11);
REG_W(0x1F, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
udelay(50);
REG_W(0x0F, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL1);
REG_W(0x10, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
REG_W(0xDB, hdmi_phy_base + HDMI_PHY_ANA_CFG0);
REG_W(0x43, hdmi_phy_base + HDMI_PHY_ANA_CFG1);
REG_W(0x02, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_ANA_CFG3);
REG_W(0x04, hdmi_phy_pll_base + HDMI_UNI_PLL_VREG_CFG);
REG_W(0xD0, hdmi_phy_base + HDMI_PHY_DCC_CFG0);
REG_W(0x1A, hdmi_phy_base + HDMI_PHY_DCC_CFG1);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG0);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG1);
REG_W(0x02, hdmi_phy_base + HDMI_PHY_TXCAL_CFG2);
REG_W(0x05, hdmi_phy_base + HDMI_PHY_TXCAL_CFG3);
udelay(200);
break;
case 148500000:
REG_W(0x81, hdmi_phy_base + HDMI_PHY_GLB_CFG);
REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_REFCLK_CFG);
REG_W(0x19, hdmi_phy_pll_base + HDMI_UNI_PLL_VCOLPF_CFG);
REG_W(0x0E, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFR_CFG);
REG_W(0x20, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFC1_CFG);
REG_W(0x0D, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFC2_CFG);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG0);
REG_W(0x52, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG1);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG2);
REG_W(0x56, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG3);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG4);
REG_W(0x10, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG0);
REG_W(0x1A, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG1);
REG_W(0x05, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG2);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV1_CFG);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV2_CFG);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV3_CFG);
REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG2);
REG_W(0x60, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG8);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG9);
REG_W(0xE6, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG10);
REG_W(0x02, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG11);
REG_W(0x1F, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
udelay(50);
REG_W(0x0F, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL1);
REG_W(0x10, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
REG_W(0xDB, hdmi_phy_base + HDMI_PHY_ANA_CFG0);
REG_W(0x43, hdmi_phy_base + HDMI_PHY_ANA_CFG1);
REG_W(0x02, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_ANA_CFG3);
REG_W(0x04, hdmi_phy_pll_base + HDMI_UNI_PLL_VREG_CFG);
REG_W(0xD0, hdmi_phy_base + HDMI_PHY_DCC_CFG0);
REG_W(0x1A, hdmi_phy_base + HDMI_PHY_DCC_CFG1);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG0);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG1);
REG_W(0x02, hdmi_phy_base + HDMI_PHY_TXCAL_CFG2);
REG_W(0x05, hdmi_phy_base + HDMI_PHY_TXCAL_CFG3);
udelay(200);
break;
case 268500000:
REG_W(0x81, hdmi_phy_base + HDMI_PHY_GLB_CFG);
REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_REFCLK_CFG);
REG_W(0x19, hdmi_phy_pll_base + HDMI_UNI_PLL_VCOLPF_CFG);
REG_W(0x0E, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFR_CFG);
REG_W(0x20, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFC1_CFG);
REG_W(0x0D, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFC2_CFG);
REG_W(0x36, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG0);
REG_W(0x61, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG1);
REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG2);
REG_W(0xF6, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG3);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG4);
REG_W(0x10, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG0);
REG_W(0x1A, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG1);
REG_W(0x05, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG2);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV1_CFG);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV2_CFG);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV3_CFG);
REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG2);
REG_W(0x60, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG8);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG9);
REG_W(0x3E, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG10);
REG_W(0x05, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG11);
REG_W(0x1F, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
udelay(50);
REG_W(0x0F, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL1);
REG_W(0x10, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
REG_W(0xDB, hdmi_phy_base + HDMI_PHY_ANA_CFG0);
REG_W(0x43, hdmi_phy_base + HDMI_PHY_ANA_CFG1);
REG_W(0x05, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_ANA_CFG3);
REG_W(0x04, hdmi_phy_pll_base + HDMI_UNI_PLL_VREG_CFG);
REG_W(0xD0, hdmi_phy_base + HDMI_PHY_DCC_CFG0);
REG_W(0x1A, hdmi_phy_base + HDMI_PHY_DCC_CFG1);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG0);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG1);
REG_W(0x11, hdmi_phy_base + HDMI_PHY_TXCAL_CFG2);
REG_W(0x05, hdmi_phy_base + HDMI_PHY_TXCAL_CFG3);
udelay(200);
break;
case 297000000:
REG_W(0x81, hdmi_phy_base + HDMI_PHY_GLB_CFG);
REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_REFCLK_CFG);
REG_W(0x19, hdmi_phy_pll_base + HDMI_UNI_PLL_VCOLPF_CFG);
REG_W(0x0E, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFR_CFG);
REG_W(0x20, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFC1_CFG);
REG_W(0x0D, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFC2_CFG);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG0);
REG_W(0x65, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG1);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG2);
REG_W(0xAC, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG3);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG4);
REG_W(0x10, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG0);
REG_W(0x1A, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG1);
REG_W(0x05, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG2);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV1_CFG);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV2_CFG);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV3_CFG);
REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG2);
REG_W(0x60, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG8);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG9);
REG_W(0xCD, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG10);
REG_W(0x05, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG11);
REG_W(0x1F, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
udelay(50);
REG_W(0x0F, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL1);
REG_W(0x10, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
REG_W(0xDB, hdmi_phy_base + HDMI_PHY_ANA_CFG0);
REG_W(0x43, hdmi_phy_base + HDMI_PHY_ANA_CFG1);
REG_W(0x06, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
REG_W(0x03, hdmi_phy_base + HDMI_PHY_ANA_CFG3);
REG_W(0x04, hdmi_phy_pll_base + HDMI_UNI_PLL_VREG_CFG);
REG_W(0xD0, hdmi_phy_base + HDMI_PHY_DCC_CFG0);
REG_W(0x1A, hdmi_phy_base + HDMI_PHY_DCC_CFG1);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG0);
REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG1);
REG_W(0x02, hdmi_phy_base + HDMI_PHY_TXCAL_CFG2);
REG_W(0x05, hdmi_phy_base + HDMI_PHY_TXCAL_CFG3);
udelay(200);
break;
default:
pr_err("%s: not supported rate=%ld\n", __func__, rate);
}
/* Make sure writes complete before disabling iface clock */
mb();
clk_disable(mdss_dsi_ahb_clk);
if (set_power_dwn)
hdmi_pll_enable();
return 0;
} /* hdmi_pll_set_rate */
int hdmi_pll_set_rate(unsigned rate)
{
unsigned int set_power_dwn = 0;
u32 ahb_en_reg = readl_relaxed(AHB_EN_REG);
u32 ahb_enabled = ahb_en_reg & BIT(4);
if (!ahb_enabled) {
writel_relaxed(ahb_en_reg | BIT(4), AHB_EN_REG);
/* Make sure iface clock is enabled before register access */
mb();
}
if (hdmi_pll_on) {
hdmi_pll_disable();
set_power_dwn = 1;
}
switch (rate) {
case 27030000:
/* 480p60/480i60 case */
writel_relaxed(0xA, HDMI_PHY_PLL_PWRDN_B);
writel_relaxed(0x38, HDMI_PHY_PLL_REFCLK_CFG);
writel_relaxed(0x2, HDMI_PHY_PLL_CHRG_PUMP_CFG);
writel_relaxed(0x20, HDMI_PHY_PLL_LOOP_FLT_CFG0);
writel_relaxed(0xFF, HDMI_PHY_PLL_LOOP_FLT_CFG1);
writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG0);
writel_relaxed(0x4E, HDMI_PHY_PLL_SDM_CFG1);
writel_relaxed(0xD7, HDMI_PHY_PLL_SDM_CFG2);
writel_relaxed(0x03, HDMI_PHY_PLL_SDM_CFG3);
writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG4);
writel_relaxed(0x2A, HDMI_PHY_PLL_VCOCAL_CFG0);
writel_relaxed(0x03, HDMI_PHY_PLL_VCOCAL_CFG1);
writel_relaxed(0x3B, HDMI_PHY_PLL_VCOCAL_CFG2);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG3);
writel_relaxed(0x86, HDMI_PHY_PLL_VCOCAL_CFG4);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG5);
writel_relaxed(0x33, HDMI_PHY_PLL_VCOCAL_CFG6);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG7);
break;
case 25200000:
/* 640x480p60 */
writel_relaxed(0x32, HDMI_PHY_PLL_REFCLK_CFG);
writel_relaxed(0x2, HDMI_PHY_PLL_CHRG_PUMP_CFG);
writel_relaxed(0x01, HDMI_PHY_PLL_LOOP_FLT_CFG0);
writel_relaxed(0x33, HDMI_PHY_PLL_LOOP_FLT_CFG1);
writel_relaxed(0x2C, HDMI_PHY_PLL_IDAC_ADJ_CFG);
writel_relaxed(0x6, HDMI_PHY_PLL_I_VI_KVCO_CFG);
writel_relaxed(0xA, HDMI_PHY_PLL_PWRDN_B);
writel_relaxed(0x77, HDMI_PHY_PLL_SDM_CFG0);
writel_relaxed(0x4C, HDMI_PHY_PLL_SDM_CFG1);
writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG2);
writel_relaxed(0xC0, HDMI_PHY_PLL_SDM_CFG3);
writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG4);
writel_relaxed(0x9A, HDMI_PHY_PLL_SSC_CFG0);
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG1);
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG2);
writel_relaxed(0x20, HDMI_PHY_PLL_SSC_CFG3);
writel_relaxed(0x10, HDMI_PHY_PLL_LOCKDET_CFG0);
writel_relaxed(0x1A, HDMI_PHY_PLL_LOCKDET_CFG1);
writel_relaxed(0x0D, HDMI_PHY_PLL_LOCKDET_CFG2);
writel_relaxed(0xF4, HDMI_PHY_PLL_VCOCAL_CFG0);
writel_relaxed(0x02, HDMI_PHY_PLL_VCOCAL_CFG1);
writel_relaxed(0x3B, HDMI_PHY_PLL_VCOCAL_CFG2);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG3);
writel_relaxed(0x86, HDMI_PHY_PLL_VCOCAL_CFG4);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG5);
writel_relaxed(0x33, HDMI_PHY_PLL_VCOCAL_CFG6);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG7);
break;
case 27000000:
/* 576p50/576i50 case */
writel_relaxed(0x32, HDMI_PHY_PLL_REFCLK_CFG);
writel_relaxed(0x2, HDMI_PHY_PLL_CHRG_PUMP_CFG);
writel_relaxed(0x01, HDMI_PHY_PLL_LOOP_FLT_CFG0);
writel_relaxed(0x33, HDMI_PHY_PLL_LOOP_FLT_CFG1);
writel_relaxed(0x2C, HDMI_PHY_PLL_IDAC_ADJ_CFG);
writel_relaxed(0x6, HDMI_PHY_PLL_I_VI_KVCO_CFG);
writel_relaxed(0xA, HDMI_PHY_PLL_PWRDN_B);
writel_relaxed(0x7B, HDMI_PHY_PLL_SDM_CFG0);
writel_relaxed(0x01, HDMI_PHY_PLL_SDM_CFG1);
writel_relaxed(0x4C, HDMI_PHY_PLL_SDM_CFG2);
writel_relaxed(0xC0, HDMI_PHY_PLL_SDM_CFG3);
writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG4);
writel_relaxed(0x9A, HDMI_PHY_PLL_SSC_CFG0);
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG1);
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG2);
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG3);
writel_relaxed(0x10, HDMI_PHY_PLL_LOCKDET_CFG0);
writel_relaxed(0x1A, HDMI_PHY_PLL_LOCKDET_CFG1);
writel_relaxed(0x0D, HDMI_PHY_PLL_LOCKDET_CFG2);
writel_relaxed(0x2a, HDMI_PHY_PLL_VCOCAL_CFG0);
writel_relaxed(0x03, HDMI_PHY_PLL_VCOCAL_CFG1);
writel_relaxed(0x3B, HDMI_PHY_PLL_VCOCAL_CFG2);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG3);
writel_relaxed(0x86, HDMI_PHY_PLL_VCOCAL_CFG4);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG5);
writel_relaxed(0x33, HDMI_PHY_PLL_VCOCAL_CFG6);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG7);
break;
case 74250000:
/* 720p60/720p50/1080i60/1080i50
* 1080p24/1080p30/1080p25 case
*/
writel_relaxed(0xA, HDMI_PHY_PLL_PWRDN_B);
writel_relaxed(0x12, HDMI_PHY_PLL_REFCLK_CFG);
writel_relaxed(0x01, HDMI_PHY_PLL_LOOP_FLT_CFG0);
writel_relaxed(0x33, HDMI_PHY_PLL_LOOP_FLT_CFG1);
writel_relaxed(0x76, HDMI_PHY_PLL_SDM_CFG0);
writel_relaxed(0xE6, HDMI_PHY_PLL_VCOCAL_CFG0);
writel_relaxed(0x02, HDMI_PHY_PLL_VCOCAL_CFG1);
writel_relaxed(0x3B, HDMI_PHY_PLL_VCOCAL_CFG2);
break;
case 148500000:
/* 1080p60/1080p50 case */
writel_relaxed(0x2, HDMI_PHY_PLL_REFCLK_CFG);
writel_relaxed(0x2, HDMI_PHY_PLL_CHRG_PUMP_CFG);
writel_relaxed(0x01, HDMI_PHY_PLL_LOOP_FLT_CFG0);
writel_relaxed(0x33, HDMI_PHY_PLL_LOOP_FLT_CFG1);
writel_relaxed(0x2C, HDMI_PHY_PLL_IDAC_ADJ_CFG);
writel_relaxed(0x6, HDMI_PHY_PLL_I_VI_KVCO_CFG);
writel_relaxed(0xA, HDMI_PHY_PLL_PWRDN_B);
writel_relaxed(0x76, HDMI_PHY_PLL_SDM_CFG0);
writel_relaxed(0x01, HDMI_PHY_PLL_SDM_CFG1);
writel_relaxed(0x4C, HDMI_PHY_PLL_SDM_CFG2);
writel_relaxed(0xC0, HDMI_PHY_PLL_SDM_CFG3);
writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG4);
writel_relaxed(0x9A, HDMI_PHY_PLL_SSC_CFG0);
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG1);
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG2);
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG3);
writel_relaxed(0x10, HDMI_PHY_PLL_LOCKDET_CFG0);
writel_relaxed(0x1A, HDMI_PHY_PLL_LOCKDET_CFG1);
writel_relaxed(0x0D, HDMI_PHY_PLL_LOCKDET_CFG2);
writel_relaxed(0xe6, HDMI_PHY_PLL_VCOCAL_CFG0);
writel_relaxed(0x02, HDMI_PHY_PLL_VCOCAL_CFG1);
writel_relaxed(0x3B, HDMI_PHY_PLL_VCOCAL_CFG2);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG3);
writel_relaxed(0x86, HDMI_PHY_PLL_VCOCAL_CFG4);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG5);
writel_relaxed(0x33, HDMI_PHY_PLL_VCOCAL_CFG6);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG7);
break;
}
/* Make sure writes complete before disabling iface clock */
mb();
if (set_power_dwn)
hdmi_pll_enable();
current_rate = rate;
if (!ahb_enabled)
writel_relaxed(ahb_en_reg & ~BIT(4), AHB_EN_REG);
return 0;
}
int hdmi_pll_enable(void)
{
unsigned int val;
u32 ahb_en_reg, ahb_enabled;
unsigned int timeout_count;
int pll_lock_retry = 10;
ahb_en_reg = readl_relaxed(AHB_EN_REG);
ahb_enabled = ahb_en_reg & BIT(4);
if (!ahb_enabled) {
writel_relaxed(ahb_en_reg | BIT(4), AHB_EN_REG);
/* Make sure iface clock is enabled before register access */
mb();
}
/* Assert PLL S/W reset */
writel_relaxed(0x8D, HDMI_PHY_PLL_LOCKDET_CFG2);
writel_relaxed(0x10, HDMI_PHY_PLL_LOCKDET_CFG0);
writel_relaxed(0x1A, HDMI_PHY_PLL_LOCKDET_CFG1);
/* Wait for a short time before de-asserting
* to allow the hardware to complete its job.
* This much of delay should be fine for hardware
* to assert and de-assert.
*/
udelay(10);
/* De-assert PLL S/W reset */
writel_relaxed(0x0D, HDMI_PHY_PLL_LOCKDET_CFG2);
val = readl_relaxed(HDMI_PHY_REG_12);
val |= BIT(5);
/* Assert PHY S/W reset */
writel_relaxed(val, HDMI_PHY_REG_12);
val &= ~BIT(5);
/* Wait for a short time before de-asserting
to allow the hardware to complete its job.
This much of delay should be fine for hardware
to assert and de-assert. */
udelay(10);
/* De-assert PHY S/W reset */
writel_relaxed(val, HDMI_PHY_REG_12);
writel_relaxed(0x3f, HDMI_PHY_REG_2);
val = readl_relaxed(HDMI_PHY_REG_12);
val |= PWRDN_B;
writel_relaxed(val, HDMI_PHY_REG_12);
/* Wait 10 us for enabling global power for PHY */
mb();
udelay(10);
val = readl_relaxed(HDMI_PHY_PLL_PWRDN_B);
val |= PLL_PWRDN_B;
val &= ~PD_PLL;
writel_relaxed(val, HDMI_PHY_PLL_PWRDN_B);
writel_relaxed(0x80, HDMI_PHY_REG_2);
timeout_count = 10000;
while (!(readl_relaxed(HDMI_PHY_PLL_STATUS0) & BIT(0)) &&
timeout_count && pll_lock_retry) {
if (--timeout_count == 0) {
/*
* PLL has still not locked.
* Do a software reset and try again
* Assert PLL S/W reset first
*/
writel_relaxed(0x8D, HDMI_PHY_PLL_LOCKDET_CFG2);
/* Wait for a short time before de-asserting
* to allow the hardware to complete its job.
* This much of delay should be fine for hardware
* to assert and de-assert.
*/
udelay(10);
writel_relaxed(0x0D, HDMI_PHY_PLL_LOCKDET_CFG2);
/*
* Wait for a short duration for the PLL calibration
* before checking if the PLL gets locked
*/
udelay(350);
timeout_count = 1000;
pll_lock_retry--;
}
}
if (!ahb_enabled)
writel_relaxed(ahb_en_reg & ~BIT(4), AHB_EN_REG);
if (!pll_lock_retry) {
pr_err("%s: HDMI PLL not locked\n", __func__);
hdmi_pll_disable();
return -EAGAIN;
}
hdmi_pll_on = 1;
return 0;
}
int hdmi_pll_enable(void)
{
unsigned int val;
u32 ahb_en_reg, ahb_enabled;
unsigned int timeout_count;
int pll_lock_retry = 10;
ahb_en_reg = readl_relaxed(AHB_EN_REG);
ahb_enabled = ahb_en_reg & BIT(4);
if (!ahb_enabled) {
writel_relaxed(ahb_en_reg | BIT(4), AHB_EN_REG);
/* */
mb();
}
/* */
writel_relaxed(0x8D, HDMI_PHY_PLL_LOCKDET_CFG2);
writel_relaxed(0x10, HDMI_PHY_PLL_LOCKDET_CFG0);
writel_relaxed(0x1A, HDMI_PHY_PLL_LOCKDET_CFG1);
/*
*/
udelay(10);
/* */
writel_relaxed(0x0D, HDMI_PHY_PLL_LOCKDET_CFG2);
val = readl_relaxed(HDMI_PHY_REG_12);
val |= BIT(5);
/* */
writel_relaxed(val, HDMI_PHY_REG_12);
val &= ~BIT(5);
/*
*/
udelay(10);
/* */
writel_relaxed(val, HDMI_PHY_REG_12);
writel_relaxed(0x3f, HDMI_PHY_REG_2);
val = readl_relaxed(HDMI_PHY_REG_12);
val |= PWRDN_B;
writel_relaxed(val, HDMI_PHY_REG_12);
/* */
mb();
udelay(10);
val = readl_relaxed(HDMI_PHY_PLL_PWRDN_B);
val |= PLL_PWRDN_B;
val &= ~PD_PLL;
writel_relaxed(val, HDMI_PHY_PLL_PWRDN_B);
writel_relaxed(0x80, HDMI_PHY_REG_2);
timeout_count = 1000;
while (!(readl_relaxed(HDMI_PHY_PLL_STATUS0) & BIT(0)) &&
timeout_count && pll_lock_retry) {
if (--timeout_count == 0) {
/*
*/
writel_relaxed(0x8D, HDMI_PHY_PLL_LOCKDET_CFG2);
/*
*/
udelay(10);
writel_relaxed(0x0D, HDMI_PHY_PLL_LOCKDET_CFG2);
/*
*/
udelay(350);
timeout_count = 1000;
pll_lock_retry--;
}
}
if (!ahb_enabled)
writel_relaxed(ahb_en_reg & ~BIT(4), AHB_EN_REG);
if (!pll_lock_retry) {
pr_err("%s: HDMI PLL not locked\n", __func__);
hdmi_pll_disable();
return -EAGAIN;
}
hdmi_pll_on = 1;
return 0;
}
int hdmi_pll_set_rate(unsigned rate)
{
unsigned int set_power_dwn = 0;
u32 ahb_en_reg = readl_relaxed(AHB_EN_REG);
u32 ahb_enabled = ahb_en_reg & BIT(4);
if (!ahb_enabled) {
writel_relaxed(ahb_en_reg | BIT(4), AHB_EN_REG);
/* */
mb();
}
if (hdmi_pll_on) {
hdmi_pll_disable();
set_power_dwn = 1;
}
switch (rate) {
case 27030000:
/* */
writel_relaxed(0xA, HDMI_PHY_PLL_PWRDN_B);
writel_relaxed(0x38, HDMI_PHY_PLL_REFCLK_CFG);
writel_relaxed(0x2, HDMI_PHY_PLL_CHRG_PUMP_CFG);
writel_relaxed(0x20, HDMI_PHY_PLL_LOOP_FLT_CFG0);
writel_relaxed(0xFF, HDMI_PHY_PLL_LOOP_FLT_CFG1);
writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG0);
writel_relaxed(0x4E, HDMI_PHY_PLL_SDM_CFG1);
writel_relaxed(0xD7, HDMI_PHY_PLL_SDM_CFG2);
writel_relaxed(0x03, HDMI_PHY_PLL_SDM_CFG3);
writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG4);
writel_relaxed(0x2A, HDMI_PHY_PLL_VCOCAL_CFG0);
writel_relaxed(0x03, HDMI_PHY_PLL_VCOCAL_CFG1);
writel_relaxed(0x3B, HDMI_PHY_PLL_VCOCAL_CFG2);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG3);
writel_relaxed(0x86, HDMI_PHY_PLL_VCOCAL_CFG4);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG5);
writel_relaxed(0x33, HDMI_PHY_PLL_VCOCAL_CFG6);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG7);
break;
case 25200000:
/* */
writel_relaxed(0x32, HDMI_PHY_PLL_REFCLK_CFG);
writel_relaxed(0x2, HDMI_PHY_PLL_CHRG_PUMP_CFG);
writel_relaxed(0x01, HDMI_PHY_PLL_LOOP_FLT_CFG0);
writel_relaxed(0x33, HDMI_PHY_PLL_LOOP_FLT_CFG1);
writel_relaxed(0x2C, HDMI_PHY_PLL_IDAC_ADJ_CFG);
writel_relaxed(0x6, HDMI_PHY_PLL_I_VI_KVCO_CFG);
writel_relaxed(0xA, HDMI_PHY_PLL_PWRDN_B);
writel_relaxed(0x77, HDMI_PHY_PLL_SDM_CFG0);
writel_relaxed(0x4C, HDMI_PHY_PLL_SDM_CFG1);
writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG2);
writel_relaxed(0xC0, HDMI_PHY_PLL_SDM_CFG3);
writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG4);
writel_relaxed(0x9A, HDMI_PHY_PLL_SSC_CFG0);
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG1);
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG2);
writel_relaxed(0x20, HDMI_PHY_PLL_SSC_CFG3);
writel_relaxed(0x10, HDMI_PHY_PLL_LOCKDET_CFG0);
writel_relaxed(0x1A, HDMI_PHY_PLL_LOCKDET_CFG1);
writel_relaxed(0x0D, HDMI_PHY_PLL_LOCKDET_CFG2);
writel_relaxed(0xF4, HDMI_PHY_PLL_VCOCAL_CFG0);
writel_relaxed(0x02, HDMI_PHY_PLL_VCOCAL_CFG1);
writel_relaxed(0x3B, HDMI_PHY_PLL_VCOCAL_CFG2);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG3);
writel_relaxed(0x86, HDMI_PHY_PLL_VCOCAL_CFG4);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG5);
writel_relaxed(0x33, HDMI_PHY_PLL_VCOCAL_CFG6);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG7);
break;
case 27000000:
/* */
writel_relaxed(0x32, HDMI_PHY_PLL_REFCLK_CFG);
writel_relaxed(0x2, HDMI_PHY_PLL_CHRG_PUMP_CFG);
writel_relaxed(0x01, HDMI_PHY_PLL_LOOP_FLT_CFG0);
writel_relaxed(0x33, HDMI_PHY_PLL_LOOP_FLT_CFG1);
writel_relaxed(0x2C, HDMI_PHY_PLL_IDAC_ADJ_CFG);
writel_relaxed(0x6, HDMI_PHY_PLL_I_VI_KVCO_CFG);
writel_relaxed(0xA, HDMI_PHY_PLL_PWRDN_B);
writel_relaxed(0x7B, HDMI_PHY_PLL_SDM_CFG0);
writel_relaxed(0x01, HDMI_PHY_PLL_SDM_CFG1);
writel_relaxed(0x4C, HDMI_PHY_PLL_SDM_CFG2);
writel_relaxed(0xC0, HDMI_PHY_PLL_SDM_CFG3);
writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG4);
writel_relaxed(0x9A, HDMI_PHY_PLL_SSC_CFG0);
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG1);
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG2);
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG3);
writel_relaxed(0x10, HDMI_PHY_PLL_LOCKDET_CFG0);
writel_relaxed(0x1A, HDMI_PHY_PLL_LOCKDET_CFG1);
writel_relaxed(0x0D, HDMI_PHY_PLL_LOCKDET_CFG2);
writel_relaxed(0x2a, HDMI_PHY_PLL_VCOCAL_CFG0);
writel_relaxed(0x03, HDMI_PHY_PLL_VCOCAL_CFG1);
writel_relaxed(0x3B, HDMI_PHY_PLL_VCOCAL_CFG2);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG3);
writel_relaxed(0x86, HDMI_PHY_PLL_VCOCAL_CFG4);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG5);
writel_relaxed(0x33, HDMI_PHY_PLL_VCOCAL_CFG6);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG7);
break;
case 74250000:
/*
*/
writel_relaxed(0xA, HDMI_PHY_PLL_PWRDN_B);
writel_relaxed(0x12, HDMI_PHY_PLL_REFCLK_CFG);
writel_relaxed(0x01, HDMI_PHY_PLL_LOOP_FLT_CFG0);
writel_relaxed(0x33, HDMI_PHY_PLL_LOOP_FLT_CFG1);
writel_relaxed(0x76, HDMI_PHY_PLL_SDM_CFG0);
writel_relaxed(0xE6, HDMI_PHY_PLL_VCOCAL_CFG0);
writel_relaxed(0x02, HDMI_PHY_PLL_VCOCAL_CFG1);
writel_relaxed(0x3B, HDMI_PHY_PLL_VCOCAL_CFG2);
break;
case 108000000:
writel_relaxed(0x08, HDMI_PHY_PLL_REFCLK_CFG);
writel_relaxed(0x21, HDMI_PHY_PLL_LOOP_FLT_CFG0);
writel_relaxed(0xF9, HDMI_PHY_PLL_LOOP_FLT_CFG1);
writel_relaxed(0x1C, HDMI_PHY_PLL_VCOCAL_CFG0);
writel_relaxed(0x02, HDMI_PHY_PLL_VCOCAL_CFG1);
writel_relaxed(0x3B, HDMI_PHY_PLL_VCOCAL_CFG2);
writel_relaxed(0x86, HDMI_PHY_PLL_VCOCAL_CFG4);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG5);
writel_relaxed(0x49, HDMI_PHY_PLL_SDM_CFG0);
writel_relaxed(0x49, HDMI_PHY_PLL_SDM_CFG1);
writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG2);
writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG3);
writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG4);
break;
case 148500000:
/* */
writel_relaxed(0x2, HDMI_PHY_PLL_REFCLK_CFG);
writel_relaxed(0x2, HDMI_PHY_PLL_CHRG_PUMP_CFG);
writel_relaxed(0x01, HDMI_PHY_PLL_LOOP_FLT_CFG0);
writel_relaxed(0x33, HDMI_PHY_PLL_LOOP_FLT_CFG1);
writel_relaxed(0x2C, HDMI_PHY_PLL_IDAC_ADJ_CFG);
writel_relaxed(0x6, HDMI_PHY_PLL_I_VI_KVCO_CFG);
writel_relaxed(0xA, HDMI_PHY_PLL_PWRDN_B);
writel_relaxed(0x76, HDMI_PHY_PLL_SDM_CFG0);
writel_relaxed(0x01, HDMI_PHY_PLL_SDM_CFG1);
writel_relaxed(0x4C, HDMI_PHY_PLL_SDM_CFG2);
writel_relaxed(0xC0, HDMI_PHY_PLL_SDM_CFG3);
writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG4);
writel_relaxed(0x9A, HDMI_PHY_PLL_SSC_CFG0);
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG1);
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG2);
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG3);
writel_relaxed(0x10, HDMI_PHY_PLL_LOCKDET_CFG0);
writel_relaxed(0x1A, HDMI_PHY_PLL_LOCKDET_CFG1);
writel_relaxed(0x0D, HDMI_PHY_PLL_LOCKDET_CFG2);
writel_relaxed(0xe6, HDMI_PHY_PLL_VCOCAL_CFG0);
writel_relaxed(0x02, HDMI_PHY_PLL_VCOCAL_CFG1);
writel_relaxed(0x3B, HDMI_PHY_PLL_VCOCAL_CFG2);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG3);
writel_relaxed(0x86, HDMI_PHY_PLL_VCOCAL_CFG4);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG5);
writel_relaxed(0x33, HDMI_PHY_PLL_VCOCAL_CFG6);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG7);
break;
}
/* */
mb();
if (set_power_dwn)
hdmi_pll_enable();
if (!ahb_enabled)
writel_relaxed(ahb_en_reg & ~BIT(4), AHB_EN_REG);
return 0;
}
int hdmi_dtv_on()
{
uint32_t ahb_en_reg = readl(AHB_EN_REG);
uint32_t ahb_enabled = ahb_en_reg & BIT(4);
uint32_t val, pll_mode, ns_val, pll_config;
if (!ahb_enabled) {
dprintf(INFO, "ahb not enabled, turning on\n");
writel(ahb_en_reg | BIT(4), AHB_EN_REG);
/* Make sure iface clock is enabled before register access */
udelay(10);
}
if (hdmi_pll_on)
hdmi_pll_disable();
/* 1080p60/1080p50 case */
writel(0x2, HDMI_PHY_PLL_REFCLK_CFG);
writel(0x2, HDMI_PHY_PLL_CHRG_PUMP_CFG);
writel(0x01, HDMI_PHY_PLL_LOOP_FLT_CFG0);
writel(0x33, HDMI_PHY_PLL_LOOP_FLT_CFG1);
writel(0x2C, HDMI_PHY_PLL_IDAC_ADJ_CFG);
writel(0x6, HDMI_PHY_PLL_I_VI_KVCO_CFG);
writel(0xA, HDMI_PHY_PLL_PWRDN_B);
writel(0x76, HDMI_PHY_PLL_SDM_CFG0);
writel(0x01, HDMI_PHY_PLL_SDM_CFG1);
writel(0x4C, HDMI_PHY_PLL_SDM_CFG2);
writel(0xC0, HDMI_PHY_PLL_SDM_CFG3);
writel(0x00, HDMI_PHY_PLL_SDM_CFG4);
writel(0x9A, HDMI_PHY_PLL_SSC_CFG0);
writel(0x00, HDMI_PHY_PLL_SSC_CFG1);
writel(0x00, HDMI_PHY_PLL_SSC_CFG2);
writel(0x00, HDMI_PHY_PLL_SSC_CFG3);
writel(0x10, HDMI_PHY_PLL_LOCKDET_CFG0);
writel(0x1A, HDMI_PHY_PLL_LOCKDET_CFG1);
writel(0x0D, HDMI_PHY_PLL_LOCKDET_CFG2);
writel(0xe6, HDMI_PHY_PLL_VCOCAL_CFG0);
writel(0x02, HDMI_PHY_PLL_VCOCAL_CFG1);
writel(0x3B, HDMI_PHY_PLL_VCOCAL_CFG2);
writel(0x00, HDMI_PHY_PLL_VCOCAL_CFG3);
writel(0x86, HDMI_PHY_PLL_VCOCAL_CFG4);
writel(0x00, HDMI_PHY_PLL_VCOCAL_CFG5);
writel(0x33, HDMI_PHY_PLL_VCOCAL_CFG6);
writel(0x00, HDMI_PHY_PLL_VCOCAL_CFG7);
udelay(10);
hdmi_pll_enable();
if (!ahb_enabled)
writel(ahb_en_reg & ~BIT(4), AHB_EN_REG);
// set M N D
ns_val = readl(TV_NS_REG);
ns_val |= BIT(7);
writel(ns_val, TV_NS_REG);
writel(0x00, TV_MD_REG);
val = readl(TV_CC_REG);
val &= ~(BM(7, 6));
val |= CC(6, 0);
writel(val, TV_CC_REG);
ns_val &= ~BIT(7);
writel(ns_val, TV_NS_REG);
// confiure hdmi_ref clk to run @ 148.5 MHz
val = readl(MISC_CC2_REG);
val |= BIT(11);
writel(val, MISC_CC2_REG);
// Enable TV src clk
writel(0x03, TV_NS_REG);
// Enable hdmi clk
val = readl(TV_CC_REG);
val |= BIT(12);
writel(val, TV_CC_REG);
// De-Assert hdmi clk
val = readl(SW_RESET_CORE_REG);
val |= BIT(1);
writel(val, SW_RESET_CORE_REG);
udelay(10);
val = readl(SW_RESET_CORE_REG);
val &= ~(BIT(1));
writel(val, SW_RESET_CORE_REG);
udelay(10);
// Root en of tv src clk
val = readl(TV_CC_REG);
val |= BIT(2);
writel(val, TV_CC_REG);
// enable mdp dtv clk
val = readl(TV_CC_REG);
val |= BIT(0);
writel(val, TV_CC_REG);
udelay(10);
return 0;
}