/* Dispatch SCIs based on the PM1a_STS and PM1a_EN registers */
static void pmt_update_sci(PMTState *s)
{
ASSERT(spin_is_locked(&s->lock));
if ( s->pm.pm1a_en & s->pm.pm1a_sts & SCI_MASK )
hvm_isa_irq_assert(s->vcpu->domain, SCI_IRQ);
else
hvm_isa_irq_deassert(s->vcpu->domain, SCI_IRQ);
}
static uint32_t rtc_ioport_read(RTCState *s, uint32_t addr)
{
int ret;
struct domain *d = vrtc_domain(s);
if ( (addr & 1) == 0 )
return 0xff;
spin_lock(&s->lock);
switch ( s->hw.cmos_index )
{
case RTC_SECONDS:
case RTC_MINUTES:
case RTC_HOURS:
case RTC_DAY_OF_WEEK:
case RTC_DAY_OF_MONTH:
case RTC_MONTH:
case RTC_YEAR:
/* if not in set mode, adjust cmos before reading*/
if (!(s->hw.cmos_data[RTC_REG_B] & RTC_SET))
{
s->current_tm = gmtime(get_localtime(d));
rtc_copy_date(s);
}
ret = s->hw.cmos_data[s->hw.cmos_index];
break;
case RTC_REG_A:
ret = s->hw.cmos_data[s->hw.cmos_index];
if ((s->use_timer == 0) && update_in_progress(s))
ret |= RTC_UIP;
break;
case RTC_REG_C:
check_for_pf_ticks(s);
ret = s->hw.cmos_data[s->hw.cmos_index];
s->hw.cmos_data[RTC_REG_C] = 0x00;
if ( ret & RTC_IRQF )
hvm_isa_irq_deassert(d, RTC_IRQ);
check_update_timer(s);
alarm_timer_update(s);
s->pt_dead_ticks = 0;
break;
default:
ret = s->hw.cmos_data[s->hw.cmos_index];
break;
}
spin_unlock(&s->lock);
return ret;
}
static void rtc_update_irq(RTCState *s)
{
ASSERT(spin_is_locked(&s->lock));
if ( rtc_mode_is(s, strict) && (s->hw.cmos_data[RTC_REG_C] & RTC_IRQF) )
return;
/* IRQ is raised if any source is both raised & enabled */
if ( !(s->hw.cmos_data[RTC_REG_B] &
s->hw.cmos_data[RTC_REG_C] &
(RTC_PF | RTC_AF | RTC_UF)) )
return;
s->hw.cmos_data[RTC_REG_C] |= RTC_IRQF;
if ( rtc_mode_is(s, no_ack) )
hvm_isa_irq_deassert(vrtc_domain(s), RTC_IRQ);
hvm_isa_irq_assert(vrtc_domain(s), RTC_IRQ);
}
static void rtc_update_irq(RTCState *s)
{
struct domain *d = vrtc_domain(s);
uint8_t irqf;
ASSERT(spin_is_locked(&s->lock));
/* IRQ is raised if any source is both raised & enabled */
irqf = (s->hw.cmos_data[RTC_REG_B]
& s->hw.cmos_data[RTC_REG_C]
& (RTC_PF|RTC_AF|RTC_UF))
? RTC_IRQF : 0;
s->hw.cmos_data[RTC_REG_C] &= ~RTC_IRQF;
s->hw.cmos_data[RTC_REG_C] |= irqf;
hvm_isa_irq_deassert(d, RTC_IRQ);
if ( irqf )
hvm_isa_irq_assert(d, RTC_IRQ);
}
static void rtc_alarm_cb(void *opaque)
{
RTCState *s = opaque;
struct domain *d = vrtc_domain(s);
spin_lock(&s->lock);
if (!(s->hw.cmos_data[RTC_REG_B] & RTC_SET))
{
s->hw.cmos_data[RTC_REG_C] |= RTC_AF;
/* alarm interrupt */
if (s->hw.cmos_data[RTC_REG_B] & RTC_AIE)
{
s->hw.cmos_data[RTC_REG_C] |= RTC_IRQF;
hvm_isa_irq_deassert(d, RTC_IRQ);
hvm_isa_irq_assert(d, RTC_IRQ);
}
alarm_timer_update(s);
}
spin_unlock(&s->lock);
}
static void rtc_update_timer2(void *opaque)
{
RTCState *s = opaque;
struct domain *d = vrtc_domain(s);
spin_lock(&s->lock);
if (!(s->hw.cmos_data[RTC_REG_B] & RTC_SET))
{
s->hw.cmos_data[RTC_REG_C] |= RTC_UF;
s->hw.cmos_data[RTC_REG_A] &= ~RTC_UIP;
if ((s->hw.cmos_data[RTC_REG_B] & RTC_UIE))
{
s->hw.cmos_data[RTC_REG_C] |= RTC_IRQF;
hvm_isa_irq_deassert(d, RTC_IRQ);
hvm_isa_irq_assert(d, RTC_IRQ);
}
check_update_timer(s);
}
spin_unlock(&s->lock);
}
static int rtc_ioport_write(void *opaque, uint32_t addr, uint32_t data)
{
RTCState *s = opaque;
struct domain *d = vrtc_domain(s);
uint32_t orig;
spin_lock(&s->lock);
if ( (addr & 1) == 0 )
{
data &= 0x7f;
s->hw.cmos_index = data;
spin_unlock(&s->lock);
return (data < RTC_CMOS_SIZE);
}
if ( s->hw.cmos_index >= RTC_CMOS_SIZE )
{
spin_unlock(&s->lock);
return 0;
}
orig = s->hw.cmos_data[s->hw.cmos_index];
switch ( s->hw.cmos_index )
{
case RTC_SECONDS_ALARM:
case RTC_MINUTES_ALARM:
case RTC_HOURS_ALARM:
s->hw.cmos_data[s->hw.cmos_index] = data;
alarm_timer_update(s);
break;
case RTC_SECONDS:
case RTC_MINUTES:
case RTC_HOURS:
case RTC_DAY_OF_WEEK:
case RTC_DAY_OF_MONTH:
case RTC_MONTH:
case RTC_YEAR:
s->hw.cmos_data[s->hw.cmos_index] = data;
/* if in set mode, do not update the time */
if ( !(s->hw.cmos_data[RTC_REG_B] & RTC_SET) )
rtc_set_time(s);
alarm_timer_update(s);
break;
case RTC_REG_A:
/* UIP bit is read only */
s->hw.cmos_data[RTC_REG_A] = (data & ~RTC_UIP) | (orig & RTC_UIP);
if ( (data ^ orig) & ~RTC_UIP )
rtc_timer_update(s);
break;
case RTC_REG_B:
if ( data & RTC_SET )
{
/* set mode: reset UIP mode */
s->hw.cmos_data[RTC_REG_A] &= ~RTC_UIP;
/* adjust cmos before stopping */
if (!(s->hw.cmos_data[RTC_REG_B] & RTC_SET))
{
s->current_tm = gmtime(get_localtime(d));
rtc_copy_date(s);
}
}
else
{
/* if disabling set mode, update the time */
if ( s->hw.cmos_data[RTC_REG_B] & RTC_SET )
rtc_set_time(s);
}
/* if the interrupt is already set when the interrupt become
* enabled, raise an interrupt immediately*/
if ((data & RTC_UIE) && !(s->hw.cmos_data[RTC_REG_B] & RTC_UIE))
if (s->hw.cmos_data[RTC_REG_C] & RTC_UF)
{
hvm_isa_irq_deassert(d, RTC_IRQ);
hvm_isa_irq_assert(d, RTC_IRQ);
}
s->hw.cmos_data[RTC_REG_B] = data;
if ( (data ^ orig) & RTC_PIE )
rtc_timer_update(s);
check_update_timer(s);
alarm_timer_update(s);
break;
case RTC_REG_C:
case RTC_REG_D:
/* cannot write to them */
break;
}
spin_unlock(&s->lock);
return 1;
}
