static __fi int IPU1chain() {
int totalqwc = 0;
if (ipu1ch.qwc > 0 && IPU1Status.InProgress)
{
int qwc = ipu1ch.qwc;
u32 *pMem;
pMem = (u32*)dmaGetAddr(ipu1ch.madr, false);
if (pMem == NULL)
{
Console.Error("ipu1dma NULL!");
return totalqwc;
}
//Write our data to the fifo
qwc = ipu_fifo.in.write(pMem, qwc);
ipu1ch.madr += qwc << 4;
ipu1ch.qwc -= qwc;
totalqwc += qwc;
}
//Update TADR etc
hwDmacSrcTadrInc(ipu1ch);
if( ipu1ch.qwc == 0)
IPU1Status.InProgress = false;
return totalqwc;
}
// Write from the EE to Fifo.
static __fi bool WriteEEtoFifo()
{
// There's some data ready to transfer into the fifo..
SIF_LOG("Sif 1: Write EE to Fifo");
const int writeSize = min((s32)sif1dma.qwc, sif1.fifo.sif_free() >> 2);
tDMA_TAG *ptag;
ptag = sif1dma.getAddr(sif1dma.madr, DMAC_SIF1, false);
if (ptag == NULL)
{
DevCon.Warning("Write EE to Fifo: ptag == NULL");
return false;
}
sif1.fifo.write((u32*)ptag, writeSize << 2);
sif1dma.madr += writeSize << 4;
hwDmacSrcTadrInc(sif1dma);
sif1.ee.cycles += writeSize; // fixme : BIAS is factored in above
sif1dma.qwc -= writeSize;
return true;
}
void incGifChAddr(u32 qwc) {
if (gifch.chcr.STR) {
gifch.madr += qwc * 16;
gifch.qwc -= qwc;
hwDmacSrcTadrInc(gifch);
}
else DevCon.Error("incGifAddr() Error!");
}
int _SPR1chain()
{
tDMA_TAG *pMem;
if (spr1ch.qwc == 0) return 0;
pMem = SPRdmaGetAddr(spr1ch.madr, false);
if (pMem == NULL) return -1;
int partialqwc = 0;
//Taking an arbitary small value for games which like to check the QWC/MADR instead of STR, so get most of
//the cycle delay out of the way before the end.
partialqwc = spr1ch.qwc;
SPR1transfer(pMem, partialqwc);
spr1ch.madr += partialqwc * 16;
spr1ch.qwc -= partialqwc;
hwDmacSrcTadrInc(spr1ch);
return (partialqwc);
}
