/*
Init hardware...
A ROM image must have been loaded before calling this function.
*/
int hw_init(void)
{
IMG_INFO *img = &img_infos;
// Get infos from image
tihw.calc_type = img_infos.calc_type;
tihw.rom_base = img->rom_base << 16;
tihw.rom_flash = img->flash;
strcpy(tihw.rom_version, img->version);
tihw.hw_type = img->hw_type;
tihw.ti92v1 = (tihw.calc_type == TI92) && (strcmp(tihw.rom_version, "2.0") < 0);
tihw.ti92v2 = (tihw.calc_type == TI92) && (strcmp(tihw.rom_version, "2.0") >= 0);
switch(tihw.calc_type)
{
case TI89:
case TI89t:
tihw.log_w = tihw.lcd_w = 160;
tihw.log_h = tihw.lcd_h = 100;
break;
case TI92:
case TI92p:
case V200:
tihw.log_w = tihw.lcd_w = 240;
tihw.log_h = tihw.lcd_h = 128;
break;
default:
return -1;
break;
}
// Do sub-initializations.
TRY(hw_mem_init());
TRY(hw_flash_init());
TRY(hw_io_init());
TRY(hw_hwp_init());
TRY(hw_dbus_init());
TRY(hw_kbd_init());
TRY(hw_m68k_init());
// Set hardware update rate (dependant from io[0x15])
if(params.hw_rate != -1)
cycle_instr = params.hw_rate;
else if(tihw.hw_type == HW1)
cycle_instr = HW1_RATE;
else if(tihw.hw_type <= HW3)
cycle_instr = HW2_RATE;
else
cycle_instr = HW4_RATE;
return 0;
}
int ti68k_linkport_reconfigure(void)
{
return hw_dbus_init();
}
