_RB_INLINE bool i2cmaster_Start1(int dev, unsigned char addr, unsigned char rwbit) {
if (i2c_IsMaster(dev) == false)
{
err_SetMsg(ERROR_I2CWRONGUSAGE, "can't start a transaction in Slave state");
return false;
}
i2cmaster_WriteAddrREG(dev, addr, rwbit);
//Remarks: if I2C master sends "Start" twice sequently, ARLoss will occur according to H/W design
return check_TX_done(dev);
}
_RB_INLINE bool i2cmaster_Start1(int dev, unsigned char addr, unsigned char rwbit) {
if (i2c_IsMaster(dev) == false)
{
err_SetMsg(ERROR_I2CWRONGUSAGE, "can't start a transaction in Slave state");
return false;
}
i2cmaster_WriteAddrREG(dev, addr, rwbit);
//Remarks: if I2C master sends "Start" twice sequently, ARLoss will occur according to H/W design
if (check_TX_done(dev) == false) return false;
I2C_action[dev] = (rwbit == I2C_WRITE)? I2CACT_MASTERWRITE : I2CACT_MASTERREAD;
I2C_curAddr = addr;
return true;
}
/******************** Slave Functions for Individual Module *****************/
RBAPI(unsigned) i2cslave_Listen(int dev) {
unsigned char i2cstat;
switch (I2C_action[dev])
{
case I2CACT_IDLE:
if (i2c_IsMaster(dev) == true) return I2CSLAVE_NOTHING;
I2C_action[dev] = I2CACT_SLAVE;
return I2CSLAVE_START;
case I2CACT_SLAVE:
i2cstat = i2c_ReadStatREG(dev);
if ((i2cstat & I2CSTAT_RXRDY) != 0)
{
I2C_action[dev] = I2CACT_SLAVEREADREQ;
return I2CSLAVE_READREQUEST;
}
if ((i2cstat & I2CSTAT_SLAVESTOPPED) != 0)
{
i2c_ClearSTAT(dev, I2CSTAT_ALL);
I2C_action[dev] = I2CACT_IDLE;
return I2CSLAVE_END;
}
if ((i2cstat & I2CSTAT_SLAVEWREQ) != 0)
{
I2C_action[dev] = I2CACT_SLAVEWRITEREQ;
return I2CSLAVE_WRITEREQUEST;
}
return I2CSLAVE_WAITING;
case I2CACT_SLAVEWRITEREQ:
case I2CACT_SLAVEREADREQ:
err_SetMsg(ERROR_I2CWRONGUSAGE, "must deal with the salve read/write request");
break;
case I2CACT_DISABLE:
err_SetMsg(ERROR_I2CWRONGUSAGE, "must enable the I2C module first");
break;
default:
err_SetMsg(ERROR_I2CWRONGUSAGE, "can't use %s() when I2C master is working", __FUNCTION__);
break;
}
return 0xffff;
}
