/* * i2c_init - initialize the i2c bus * * speed: bus speed (in HZ) * slaveaddr: address of device in slave mode * * Slave mode is not implemented. */ void i2c_init(int speed, int slaveaddr) { struct u5500_i2c_regs *i2c_regs; debug("i2c_init bus %d, speed %d\n", i2c_bus_num, speed); u5500_clock_enable(i2c_clock_bits[i2c_bus_num].periph, i2c_clock_bits[i2c_bus_num].pcken, i2c_clock_bits[i2c_bus_num].kcken); i2c_regs = i2c_dev[i2c_bus_num]; /* Disable the controller */ i2c_clr_bit(&i2c_regs->cr, I2C_CR_PE); /* Clear registers */ writel(0, &i2c_regs->cr); writel(0, &i2c_regs->scr); writel(0, &i2c_regs->hsmcr); writel(0, &i2c_regs->tftr); writel(0, &i2c_regs->rftr); writel(0, &i2c_regs->dmar); i2c_bus_speed[i2c_bus_num] = __i2c_set_bus_speed(speed); /* * Set our own address. * Set slave address mode to 7 bit addressing mode */ i2c_clr_bit(&i2c_regs->cr, I2C_CR_SAM); i2c_write_field(&i2c_regs->scr, I2C_SCR_ADDR, I2C_SCR_SHIFT_ADDR, slaveaddr); /* Slave Data Set up Time */ i2c_write_field(&i2c_regs->scr, I2C_SCR_DATA_SETUP_TIME, I2C_SCR_SHIFT_DATA_SETUP_TIME, SLAVE_SETUP_TIME); /* Disable the DMA sync logic */ i2c_write_field(&i2c_regs->cr, I2C_CR_DMA_SLE, I2C_CR_SHIFT_DMA_SLE, 0); /* Disable interrupts */ writel(0, &i2c_regs->imscr); /* Configure bus master mode */ i2c_write_field(&i2c_regs->cr, I2C_CR_OM, I2C_CR_SHIFT_OM, I2C_BUS_MASTER_MODE); /* Set FIFO threshold values */ writel(TX_FIFO_THRESHOLD, &i2c_regs->tftr); writel(RX_FIFO_THRESHOLD, &i2c_regs->rftr); /* Enable the I2C Controller */ i2c_set_bit(&i2c_regs->cr, I2C_CR_PE); bus_initialized[i2c_bus_num] = 1; }
/** * init_hw() - initialize the I2C hardware * @dev: private data of I2C Driver */ static int init_hw(struct nmk_i2c_dev *dev) { int stat; stat = flush_i2c_fifo(dev); if (stat) return stat; /* disable the controller */ i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE); disable_all_interrupts(dev); clear_all_interrupts(dev); dev->cli.operation = I2C_NO_OPERATION; return 0; }