static inline int i2c_do_write(i2c_t *obj, int value) {
int timeout = 0;
if (!(i2c_status(obj) & SR2_NACKF)) {
/* RIICnSR2.NACKF=0 */
/* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
while (!(i2c_status(obj) & SR2_TDRE)) {
/* RIICnSR2.TDRE=0 */
timeout ++;
if (timeout >= TIMEOUT_1S) {
return -1;
}
if (i2c_status(obj) & SR2_NACKF) {
/* RIICnSR2.NACKF=1 */
return -1;
}
}
/* write the data */
REG(DRT.UINT32) = value;
} else {
return -1;
}
return 0;
}
int i2c_slave_read(i2c_t *obj, char *data, int length) {
int count = 0;
int status;
do {
i2c_clear_SI(obj);
i2c_wait_SI(obj);
status = i2c_status(obj);
if((status == 0x80) || (status == 0x90)) {
data[count] = I2C_DAT(obj) & 0xFF;
}
count++;
} while (((status == 0x80) || (status == 0x90) ||
(status == 0x060) || (status == 0x70)) && (count < length));
// Clear old status and wait for Serial Interrupt.
i2c_clear_SI(obj);
i2c_wait_SI(obj);
// Obtain new status.
status = i2c_status(obj);
if(status != 0xA0) {
i2c_stop(obj);
}
i2c_clear_SI(obj);
return count;
}
int i2c_byte_write(i2c_t *obj, int data) {
int ack = 0;
int status;
int timeout = 0;
status = i2c_do_write(obj, (data & 0xFF));
if (status != 0) {
i2c_set_SR2_NACKF_STOP(obj);
} else {
while (((i2c_status(obj) & SR2_RDRF) == 0) && ((i2c_status(obj) & SR2_TEND) == 0)) {
timeout++;
if (timeout >= WAIT_TIMEOUT) {
return ack;
}
}
/* check ACK/NACK */
if ((REG(SR2.UINT32) & SR2_NACKF) != 0) {
/* NACK */
i2c_set_SR2_NACKF_STOP(obj);
} else {
ack = 1;
}
}
return ack;
}
static inline int i2c_do_write(i2c_t *obj, int value) {
// write the data
if (!(i2c_status(obj) & NACKF)) { // NACF=0
i2c_wait_TDRE(obj);
REG(DRT.UINT32) = value;
} else {
return 0xff;
}
return i2c_status(obj);
}
uint8_t TwoWire::requestFrom(uint8_t address, uint8_t length, uint8_t sendStop)
{
uint8_t tmp __attribute__((unused));
uint8_t status, count=0;
rxBufferIndex = 0;
rxBufferLength = 0;
//serial_print("requestFrom\n");
// clear the status flags
I2C0_S = I2C_S_IICIF | I2C_S_ARBL;
// now take control of the bus...
if (I2C0_C1 & I2C_C1_MST) {
// we are already the bus master, so send a repeated start
I2C0_C1 = I2C_C1_IICEN | I2C_C1_MST | I2C_C1_RSTA | I2C_C1_TX;
} else {
// we are not currently the bus master, so wait for bus ready
while (i2c_status() & I2C_S_BUSY) ;
// become the bus master in transmit mode (send start)
slave_mode = 0;
I2C0_C1 = I2C_C1_IICEN | I2C_C1_MST | I2C_C1_TX;
}
// send the address
I2C0_D = (address << 1) | 1;
i2c_wait();
status = i2c_status();
if ((status & I2C_S_RXAK) || (status & I2C_S_ARBL)) {
// the slave device did not acknowledge
// or we lost bus arbitration to another master
I2C0_C1 = I2C_C1_IICEN;
return 0;
}
if (length == 0) {
// TODO: does anybody really do zero length reads?
// if so, does this code really work?
I2C0_C1 = I2C_C1_IICEN | (sendStop ? 0 : I2C_C1_MST);
return 0;
} else if (length == 1) {
I2C0_C1 = I2C_C1_IICEN | I2C_C1_MST | I2C_C1_TXAK;
} else {
I2C0_C1 = I2C_C1_IICEN | I2C_C1_MST;
}
tmp = I2C0_D; // initiate the first receive
while (length > 1) {
i2c_wait();
length--;
if (length == 1) I2C0_C1 = I2C_C1_IICEN | I2C_C1_MST | I2C_C1_TXAK;
rxBuffer[count++] = I2C0_D;
}
i2c_wait();
I2C0_C1 = I2C_C1_IICEN | I2C_C1_MST | I2C_C1_TX;
rxBuffer[count++] = I2C0_D;
if (sendStop) I2C0_C1 = I2C_C1_IICEN;
rxBufferLength = count;
return count;
}
//New version WH, Tested OK for Start and Repeated Start
//Old version was Wrong: Calls i2c_start without setting address, i2c_do_read continues before checking status, status check for wrong value
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
int count, status;
//Store the address+RD and then generate STA
I2C_DAT(obj) = address | 0x01;
i2c_start(obj);
// Wait for completion of STA and Sending of SlaveAddress+RD and first Read byte
i2c_wait_SI(obj);
status = i2c_status(obj);
if (status == 0x03) { // NAK on SlaveAddress
i2c_stop(obj);
return I2C_ERROR_NO_SLAVE;
}
// Read in all except last byte
for (count = 0; count < (length-1); count++) {
// Wait for it to arrive, note that first byte read after address+RD is already waiting
i2c_wait_SI(obj);
status = i2c_status(obj);
if (status != 0x01) { // RX RDY
i2c_stop(obj);
return count;
}
data[count] = I2C_DAT(obj) & 0xFF; // Store read byte
obj->i2c->MSTCTL = (1 << 0); // Send ACK and Continue to read
}
// Read final byte
// Wait for it to arrive
i2c_wait_SI(obj);
status = i2c_status(obj);
if (status != 0x01) { // RX RDY
i2c_stop(obj);
return count;
}
data[count] = I2C_DAT(obj) & 0xFF; // Store final read byte
// If not repeated start, send stop.
if (stop) {
i2c_stop(obj); // Also sends NAK for last read byte
} else {
repeated_start = 1;
}
return length;
}
int i2c_slave_read(i2c_t *obj, char *data, int length) {
int timeout = 0;
int count;
int break_flg = 0;
if(length <= 0) {
return 0;
}
for (count = 0; ((count < (length + 1)) && (break_flg == 0)); count++) {
/* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
while ((i2c_status(obj) & SR2_STOP) || (!(i2c_status(obj) & SR2_RDRF))) {
/* RIICnSR2.STOP = 1 or RIICnSR2.RDRF = 0 */
if (i2c_status(obj) & SR2_STOP) {
/* RIICnSR2.STOP = 1 */
break_flg = 1;
break;
}
timeout ++;
if (timeout >= TIMEOUT_1S) {
return -1;
}
}
if (break_flg == 0) {
if (count == 0) {
/* dummy read */
(void)REG(DRR.UINT32);
} else {
data[count - 1] = (char)(REG(DRR.UINT32) & 0xFF);
}
}
}
if (break_flg == 0) {
(void)i2c_wait_STOP(obj);
} else {
if (i2c_status(obj) & SR2_RDRF) {
if (count <= 1) {
/* fail safe */
/* dummy read */
(void)REG(DRR.UINT32);
} else {
data[count - 2] = (char)(REG(DRR.UINT32) & 0xFF);
}
}
}
/* SR2.STOP = 0 */
REG(SR2.UINT32) &= ~SR2_STOP;
return (count - 1);
}
inline int i2c_start(i2c_t *obj) {
int status = 0;
int isInterrupted = I2C_CONSET(obj) & (1 << 3);
// 8.1 Before master mode can be entered, I2CON must be initialised to:
// - I2EN STA STO SI AA - -
// - 1 0 0 x x - -
// if AA = 0, it can't enter slave mode
i2c_conclr(obj, 1, 1, 0, 1);
// The master mode may now be entered by setting the STA bit
// this will generate a start condition when the bus becomes free
i2c_conset(obj, 1, 0, 0, 1);
// Clearing SI bit when it wasn't set on entry can jump past state
// 0x10 or 0x08 and erroneously send uninitialized slave address.
if (isInterrupted)
i2c_clear_SI(obj);
i2c_wait_SI(obj);
status = i2c_status(obj);
// Clear start bit now that it's transmitted
i2c_conclr(obj, 1, 0, 0, 0);
return status;
}
//New version WH, Tested OK for Start and Repeated Start
//Old version was Wrong: Calls i2c_start without setting address first
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
int i, status;
//Store the address+/WR and then generate STA
I2C_DAT(obj) = address & 0xFE;
i2c_start(obj);
// Wait for completion of STA and Sending of SlaveAddress+/WR
i2c_wait_SI(obj);
status = i2c_status(obj);
if (status == 0x03) { // NAK SlaveAddress
i2c_stop(obj);
return I2C_ERROR_NO_SLAVE;
}
//Write all bytes
for (i=0; i<length; i++) {
status = i2c_do_write(obj, data[i], 0);
if (status != 0x02) { // TX RDY. Handles a Slave NAK on datawrite
i2c_stop(obj);
return i;
}
}
// If not repeated start, send stop.
if (stop) {
i2c_stop(obj);
} else {
repeated_start = 1;
}
return length;
}
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
int count, status;
status = i2c_start(obj);
if ((status != 0x10) && (status != 0x08)) {
i2c_stop(obj);
return status;
}
status = i2c_do_write(obj, (address | 0x01));
if (status != 0x40) {
i2c_stop(obj);
return status;
}
// Read in all except last byte
for (count = 0; count < (length - 1); count++) {
int value = i2c_do_read(obj, 0);
status = i2c_status(obj);
if (status != 0x50) {
i2c_stop(obj);
return status;
}
data[count] = (char) value;
}
// read in last byte
int value = i2c_do_read(obj, 1);
status = i2c_status(obj);
if (status != 0x58) {
i2c_stop(obj);
return status;
}
data[count] = (char) value;
// If not repeated start, send stop.
if (stop) {
if(i2c_stop(obj) == 1)
return 1;
}
return 0;
}
// Wait until the Trans Data Empty (TDRE) is set
static int i2c_wait_TDRE(i2c_t *obj) {
int timeout = 0;
while (!(i2c_status(obj) & (1 << 7))) {
timeout ++;
if (timeout > 100000) return -1;
}
return 0;
}
uint8_t distco_transmit()
{
if (i2c_start_transmission()==0)
return 0;
if (i2c_wait_transmission()==0)
return 0;
if (i2c_status()!=I2C_SUCCESS)
return 0;
return 1;
}
/*---------------------------------------------------------------------------*/
bool
board_i2c_write(uint8_t *data, uint8_t len)
{
uint32_t i;
bool success;
/* Write slave address */
ti_lib_i2c_master_slave_addr_set(I2C0_BASE, slave_addr, false);
/* Write first byte */
ti_lib_i2c_master_data_put(I2C0_BASE, data[0]);
/* Check if another master has access */
while(ti_lib_i2c_master_bus_busy(I2C0_BASE));
/* Assert RUN + START */
ti_lib_i2c_master_control(I2C0_BASE, I2C_MASTER_CMD_BURST_SEND_START);
while(ti_lib_i2c_master_busy(I2C0_BASE));
success = i2c_status();
for(i = 1; i < len && success; i++) {
/* Write next byte */
ti_lib_i2c_master_data_put(I2C0_BASE, data[i]);
if(i < len - 1) {
/* Clear START */
ti_lib_i2c_master_control(I2C0_BASE, I2C_MASTER_CMD_BURST_SEND_CONT);
while(ti_lib_i2c_master_busy(I2C0_BASE));
success = i2c_status();
}
}
/* Assert stop */
if(success) {
/* Assert STOP */
ti_lib_i2c_master_control(I2C0_BASE, I2C_MASTER_CMD_BURST_SEND_FINISH);
while(ti_lib_i2c_master_busy(I2C0_BASE));
success = i2c_status();
while(ti_lib_i2c_master_bus_busy(I2C0_BASE));
}
return success;
}
//Spec says: first check Idle and status is Ok
static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
// write the data
I2C_DAT(obj) = value;
if (!addr)
obj->i2c->MSTCTL = (1 << 0); //Set continue for data. Should not be set for addr since that uses STA
// wait and return status
i2c_wait_SI(obj);
return i2c_status(obj);
}
static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
// write the data
I2C_DAT(obj) = value;
// clear SI to init a send
i2c_clear_SI(obj);
// wait and return status
i2c_wait_SI(obj);
return i2c_status(obj);
}
static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
// write the data
I2C_DAT(obj) = value;
if (!addr)
obj->i2c->MSTCTL = (1 << 0);
// wait and return status
i2c_wait_SI(obj);
return i2c_status(obj);
}
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
int count, status;
i2c_start(obj);
status = i2c_do_write(obj, (address | 0x01), 1);
if (status != 0x01) {
i2c_stop(obj);
return I2C_ERROR_NO_SLAVE;
}
// Read in all except last byte
for (count = 0; count < (length - 1); count++) {
int value = i2c_do_read(obj, 0);
status = i2c_status(obj);
if (status != 0x00) {
i2c_stop(obj);
return count;
}
data[count] = (char) value;
}
// read in last byte
int value = i2c_do_read(obj, 1);
status = i2c_status(obj);
if (status != 0x01) {
i2c_stop(obj);
return length - 1;
}
data[count] = (char) value;
// If not repeated start, send stop.
if (stop) {
i2c_stop(obj);
} else {
repeated_start = 1;
}
return length;
}
static void i2c_wait(void)
{
#if 0
while (!(I2C0_S & I2C_S_IICIF)) ; // wait
I2C0_S = I2C_S_IICIF;
#endif
//Serial.write('^');
while (1) {
if ((i2c_status() & I2C_S_IICIF)) break;
}
I2C0_S = I2C_S_IICIF;
}
static int i2c_wait_START(i2c_t *obj) {
int timeout = 0;
/* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
while (!(i2c_status(obj) & SR2_START)) {
timeout ++;
if (timeout >= TIMEOUT_1S) {
return -1;
}
}
return 0;
}
static int i2c_wait_STOP(i2c_t *obj) {
int timeout = 0;
/* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
while ((i2c_status(obj) & SR2_STOP) == 0) {
timeout ++;
if (timeout >= WAIT_TIMEOUT) {
return -1;
}
}
return 0;
}
/*---------------------------------------------------------------------------*/
bool
board_i2c_read(uint8_t *data, uint8_t len)
{
uint8_t i;
bool success;
/* Set slave address */
ti_lib_i2c_master_slave_addr_set(I2C0_BASE, slave_addr, true);
/* Check if another master has access */
while(ti_lib_i2c_master_bus_busy(I2C0_BASE));
/* Assert RUN + START + ACK */
ti_lib_i2c_master_control(I2C0_BASE, I2C_MASTER_CMD_BURST_RECEIVE_START);
i = 0;
success = true;
while(i < (len - 1) && success) {
while(ti_lib_i2c_master_busy(I2C0_BASE));
success = i2c_status();
if(success) {
data[i] = ti_lib_i2c_master_data_get(I2C0_BASE);
ti_lib_i2c_master_control(I2C0_BASE, I2C_MASTER_CMD_BURST_RECEIVE_CONT);
i++;
}
}
if(success) {
ti_lib_i2c_master_control(I2C0_BASE, I2C_MASTER_CMD_BURST_RECEIVE_FINISH);
while(ti_lib_i2c_master_busy(I2C0_BASE));
success = i2c_status();
if(success) {
data[len - 1] = ti_lib_i2c_master_data_get(I2C0_BASE);
while(ti_lib_i2c_master_bus_busy(I2C0_BASE));
}
}
return success;
}
int i2c_slave_receive(i2c_t *obj) {
int status;
int retval;
status = i2c_status(obj);
switch(status) {
case 0x60: retval = 3; break;
case 0x70: retval = 2; break;
case 0xA8: retval = 1; break;
default : retval = 0; break;
}
return(retval);
}
static inline int i2c_do_write(i2c_t *obj, int value) {
int timeout = 0;
/* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
while ((i2c_status(obj) & SR2_TDRE) == 0) {
timeout ++;
if (timeout >= WAIT_TIMEOUT) {
return -1;
}
}
/* write the data */
REG(DRT.UINT32) = value;
return 0;
}
bool TwoWire::wait_idle(void)
{
bool reset=false;
uint32_t wait_begin = millis();
//Serial.print("busy:");
while (i2c_status() & I2C_S_BUSY) {
//Serial.write('.') ;
uint32_t waited = millis() - wait_begin;
#if 1
if (waited > 15 && !reset) {
reset = true;
//Serial.println("attempt forced reset");
uint8_t sda_pin = hardware.sda_pin[sda_pin_index];
pinMode(sda_pin, INPUT_DISABLE);
uint8_t scl_pin = hardware.scl_pin[sda_pin_index];
pinMode(scl_pin, OUTPUT);
for (int i=0; i < 9; i++) {
digitalWrite(scl_pin, LOW);
delayMicroseconds(5);
digitalWrite(scl_pin, HIGH);
delayMicroseconds(5);
}
uint32_t mux;
volatile uint32_t *reg;
reg = portConfigRegister(hardware.sda_pin[sda_pin_index]);
mux = PORT_PCR_MUX(hardware.sda_mux[sda_pin_index]);
*reg = mux|PORT_PCR_ODE|PORT_PCR_SRE|PORT_PCR_DSE;
reg = portConfigRegister(hardware.scl_pin[scl_pin_index]);
mux = PORT_PCR_MUX(hardware.scl_mux[scl_pin_index]);
*reg = mux|PORT_PCR_ODE|PORT_PCR_SRE|PORT_PCR_DSE;
delayMicroseconds(10);
continue;
}
#endif
if (waited > 16) {
// bus stuck busy too long
port().C1 = 0;
port().C1 = I2C_C1_IICEN;
//Serial.println("abort");
//return 4; // timeout waiting for bus
return false;
}
}
return true;
}
/*---------------------------------------------------------------------------*/
bool
board_i2c_write_single(uint8_t data)
{
/* Write slave address */
ti_lib_i2c_master_slave_addr_set(I2C0_BASE, slave_addr, false);
/* Write first byte */
ti_lib_i2c_master_data_put(I2C0_BASE, data);
/* Check if another master has access */
while(ti_lib_i2c_master_bus_busy(I2C0_BASE));
/* Assert RUN + START + STOP */
ti_lib_i2c_master_control(I2C0_BASE, I2C_MASTER_CMD_SINGLE_SEND);
while(ti_lib_i2c_master_busy(I2C0_BASE));
return i2c_status();
}
inline int i2c_start(i2c_t *obj) {
int status = 0;
// 8.1 Before master mode can be entered, I2CON must be initialised to:
// - I2EN STA STO SI AA - -
// - 1 0 0 0 x - -
// if AA = 0, it can't enter slave mode
i2c_conclr(obj, 1, 1, 1, 1);
// The master mode may now be entered by setting the STA bit
// this will generate a start condition when the bus becomes free
i2c_conset(obj, 1, 0, 0, 1);
i2c_wait_SI(obj);
status = i2c_status(obj);
// Clear start bit now transmitted, and interrupt bit
i2c_conclr(obj, 1, 0, 0, 0);
return status;
}
int i2c_slave_read(i2c_t *obj, char *data, int length) {
int count = 0;
int status;
do {
i2c_clear_SI(obj);
i2c_wait_SI(obj);
status = i2c_status(obj);
if((status == 0x80) || (status == 0x90)) {
data[count] = I2C_DAT(obj) & 0xFF;
}
count++;
} while (((status == 0x80) || (status == 0x90) ||
(status == 0x060) || (status == 0x70)) && (count < length));
if(status != 0xA0) {
i2c_stop(obj);
}
i2c_clear_SI(obj);
return count;
}
int i2c_slave_read(i2c_t *obj, char *data, int length) {
int count = 0;
int status;
volatile int dummy = REG(DRR.UINT32) ;
do {
i2c_wait_RDRF(obj);
status = i2c_status(obj);
if(!(status & 0x10)) {
data[count] = REG(DRR.UINT32) & 0xFF;
}
count++;
} while ( !(status & 0x10) && (count < length) );
if(status & 0x10) {
i2c_stop(obj);
i2c_wait_STOP(obj);
}
//i2c_clear_TDRE(obj);
return count;
}
/**
* NOTE: The technique is not the same as that used in TinyVM.
* The return value indicates the impact of the call on the VM
* system. EXEC_CONTINUE normal return the system should return to the return
* address provided by the VM. EXEC_RUN The call has modified the value of
* VM PC and this should be used to restart execution. EXEC_RETRY The call
* needs to be re-tried (typically for a GC failure), all global state
* should be left intact, the PC has been set appropriately.
*
*/
int dispatch_native(TWOBYTES signature, STACKWORD * paramBase)
{
STACKWORD p0 = paramBase[0];
switch (signature) {
case wait_4_5V:
return monitor_wait((Object *) word2ptr(p0), 0);
case wait_4J_5V:
return monitor_wait((Object *) word2ptr(p0), ((int)paramBase[1] > 0 ? 0x7fffffff : paramBase[2]));
case notify_4_5V:
return monitor_notify((Object *) word2ptr(p0), false);
case notifyAll_4_5V:
return monitor_notify((Object *) word2ptr(p0), true);
case start_4_5V:
// Create thread, allow for instruction restart
return init_thread((Thread *) word2ptr(p0));
case yield_4_5V:
schedule_request(REQUEST_SWITCH_THREAD);
break;
case sleep_4J_5V:
sleep_thread(((int)p0 > 0 ? 0x7fffffff : paramBase[1]));
schedule_request(REQUEST_SWITCH_THREAD);
break;
case getPriority_4_5I:
push_word(get_thread_priority((Thread *) word2ptr(p0)));
break;
case setPriority_4I_5V:
{
STACKWORD p = (STACKWORD) paramBase[1];
if (p > MAX_PRIORITY || p < MIN_PRIORITY)
return throw_new_exception(JAVA_LANG_ILLEGALARGUMENTEXCEPTION);
else
set_thread_priority((Thread *) word2ptr(p0), p);
}
break;
case currentThread_4_5Ljava_3lang_3Thread_2:
push_ref(ptr2ref(currentThread));
break;
case interrupt_4_5V:
interrupt_thread((Thread *) word2ptr(p0));
break;
case interrupted_4_5Z:
{
JBYTE i = currentThread->interruptState != INTERRUPT_CLEARED;
currentThread->interruptState = INTERRUPT_CLEARED;
push_word(i);
}
break;
case isInterrupted_4_5Z:
push_word(((Thread *) word2ptr(p0))->interruptState
!= INTERRUPT_CLEARED);
break;
case join_4_5V:
join_thread((Thread *) word2ptr(p0), 0);
break;
case join_4J_5V:
join_thread((Thread *) word2obj(p0), paramBase[2]);
break;
case halt_4I_5V:
schedule_request(REQUEST_EXIT);
break;
case shutdown_4_5V:
shutdown_program(false);
break;
case currentTimeMillis_4_5J:
push_word(0);
push_word(systick_get_ms());
break;
case readSensorValue_4I_5I:
push_word(sp_read(p0, SP_ANA));
break;
case setPowerTypeById_4II_5V:
sp_set_power(p0, paramBase[1]);
break;
case freeMemory_4_5J:
push_word(0);
push_word(getHeapFree());
break;
case totalMemory_4_5J:
push_word(0);
push_word(getHeapSize());
break;
case floatToRawIntBits_4F_5I: // Fall through
case intBitsToFloat_4I_5F:
push_word(p0);
break;
case doubleToRawLongBits_4D_5J: // Fall through
case longBitsToDouble_4J_5D:
push_word(p0);
push_word(paramBase[1]);
break;
case drawString_4Ljava_3lang_3String_2II_5V:
{
String *p = (String *)word2obj(p0);
Object *charArray;
if (!p) return throw_new_exception(JAVA_LANG_NULLPOINTEREXCEPTION);
charArray = (Object *) word2ptr(get_word_4_ns(fields_start(p)));
if (!charArray) return throw_new_exception(JAVA_LANG_NULLPOINTEREXCEPTION);
display_goto_xy(paramBase[1], paramBase[2]);
display_jstring(p);
}
break;
case drawInt_4III_5V:
display_goto_xy(paramBase[1], paramBase[2]);
display_int(p0, 0);
break;
case drawInt_4IIII_5V:
display_goto_xy(paramBase[2], paramBase[3]);
display_int(p0, paramBase[1]);
break;
case asyncRefresh_4_5V:
display_update();
break;
case clear_4_5V:
display_clear(0);
break;
case getDisplay_4_5_1B:
push_word(display_get_array());
break;
case setAutoRefreshPeriod_4I_5I:
push_word(display_set_auto_update_period(p0));
break;
case getRefreshCompleteTime_4_5I:
push_word(display_get_update_complete_time());
break;
case bitBlt_4_1BIIII_1BIIIIIII_5V:
{
Object *src = word2ptr(p0);
Object *dst = word2ptr(paramBase[5]);
display_bitblt((byte *)(src != NULL ?jbyte_array(src):NULL), paramBase[1], paramBase[2], paramBase[3], paramBase[4], (byte *)(dst!=NULL?jbyte_array(dst):NULL), paramBase[6], paramBase[7], paramBase[8], paramBase[9], paramBase[10], paramBase[11], paramBase[12]);
break;
}
case getSystemFont_4_5_1B:
push_word(display_get_font());
break;
case setContrast_4I_5V:
nxt_lcd_set_pot(p0);
break;
case getBatteryStatus_4_5I:
push_word(battery_voltage());
break;
case getButtons_4_5I:
push_word(buttons_get());
break;
case getTachoCountById_4I_5I:
push_word(nxt_motor_get_count(p0));
break;
case controlMotorById_4III_5V:
nxt_motor_set_speed(p0, paramBase[1], paramBase[2]);
break;
case resetTachoCountById_4I_5V:
nxt_motor_set_count(p0, 0);
break;
case i2cEnableById_4II_5V:
if (i2c_enable(p0, paramBase[1]) == 0)
return EXEC_RETRY;
else
break;
case i2cDisableById_4I_5V:
i2c_disable(p0);
break;
case i2cStatusById_4I_5I:
push_word(i2c_status(p0));
break;
case i2cStartById_4II_1BIII_5I:
{
Object *p = word2obj(paramBase[2]);
JBYTE *byteArray = p ? jbyte_array(p) + paramBase[3] : NULL;
push_word(i2c_start(p0,
paramBase[1],
(U8 *)byteArray,
paramBase[4],
paramBase[5]));
}
break;
case i2cCompleteById_4I_1BII_5I:
{
Object *p = word2ptr(paramBase[1]);
JBYTE *byteArray = p ? jbyte_array(p) + paramBase[2] : NULL;
push_word(i2c_complete(p0,
(U8 *)byteArray,
paramBase[3]));
}
break;
case playFreq_4III_5V:
sound_freq(p0,paramBase[1], paramBase[2]);
break;
case btGetBC4CmdMode_4_5I:
push_word(bt_get_mode());
break;
case btSetArmCmdMode_4I_5V:
if (p0 == 0) bt_set_arm7_cmd();
else bt_clear_arm7_cmd();
break;
case btSetResetLow_4_5V:
bt_set_reset_low();
break;
case btSetResetHigh_4_5V:
bt_set_reset_high();
break;
case btWrite_4_1BII_5I:
{
Object *p = word2ptr(p0);
byte *byteArray = (byte *) jbyte_array(p);
push_word(bt_write(byteArray, paramBase[1], paramBase[2]));
}
break;
case btRead_4_1BII_5I:
{
Object *p = word2ptr(p0);
byte *byteArray = (byte *) jbyte_array(p);
push_word(bt_read(byteArray, paramBase[1], paramBase[2]));
}
break;
case btPending_4_5I:
{
push_word(bt_event_check(0xffffffff));
}
break;
case btEnable_4_5V:
if (bt_enable() == 0)
return EXEC_RETRY;
else
break;
case btDisable_4_5V:
bt_disable();
break;
case usbRead_4_1BII_5I:
{
Object *p = word2ptr(p0);
byte *byteArray = (byte *) jbyte_array(p);
push_word(udp_read(byteArray,paramBase[1], paramBase[2]));
}
break;
case usbWrite_4_1BII_5I:
{
Object *p = word2ptr(p0);
byte *byteArray = (byte *) jbyte_array(p);
push_word(udp_write(byteArray,paramBase[1], paramBase[2]));
}
break;
case usbStatus_4_5I:
{
push_word(udp_event_check(0xffffffff));
}
break;
case usbEnable_4I_5V:
{
udp_enable(p0);
}
break;
case usbDisable_4_5V:
{
udp_disable();
}
break;
case usbReset_4_5V:
udp_reset();
break;
case usbSetSerialNo_4Ljava_3lang_3String_2_5V:
{
byte *p = word2ptr(p0);
int len;
Object *charArray = (Object *) word2ptr(get_word_4_ns(fields_start(p)));
len = get_array_length(charArray);
udp_set_serialno((U8 *)jchar_array(charArray), len);
}
break;
case usbSetName_4Ljava_3lang_3String_2_5V:
{
byte *p = word2ptr(p0);
int len;
Object *charArray = (Object *) word2ptr(get_word_4_ns(fields_start(p)));
len = get_array_length(charArray);
udp_set_name((U8 *)jchar_array(charArray), len);
}
break;
case flashWritePage_4_1BI_5I:
{
Object *p = word2ptr(p0);
unsigned long *intArray = (unsigned long *) jint_array(p);
push_word(flash_write_page(intArray,paramBase[1]));
}
break;
case flashReadPage_4_1BI_5I:
{
Object *p = word2ptr(p0);
unsigned long *intArray = (unsigned long *) jint_array(p);
push_word(flash_read_page(intArray,paramBase[1]));
}
break;
case flashExec_4II_5I:
push_word(run_program((byte *)(&FLASH_BASE[(p0*FLASH_PAGE_SIZE)]), paramBase[1]));
break;
case playSample_4IIIII_5V:
sound_play_sample(((unsigned char *) &FLASH_BASE[(p0*FLASH_PAGE_SIZE)]) + paramBase[1],paramBase[2],paramBase[3],paramBase[4]);
break;
case playQueuedSample_4_1BIIII_5I:
push_word(sound_add_sample((U8 *)jbyte_array(word2obj(p0)) + paramBase[1],paramBase[2],paramBase[3],paramBase[4]));
break;
case getTime_4_5I:
push_word(sound_get_time());
break;
case getDataAddress_4Ljava_3lang_3Object_2_5I:
if (is_array(word2obj(p0)))
push_word (ptr2word ((byte *) array_start(word2ptr(p0))));
else
push_word (ptr2word ((byte *) fields_start(word2ptr(p0))));
break;
case getObjectAddress_4Ljava_3lang_3Object_2_5I:
push_word(p0);
break;
case gc_4_5V:
// Restartable garbage collection
return garbage_collect();
case shutDown_4_5V:
shutdown(); // does not return
case boot_4_5V:
display_clear(1);
while (1) nxt_avr_firmware_update_mode(); // does not return
case arraycopy_4Ljava_3lang_3Object_2ILjava_3lang_3Object_2II_5V:
return arraycopy(word2ptr(p0), paramBase[1], word2ptr(paramBase[2]), paramBase[3], paramBase[4]);
case executeProgram_4I_5V:
// Exceute program, allow for instruction re-start
return execute_program(p0);
case setDebug_4_5V:
set_debug(word2ptr(p0));
break;
case eventOptions_4II_5I:
{
byte old = debugEventOptions[p0];
debugEventOptions[p0] = (byte)paramBase[1];
push_word(old);
}
break;
case suspendThread_4Ljava_3lang_3Object_2_5V:
suspend_thread(ref2ptr(p0));
break;
case resumeThread_4Ljava_3lang_3Object_2_5V:
resume_thread(ref2ptr(p0));
break;
case getProgramExecutionsCount_4_5I:
push_word(gProgramExecutions);
break;
case getFirmwareRevision_4_5I:
push_word((STACKWORD) getRevision());
break;
case getFirmwareRawVersion_4_5I:
push_word((STACKWORD) VERSION_NUMBER);
break;
case hsEnable_4II_5V:
{
if (hs_enable((int)p0, (int)paramBase[1]) == 0)
return EXEC_RETRY;
}
break;
case hsDisable_4_5V:
{
hs_disable();
}
break;
case hsWrite_4_1BII_5I:
{
Object *p = word2ptr(p0);
byte *byteArray = (byte *) jbyte_array(p);
push_word(hs_write(byteArray, paramBase[1], paramBase[2]));
}
break;
case hsRead_4_1BII_5I:
{
Object *p = word2ptr(p0);
byte *byteArray = (byte *) jbyte_array(p);
push_word(hs_read(byteArray, paramBase[1], paramBase[2]));
}
break;
case hsPending_4_5I:
{
push_word(hs_pending());
}
break;
case hsSend_4BB_1BII_1C_5I:
{
Object *p = word2ptr(paramBase[2]);
U8 *data = (U8 *)jbyte_array(p);
p = word2ptr(paramBase[5]);
U16 *crc = (U16 *)jchar_array(p);
push_word(hs_send((U8) p0, (U8)paramBase[1], data, paramBase[3], paramBase[4], crc));
}
break;
case hsRecv_4_1BI_1CI_5I:
{
Object *p = word2ptr(p0);
U8 *data = (U8 *)jbyte_array(p);
p = word2ptr(paramBase[2]);
U16 *crc = (U16 *)jchar_array(p);
push_word(hs_recv(data, paramBase[1], crc, paramBase[3]));
}
break;
case getUserPages_4_5I:
push_word(FLASH_MAX_PAGES - flash_start_page);
break;
case setVMOptions_4I_5V:
gVMOptions = p0;
break;
case getVMOptions_4_5I:
push_word(gVMOptions);
break;
case isAssignable_4II_5Z:
push_word(is_assignable(p0, paramBase[1]));
break;
case cloneObject_4Ljava_3lang_3Object_2_5Ljava_3lang_3Object_2:
{
Object *newObj = clone((Object *)ref2obj(p0));
if (newObj == NULL) return EXEC_RETRY;
push_word(obj2ref(newObj));
}
break;
case memPeek_4III_5I:
push_word(mem_peek(p0, paramBase[1], paramBase[2]));
break;
case memCopy_4Ljava_3lang_3Object_2IIII_5V:
mem_copy(word2ptr(p0), paramBase[1], paramBase[2], paramBase[3], paramBase[4]);
break;
case memGetReference_4II_5Ljava_3lang_3Object_2:
push_word(mem_get_reference(p0, paramBase[1]));
break;
case setSensorPin_4III_5V:
sp_set(p0, paramBase[1], paramBase[2]);
break;
case getSensorPin_4II_5I:
push_word(sp_get(p0, paramBase[1]));
break;
case setSensorPinMode_4III_5V:
sp_set_mode(p0, paramBase[1], paramBase[2]);
break;
case readSensorPin_4II_5I:
push_word(sp_read(p0, paramBase[1]));
break;
case nanoTime_4_5J:
{
U64 ns = systick_get_ns();
push_word(ns >> 32);
push_word(ns);
}
break;
case createStackTrace_4Ljava_3lang_3Thread_2Ljava_3lang_3Object_2_5_1I:
{
Object *trace = create_stack_trace((Thread *)ref2obj(p0), ref2obj(paramBase[1]));
if (trace == NULL) return EXEC_RETRY;
push_word(obj2ref(trace));
}
break;
case registerEvent_4_5I:
push_word(register_event((NXTEvent *) ref2obj(p0)));
break;
case unregisterEvent_4_5I:
push_word(unregister_event((NXTEvent *) ref2obj(p0)));
break;
case changeEvent_4II_5I:
push_word(change_event((NXTEvent *) ref2obj(p0), paramBase[1], paramBase[2]));
break;
case isInitialized_4I_5Z:
push_word(is_initialized_idx(p0));
break;
case allocate_4II_5Ljava_3lang_3Object_2:
{
Object *allocated;
if(paramBase[1]>0){
allocated=new_single_array(p0,paramBase[1]);
}else{
allocated=new_object_for_class(p0);
}
if(allocated == NULL) return EXEC_RETRY;
push_word(obj2ref(allocated));
}
break;
case memPut_4IIII_5V:
store_word_ns((byte *)(memory_base[p0] + paramBase[1]), paramBase[2],paramBase[3]);
break;
case notifyEvent_4ILjava_3lang_3Thread_2_5Z:
push_word(debug_event(paramBase[1], NULL, (Thread*) ref2obj(paramBase[2]), 0, 0, 0, 0));
break;
case setThreadRequest_4Ljava_3lang_3Thread_2Llejos_3nxt_3debug_3SteppingRequest_2_5V:
{
Thread *th = (Thread*) ref2obj(p0);
th->debugData = (REFERENCE) paramBase[1];
// currently we only get stepping requests
if(paramBase[1])
th->flags |= THREAD_STEPPING;
else
th->flags &= ~THREAD_STEPPING;
}
break;
case isStepping_4Ljava_3lang_3Thread_2_5Z:
{
Thread *th = (Thread*) ref2obj(p0);
push_word(is_stepping(th));
}
break;
case setBreakpointList_4_1Llejos_3nxt_3debug_3Breakpoint_2I_5V:
breakpoint_set_list((Breakpoint**) array_start(p0), paramBase[1]);
break;
case enableBreakpoint_4Llejos_3nxt_3debug_3Breakpoint_2Z_5V:
breakpoint_enable((Breakpoint*) word2ptr(p0), (boolean) paramBase[1]);
break;
case firmwareExceptionHandler_4Ljava_3lang_3Throwable_2II_5V:
firmware_exception_handler((Throwable *)p0, paramBase[1], paramBase[2]);
break;
case exitThread_4_5V:
currentThread->state = DEAD;
schedule_request(REQUEST_SWITCH_THREAD);
break;
case updateThreadFlags_4Ljava_3lang_3Thread_2II_5I:
((Thread *)p0)->flags |= paramBase[1];
((Thread *)p0)->flags &= ~paramBase[2];
//printf("m %x %d\n", p0, ((Thread *)p0)->flags);
push_word(((Thread *)p0)->flags);
break;
default:
return throw_new_exception(JAVA_LANG_NOSUCHMETHODERROR);
}
return EXEC_CONTINUE;
}
static inline void i2c_wait_RDRF(i2c_t *obj) {
while (!(i2c_status(obj) & (1 << 5))) ;
}
