extern "C" void Reset_Handler()
{
/* 4 bits for preemption priority */
NVIC_SetPriorityGrouping(4);
/* enable data/instruction cache, set wait cycles, set flash latency */
FLASH->ACR |= FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN | FLASH_ACR_LATENCY_5WS;
assert(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) == FLASH_ACR_LATENCY_5WS);
/* enable FPU if needed */
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
/* enable coprocessors CP10 and CP11 */
SCB->CPACR |= (0x0f << 20);
#endif
clock_init();
/* data initialization */
memcpy(&__data_start__, &__etext, (intptr_t)&__data_end__ - (intptr_t)&__data_start__);
memcpy(&__data2_start__, &__etext2, (intptr_t)&__data2_end__ - (intptr_t)&__data2_start__);
memset(&__bss_start__, 0, (intptr_t)&__bss_end__ - (intptr_t)&__bss_start__);
memset(&__bss2_start__, 0, (intptr_t)&__bss2_end__ - (intptr_t)&__bss2_start__);
/* set interrupt vector table offset */
SCB->VTOR = (uint32_t)&interruptVectorTable;
/* c++ constructors */
__libc_init_array();
gpio_init();
i2s_init();
main();
}
void audio_on() {
audio_off(); //Turn off to make sure we do a proper reset
delay(1000000);
i2s_init(SPARROW_I2S);
write_pin(AUDIO_POWER_EN_PIN, true);
delay(1000000); //TLV320AIC3100 spec: Reset low for at least 10ns
write_pin(AUDIO_NRESET, true);
delay(1000000); //TLV320AIC3100 spec: 1ms min after reset
}
int am_device_init(aud_dev_info* devinfo, void *dev_fmt, void *strm_fmt)
{
am_stream_format_info *sfmt = (am_stream_format_info*)strm_fmt;
am_dev_format_info *dfmt = (am_dev_format_info*)dev_fmt;
if (devinfo->dev_type == AUDIO_I2S_DEVICE) {
struct tegra_i2s_property i2sprop;
memset(&i2sprop, 0, sizeof(i2sprop));
if (sfmt) {
i2sprop.bit_size = sfmt->bitsize;
i2sprop.sample_rate = sfmt->samplerate;
}
if (dfmt) {
i2sprop.master_mode = dfmt->mastermode;
i2sprop.audio_mode = dfmt->audiomode;
i2sprop.clk_rate = dfmt->clkrate;
i2sprop.fifo_fmt = dfmt->fifofmt;
i2sprop.total_slots = dfmt->total_slots;
i2sprop.fsync_width = dfmt->fsync_width;
i2sprop.rx_slot_enables = dfmt->rx_slot_enables;
i2sprop.tx_slot_enables = dfmt->tx_slot_enables;
i2sprop.rx_bit_offset = dfmt->rx_bit_offset;
i2sprop.tx_bit_offset = dfmt->tx_bit_offset;
i2sprop.tdm_bitsize = dfmt->tdm_bitsize;
}
return i2s_init(devinfo->dev_id, &i2sprop);
} else if (devinfo->dev_type == AUDIO_SPDIF_DEVICE) {
struct tegra_spdif_property spdifprop;
memset(&spdifprop, 0, sizeof(spdifprop));
if (sfmt) {
spdifprop.bit_size = sfmt->bitsize;
spdifprop.sample_rate = sfmt->samplerate;
spdifprop.channels = sfmt->channels;
}
if (dfmt) {
spdifprop.clk_rate = dfmt->clkrate;
}
return spdif_init(
devinfo->base,
devinfo->phy_base,
devinfo->fifo_mode,
&spdifprop);
}
return 0;
}
uint32_t c_ICS43432::init(int32_t fsamp, int32_t *buffer, uint32_t nbuf)
{
i2s_init();
float fs = i2s_speedConfig(ICS43432_DEV,N_BITS, fsamp);
if(fs<1.0f) return 0;
i2s_config(1, N_BITS, I2S_RX_2CH, 0);
i2s_configurePorts(2);
DMA_init();
i2s_setupInput(buffer,nbuf,2,5); //port, prio (8=normal)
return (uint32_t) fs;
}
int am_device_init(aud_dev_info* devinfo, void *dev_fmt, void *strm_fmt)
{
am_stream_format_info *sfmt = (am_stream_format_info*)strm_fmt;
am_dev_format_info *dfmt = (am_dev_format_info*)dev_fmt;
AM_DEBUG_PRINT("%s++\n", __func__);
if (devinfo->dev_type == AUDIO_I2S_DEVICE) {
struct tegra_i2s_property i2sprop;
memset(&i2sprop, 0, sizeof(i2sprop));
if (sfmt) {
i2sprop.bit_size = sfmt->bitsize;
i2sprop.sample_rate = sfmt->samplerate;
}
if (dfmt) {
i2sprop.master_mode = dfmt->mastermode;
i2sprop.audio_mode = dfmt->audiomode;
i2sprop.clk_rate = dfmt->clkrate;
i2sprop.fifo_fmt = dfmt->fifofmt;
}
return i2s_init(devinfo->dev_id, &i2sprop);
} else if (devinfo->dev_type == AUDIO_SPDIF_DEVICE) {
struct tegra_spdif_property spdifprop;
memset(&spdifprop, 0, sizeof(spdifprop));
if (sfmt) {
spdifprop.bit_size = sfmt->bitsize;
spdifprop.sample_rate = sfmt->samplerate;
spdifprop.channels = sfmt->channels;
}
if (dfmt) {
spdifprop.clk_rate = dfmt->clkrate;
}
return spdif_init(
devinfo->base,
devinfo->phy_base,
devinfo->fifo_mode,
&spdifprop);
}
return 0;
}
static int i2s_send(I2sOps *me, uint32_t *data, unsigned int length)
{
Exynos5I2s *bus = container_of(me, Exynos5I2s, ops);
Exynos5I2sRegs *regs = bus->regs;
if (!bus->initialized) {
if (i2s_init(bus))
return -1;
else
bus->initialized = 1;
}
i2s_send_generic(data, length, ®s->tx_data, ®s->control);
return 0;
}
//! [setup]
static void _configure_i2s(void)
{
//! [setup_i2s_init]
i2s_init(&i2s_instance, CONF_I2S_MODULE);
//! [setup_i2s_init]
//! [setup_clock_unit_config]
struct i2s_clock_unit_config config_clock_unit;
//! [setup_clock_unit_config]
//! [setup_clock_unit_config_defaults]
i2s_clock_unit_get_config_defaults(&config_clock_unit);
//! [setup_clock_unit_config_defaults]
//! [setup_clock_unit_change_config]
config_clock_unit.clock.gclk_src = GCLK_GENERATOR_0;
config_clock_unit.clock.mck_src = I2S_MASTER_CLOCK_SOURCE_GCLK;
config_clock_unit.clock.mck_out_enable = true;
config_clock_unit.clock.mck_out_div = 2;
config_clock_unit.clock.sck_src = I2S_SERIAL_CLOCK_SOURCE_MCKDIV;
config_clock_unit.clock.sck_div = 4;
config_clock_unit.frame.number_slots = 2;
config_clock_unit.frame.slot_size = I2S_SLOT_SIZE_32_BIT;
config_clock_unit.frame.data_delay = I2S_DATA_DELAY_0;
config_clock_unit.frame.frame_sync.source = I2S_FRAME_SYNC_SOURCE_SCKDIV;
config_clock_unit.frame.frame_sync.width = I2S_FRAME_SYNC_WIDTH_HALF_FRAME;
//! [setup_clock_unit_change_config]
//! [setup_clock_unit_change_pins]
config_clock_unit.mck_pin.enable = true;
config_clock_unit.mck_pin.gpio = CONF_I2S_MCK_PIN;
config_clock_unit.mck_pin.mux = CONF_I2S_MCK_MUX;
config_clock_unit.sck_pin.enable = true;
config_clock_unit.sck_pin.gpio = CONF_I2S_SCK_PIN;
config_clock_unit.sck_pin.mux = CONF_I2S_SCK_MUX;
config_clock_unit.fs_pin.enable = true;
config_clock_unit.fs_pin.gpio = CONF_I2S_FS_PIN;
config_clock_unit.fs_pin.mux = CONF_I2S_FS_MUX;
//! [setup_clock_unit_change_pins]
//! [setup_clock_unit_set_config]
i2s_clock_unit_set_config(&i2s_instance, I2S_CLOCK_UNIT_0,
&config_clock_unit);
//! [setup_clock_unit_set_config]
//! [setup_serializer_config]
struct i2s_serializer_config config_serializer;
//! [setup_serializer_config]
//! [setup_serializer_config_defaults]
i2s_serializer_get_config_defaults(&config_serializer);
//! [setup_serializer_config_defaults]
//! [setup_serializer_change_config_tx]
config_serializer.clock_unit = I2S_CLOCK_UNIT_0;
config_serializer.mode = I2S_SERIALIZER_TRANSMIT;
config_serializer.data_size = I2S_DATA_SIZE_16BIT;
//! [setup_serializer_change_config_tx]
//! [setup_serializer_change_config_pin_tx]
config_serializer.data_pin.enable = true;
config_serializer.data_pin.gpio = CONF_I2S_SD_PIN;
config_serializer.data_pin.mux = CONF_I2S_SD_MUX;
//! [setup_serializer_change_config_pin_tx]
//! [setup_serializer_set_config_tx]
i2s_serializer_set_config(&i2s_instance, I2S_SERIALIZER_0,
&config_serializer);
//! [setup_serializer_set_config_tx]
//! [setup_enable]
i2s_enable(&i2s_instance);
i2s_clock_unit_enable(&i2s_instance, I2S_CLOCK_UNIT_0);
i2s_serializer_enable(&i2s_instance, I2S_SERIALIZER_0);
//! [setup_enable]
}
int main(void)
{
uint16_t i;
char temp_char;
uint8_t num_chars_ret;
// For CS4272 (uC i2s interface in slave mode) not sure about
// initialization sequence (i2s interface first, or setup cs4272 first)
// For now, start with codec (get interface clocks started first)
// Initialize USB
usb_init();
delay(100);
// Initialize I2C subsystem
i2c_init();
delay(100);
for(i = 0; i < 64; i++)
{
buffer[i] = 0;
}
// Wait to setup codec to make sure user has turned on audio board power
while((buffer[0] != 'y') && (buffer[0] != 'Y'))
{
serial_write_string("Init codec? (y/n)\r\n>");
// Wait for response
num_chars_ret = serial_read_line(buffer,64);
if(num_chars_ret < 1)
{
serial_write_string("Error reading line. Please try again.\r\n");
}
}
for(i = 0; i < 64; i++)
{
buffer[i] = 0;
}
// Initialize CS4272
codec_init();
delay(100);
// Initialize I2S subsystem
i2s_init();
delay(10);
serial_write_string("Codec Initialized\r\n");
delay(10);
// Test to see if i2c is working
uint8_t reg_result;
uint8_t ii;
for(ii = 1; ii < 9; ii++)
{
itoa(ii,buffer,10);
serial_write_string("Address ");
serial_write_string(buffer);
serial_write_string(": ");
reg_result = codec_read(ii);
itoa(reg_result,buffer,10);
serial_write_string(buffer);
serial_write_string("\r\n");
delay(100);
}
for(i = 0; i < 64; i++)
{
buffer[i] = 0;
}
serial_write_string("Waiting 10 seconds for ADC high pass filter to stabilize\r\n");
delay(10000);
while(1)
{
// Initialize indices, etc
tx_buf_idx = 0;
rx_buf_idx = 0;
curr_run = 0;
for(i = 0; i < NUM_SAMP; i++)
{
//recv_data_real[i] = 0;
//recv_data_imag[i] = 0;
recv_data_right[i] = 0;
//recv_data_left[i] = 0;
}
for(i = 0; i < 64; i++)
{
buffer[i] = 0;
}
while((buffer[0] != 'y') && (buffer[0] != 'Y'))
{
serial_write_string("Start test? (y/n)\r\n>");
// Wait for response
num_chars_ret = serial_read_line(buffer,64);
if(num_chars_ret < 1)
{
serial_write_string("Error reading line. Please try again.\r\n");
}
}
// Start test
serial_write_string("Starting test.\r\n");
//output_real_part = 1;
test_running = 1;
i2s_start();
// Wait for real part to finish
while(test_running)
{
//serial_write_string("Running real part. Please wait .....\r\n");
delay(1000);
}
// Test is now finished
// serial_write_string("Real part is finished. Starting imaginary part.\r\n");
//
// delay(1000);
//
// // Start imaginary part
// output_real_part = 0;
// test_running = 1;
// i2s_start();
//
// // Wait for real part to finish
// while(test_running)
// {
// //serial_write_string("Running imaginary part. Please wait .....\r\n");
// delay(1000);
// }
//
// // Test is now finished
// serial_write_string("Imaginary part is finished. Printing Data.\r\n");
// Print data
for(i = 0; i < NUM_SAMP; i++)
{
itoa(recv_data_right[i],buffer,10);
serial_write_string(buffer);
serial_write_string(",");
itoa(recv_data_left[i],buffer,10);
serial_write_string(buffer);
serial_write_string("\r\n");
delay(50);
}
serial_write_string("End of data.\r\n");
}
return 0;
}
/**
* \brief Test audio data transfer and receive.
*
* \param test Current test case.
*/
static void run_i2s_test(const struct test_case *test)
{
uint32_t i;
struct i2s_config config;
struct i2s_dev_inst dev_inst;
Pdc *p_i2sc_pdc;
Pdc *p_i2sc_pdc2;
pdc_packet_t pdc_i2sc_packet_tx, pdc_i2sc_packet_rx;
pdc_packet_t pdc2_i2sc_packet_tx, pdc2_i2sc_packet_rx;
/* Set the configuration */
i2s_get_config_defaults(&config);
config.data_format = I2S_DATE_16BIT;
config.fs_ratio = I2S_FS_RATE_256;
config.loopback = true;
i2s_init(&dev_inst, I2SC0, &config);
/* Enable the I2SC module. */
i2s_enable(&dev_inst);
/* Get pointer to I2SC PDC register base */
p_i2sc_pdc = i2s_get_pdc_base(&dev_inst);
p_i2sc_pdc2 = (Pdc *)((uint32_t)p_i2sc_pdc + 0x100U);
/* Initialize PDC data packet for transfer */
pdc_i2sc_packet_tx.ul_addr = (uint32_t) output_samples_left;
pdc_i2sc_packet_tx.ul_size = SOUND_SAMPLES;
pdc_i2sc_packet_rx.ul_addr = (uint32_t) input_samples_left;
pdc_i2sc_packet_rx.ul_size = SOUND_SAMPLES;
pdc2_i2sc_packet_tx.ul_addr = (uint32_t) output_samples_right;
pdc2_i2sc_packet_tx.ul_size = SOUND_SAMPLES;
pdc2_i2sc_packet_rx.ul_addr = (uint32_t) input_samples_right;
pdc2_i2sc_packet_rx.ul_size = SOUND_SAMPLES;
/* Configure PDC for data transfer */
pdc_tx_init(p_i2sc_pdc, &pdc_i2sc_packet_tx, NULL);
pdc_rx_init(p_i2sc_pdc, &pdc_i2sc_packet_rx, NULL);
pdc_tx_init(p_i2sc_pdc2, &pdc2_i2sc_packet_tx, NULL);
pdc_rx_init(p_i2sc_pdc2, &pdc2_i2sc_packet_rx, NULL);
/* Enable PDC transfers */
pdc_enable_transfer(p_i2sc_pdc, PERIPH_PTCR_TXTEN | PERIPH_PTCR_RXTEN);
pdc_enable_transfer(p_i2sc_pdc2, PERIPH_PTCR_TXTEN | PERIPH_PTCR_RXTEN);
/* Enable the functions */
i2s_enable_transmission(&dev_inst);
i2s_enable_clocks(&dev_inst);
/**
* Since the transfer and receive timing is not under control, we
* need adjust here the enable sequence and add some delay
* functions if it's needed.
*/
for (i = 0; i < 0x8; i++) {
input_samples_left[i] = i;
}
i2s_enable_reception(&dev_inst);
/* Wait transfer complete */
while (!(i2s_get_status(&dev_inst) & I2SC_SR_RXBUFF)) {
}
/**
* Wait a moment to let the PDC finish. The status bit is cleared
* before all transfer finish.
*/
delay_us(10);
/* Disable the PDC module. */
pdc_disable_transfer(p_i2sc_pdc, PERIPH_PTCR_RXTDIS| PERIPH_PTCR_TXTDIS);
pdc_disable_transfer(p_i2sc_pdc2, PERIPH_PTCR_RXTDIS| PERIPH_PTCR_TXTDIS);
/* Disable the I2SC module. */
i2s_disable(&dev_inst);
/* Compare the data. */
for (i = 0; i < SOUND_SAMPLES; i++) {
if ((input_samples_left[i] != output_samples_left[i]) ||
(input_samples_right[i] != output_samples_right[i])) {
flag = false;
}
}
test_assert_true(test, flag == true, "Audio data did not match!");
}
