static void
tprof_amdpmi_start_cpu(void *arg1, void *arg2)
{
struct cpu_info * const ci = curcpu();
uint64_t pesr;
uint64_t event_lo;
uint64_t event_hi;
event_hi = event >> 8;
event_lo = event & 0xff;
pesr = PESR_USR | PESR_OS | PESR_INT |
__SHIFTIN(event_lo, PESR_EVENT_MASK_LO) |
__SHIFTIN(event_hi, PESR_EVENT_MASK_HI) |
__SHIFTIN(0, PESR_COUNTER_MASK) |
__SHIFTIN(unit, PESR_UNIT_MASK);
wrmsr(PERFCTR(ctrno), counter_reset_val);
wrmsr(PERFEVTSEL(ctrno), pesr);
tprof_amdpmi_lapic_saved[cpu_index(ci)] = i82489_readreg(LAPIC_PCINT);
i82489_writereg(LAPIC_PCINT, LAPIC_DLMODE_NMI);
wrmsr(PERFEVTSEL(ctrno), pesr | PESR_EN);
}
static __inline u_int32_t
lapic_gettick(void)
{
return i82489_readreg(LAPIC_CCR_TIMER);
}
void
lapic_set_lvt(void)
{
struct cpu_info *ci = curcpu();
int i;
struct mp_intr_map *mpi;
#ifdef MULTIPROCESSOR
if (mp_verbose) {
apic_format_redir(ci->ci_dev.dv_xname, "prelint", 0, 0,
i82489_readreg(LAPIC_LVINT0));
apic_format_redir(ci->ci_dev.dv_xname, "prelint", 1, 0,
i82489_readreg(LAPIC_LVINT1));
}
#endif
if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
/*
* Detect the presence of C1E capability mostly on latest
* dual-cores (or future) k8 family. This mis-feature renders
* the local APIC timer dead, so we disable it by reading
* the Interrupt Pending Message register and clearing both
* C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
*
* Reference:
* "BIOS and Kernel Developer's Guide for AMD NPT
* Family 0Fh Processors"
* #32559 revision 3.00
*/
if ((cpu_id & 0x00000f00) == 0x00000f00 &&
(cpu_id & 0x0fff0000) >= 0x00040000) {
uint64_t msr;
msr = rdmsr(MSR_INT_PEN_MSG);
if (msr & (IPM_C1E_CMP_HLT|IPM_SMI_CMP_HLT)) {
msr &= ~(IPM_C1E_CMP_HLT|IPM_SMI_CMP_HLT);
wrmsr(MSR_INT_PEN_MSG, msr);
}
}
}
for (i = 0; i < mp_nintrs; i++) {
mpi = &mp_intrs[i];
if (mpi->ioapic == NULL && (mpi->cpu_id == MPS_ALL_APICS
|| mpi->cpu_id == ci->ci_apicid)) {
#ifdef DIAGNOSTIC
if (mpi->ioapic_pin > 1)
panic("lapic_set_lvt: bad pin value %d",
mpi->ioapic_pin);
#endif
if (mpi->ioapic_pin == 0)
i82489_writereg(LAPIC_LVINT0, mpi->redir);
else
i82489_writereg(LAPIC_LVINT1, mpi->redir);
}
}
#ifdef MULTIPROCESSOR
if (mp_verbose) {
apic_format_redir(ci->ci_dev.dv_xname, "timer", 0, 0,
i82489_readreg(LAPIC_LVTT));
apic_format_redir(ci->ci_dev.dv_xname, "pcint", 0, 0,
i82489_readreg(LAPIC_PCINT));
apic_format_redir(ci->ci_dev.dv_xname, "lint", 0, 0,
i82489_readreg(LAPIC_LVINT0));
apic_format_redir(ci->ci_dev.dv_xname, "lint", 1, 0,
i82489_readreg(LAPIC_LVINT1));
apic_format_redir(ci->ci_dev.dv_xname, "err", 0, 0,
i82489_readreg(LAPIC_LVERR));
}
#endif
}
