void * asmlinkage romstage_main(unsigned long bist) { int cbmem_was_initted; /* init_timer(); */ post_code(0x05); i82801ix_early_init(); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); cbmem_was_initted = !cbmem_recovery(0); timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); /* Emulation uses fixed low stack during ramstage. */ return NULL; }
void main(unsigned long bist) { int cbmem_was_initted; /* init_timer(); */ post_code(0x05); i82801ix_early_init(); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); //print_pci_devices(); //dump_pci_devices(); cbmem_was_initted = !cbmem_initialize(); timestamp_init(rdtsc()); timestamp_add_now(TS_START_ROMSTAGE); }
/* Platform has no romstage entry point under mainboard directory, * so this one is named with prefix mainboard. */ void mainboard_romstage_entry(unsigned long bist) { sysinfo_t sysinfo; int s3resume = 0; int cbmem_initted; u16 reg16; /* basic northbridge setup, including MMCONF BAR */ gm45_early_init(); if (bist == 0) enable_lapic(); /* First, run everything needed for console output. */ i82801ix_early_init(); setup_pch_gpios(&mainboard_gpio_map); mb_setup_lpc(); mb_setup_superio(); console_init(); report_bist_failure(bist); reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3); pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16); if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); gm45_early_reset(); } /* ASPM related setting, set early by original BIOS. */ DMIBAR16(0x204) &= ~(3 << 10); /* Check for S3 resume. */ s3resume = southbridge_detect_s3_resume(); /* RAM initialization */ enter_raminit_or_reset(); memset(&sysinfo, 0, sizeof(sysinfo)); get_mb_spd_addrmap(sysinfo.spd_map); const struct device *dev; dev = pcidev_on_root(2, 0); if (dev) sysinfo.enable_igd = dev->enabled; dev = pcidev_on_root(1, 0); if (dev) sysinfo.enable_peg = dev->enabled; get_gmch_info(&sysinfo); mb_pre_raminit_setup(&sysinfo); raminit(&sysinfo, s3resume); mb_post_raminit_setup(); const u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN); /* Disable D4F0 (unknown signal controller). */ pci_write_config32(MCH_DEV, D0F0_DEVEN, deven & ~0x4000); init_pm(&sysinfo, 0); i82801ix_dmi_setup(); gm45_late_init(sysinfo.stepping); i82801ix_dmi_poll_vc1(); MCHBAR16(SSKPD_MCHBAR) = 0xCAFE; init_iommu(); cbmem_initted = !cbmem_recovery(s3resume); romstage_handoff_init(cbmem_initted && s3resume); printk(BIOS_SPEW, "exit main()\n"); }