Example #1
0
/* Check pitch constriants for all chips & tiling formats */
static bool
i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
{
    int tile_width;

    /* Linear is always fine */
    if (tiling_mode == I915_TILING_NONE)
        return true;

    if (!IS_I9XX(dev) ||
            (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
        tile_width = 128;
    else
        tile_width = 512;

    /* check maximum stride & object size */
    if (IS_I965G(dev)) {
        /* i965 stores the end address of the gtt mapping in the fence
         * reg, so dont bother to check the size */
        if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
            return false;
    } else if (IS_I9XX(dev)) {
        uint32_t pitch_val = ffs(stride / tile_width) - 1;

        /* XXX: For Y tiling, FENCE_MAX_PITCH_VAL is actually 6 (8KB)
         * instead of 4 (2KB) on 945s.
         */
        if (pitch_val > I915_FENCE_MAX_PITCH_VAL ||
                size > (I830_FENCE_MAX_SIZE_VAL << 20))
            return false;
    } else {
        uint32_t pitch_val = ffs(stride / tile_width) - 1;

        if (pitch_val > I830_FENCE_MAX_PITCH_VAL ||
                size > (I830_FENCE_MAX_SIZE_VAL << 19))
            return false;
    }

    /* 965+ just needs multiples of tile width */
    if (IS_I965G(dev)) {
        if (stride & (tile_width - 1))
            return false;
        return true;
    }

    /* Pre-965 needs power of two tile widths */
    if (stride < tile_width)
        return false;

    if (stride & (stride - 1))
        return false;

    /* We don't 0handle the aperture area covered by the fence being bigger
     * than the object size.
     */
    if (i915_get_fence_size(dev, size) != size)
        return false;

    return true;
}
Example #2
0
/* Check pitch constriants for all chips & tiling formats */
static int 
i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
{
	int tile_width;

	/* Linear is always fine */
	if (tiling_mode == I915_TILING_NONE)
		return 1;

	if (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
		tile_width = 128;
	else
		tile_width = 512;

	if (stride == 0)
		return 0;

	/* 965+ just needs multiples of tile width */
	if (IS_I965G(dev)) {
		if (stride & (tile_width - 1))
			return 0;
		return 1;
	}

	/* Pre-965 needs power of two tile widths */
	if (stride < tile_width)
		return 0;

	if (!ISP2(stride))
		return 0;

	/* We don't handle the aperture area covered by the fence being bigger
	 * than the object size.
	 */
	if (i915_get_fence_size(dev, size) != size)
		return 0;

	return 1;
}