int intel_ctx_workarounds_emit(struct i915_request *rq) { struct i915_workarounds *w = &rq->i915->workarounds; u32 *cs; int ret, i; if (w->count == 0) return 0; ret = rq->engine->emit_flush(rq, EMIT_BARRIER); if (ret) return ret; cs = intel_ring_begin(rq, (w->count * 2 + 2)); if (IS_ERR(cs)) return PTR_ERR(cs); *cs++ = MI_LOAD_REGISTER_IMM(w->count); for (i = 0; i < w->count; i++) { *cs++ = i915_mmio_reg_offset(w->reg[i].addr); *cs++ = w->reg[i].value; } *cs++ = MI_NOOP; intel_ring_advance(rq, cs); ret = rq->engine->emit_flush(rq, EMIT_BARRIER); if (ret) return ret; return 0; }
static struct whitelist *whitelist_build(struct intel_engine_cs *engine, struct whitelist *w) { struct drm_i915_private *i915 = engine->i915; GEM_BUG_ON(engine->id != RCS); w->count = 0; w->nopid = i915_mmio_reg_offset(RING_NOPID(engine->mmio_base)); if (INTEL_GEN(i915) < 8) return NULL; else if (IS_BROADWELL(i915)) bdw_whitelist_build(w); else if (IS_CHERRYVIEW(i915)) chv_whitelist_build(w); else if (IS_SKYLAKE(i915)) skl_whitelist_build(w); else if (IS_BROXTON(i915)) bxt_whitelist_build(w); else if (IS_KABYLAKE(i915)) kbl_whitelist_build(w); else if (IS_GEMINILAKE(i915)) glk_whitelist_build(w); else if (IS_COFFEELAKE(i915)) cfl_whitelist_build(w); else if (IS_CANNONLAKE(i915)) cnl_whitelist_build(w); else if (IS_ICELAKE(i915)) icl_whitelist_build(w); else MISSING_CASE(INTEL_GEN(i915)); return w; }
static int intel_shadow_table_check(void) { struct { const i915_reg_t *regs; unsigned int size; } reg_lists[] = { { gen8_shadowed_regs, ARRAY_SIZE(gen8_shadowed_regs) }, { gen11_shadowed_regs, ARRAY_SIZE(gen11_shadowed_regs) }, }; const i915_reg_t *reg; unsigned int i, j; s32 prev; for (j = 0; j < ARRAY_SIZE(reg_lists); ++j) { reg = reg_lists[j].regs; for (i = 0, prev = -1; i < reg_lists[j].size; i++, reg++) { u32 offset = i915_mmio_reg_offset(*reg); if (prev >= (s32)offset) { pr_err("%s: entry[%d]:(%x) is before previous (%x)\n", __func__, i, offset, prev); return -EINVAL; } prev = offset; } } return 0; }
static void guc_init_send_regs(struct intel_guc *guc) { struct drm_i915_private *dev_priv = guc_to_i915(guc); enum forcewake_domains fw_domains = 0; unsigned int i; guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0)); guc->send_regs.count = SOFT_SCRATCH_COUNT - 1; for (i = 0; i < guc->send_regs.count; i++) { fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, guc_send_reg(guc, i), FW_REG_READ | FW_REG_WRITE); } guc->send_regs.fw_domains = fw_domains; }
static void whitelist_apply(struct intel_engine_cs *engine, const struct whitelist *w) { struct drm_i915_private *dev_priv = engine->i915; const u32 base = engine->mmio_base; unsigned int i; if (!w) return; intel_uncore_forcewake_get(engine->i915, FORCEWAKE_ALL); for (i = 0; i < w->count; i++) I915_WRITE_FW(RING_FORCE_TO_NONPRIV(base, i), i915_mmio_reg_offset(w->reg[i])); /* And clear the rest just in case of garbage */ for (; i < RING_MAX_NONPRIV_SLOTS; i++) I915_WRITE_FW(RING_FORCE_TO_NONPRIV(base, i), w->nopid); intel_uncore_forcewake_put(engine->i915, FORCEWAKE_ALL); }