static void md_reset(MicroDriveState *s) { s->opt = OPT_MODE_MMAP; s->stat = 0; s->pins = 0; s->cycle = 0; s->ctrl = 0; ide_bus_reset(&s->bus); }
static void cmd646_reset(void *opaque) { PCIIDEState *d = opaque; unsigned int i; for (i = 0; i < 2; i++) { ide_bus_reset(&d->bus[i]); } }
static void md_reset(DeviceState *dev) { MicroDriveState *s = MICRODRIVE(dev); s->opt = OPT_MODE_MMAP; s->stat = 0; s->pins = 0; s->cycle = 0; s->ctrl = 0; ide_bus_reset(&s->bus); }
static void pc98_ide_reset(DeviceState *d) { PC98IDEState *s = container_of(d, PC98IDEState, dev.qdev); int i, j; for (i = 0; i < 2; i++) { ide_bus_reset(&s->bus[i]); for (j = 0; j < 2; j++) { s->bus[i].ifs[j].status = READY_STAT | SEEK_STAT; s->bus[i].ifs[j].error = 0x01; } s->bus[i].unit = 0; } s->cur_bus = &s->bus[0]; }
static void piix3_reset(void *opaque) { PCIIDEState *d = opaque; uint8_t *pci_conf = d->dev.config; int i; for (i = 0; i < 2; i++) { ide_bus_reset(&d->bus[i]); } /* TODO: this is the default. do not override. */ pci_conf[PCI_COMMAND] = 0x00; /* TODO: this is the default. do not override. */ pci_conf[PCI_COMMAND + 1] = 0x00; /* TODO: use pci_set_word */ pci_conf[PCI_STATUS] = PCI_STATUS_FAST_BACK; pci_conf[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8; pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */ }
static void via_reset(void *opaque) { PCIIDEState *d = opaque; PCIDevice *pd = PCI_DEVICE(d); uint8_t *pci_conf = pd->config; int i; for (i = 0; i < 2; i++) { ide_bus_reset(&d->bus[i]); } pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_WAIT); pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, 0x000001f0); pci_set_long(pci_conf + PCI_BASE_ADDRESS_1, 0x000003f4); pci_set_long(pci_conf + PCI_BASE_ADDRESS_2, 0x00000170); pci_set_long(pci_conf + PCI_BASE_ADDRESS_3, 0x00000374); pci_set_long(pci_conf + PCI_BASE_ADDRESS_4, 0x0000cc01); /* BMIBA: 20-23h */ pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e); /* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/ pci_set_long(pci_conf + 0x40, 0x0a090600); /* IDE misc configuration 1/2/3 */ pci_set_long(pci_conf + 0x44, 0x00c00068); /* IDE Timing control */ pci_set_long(pci_conf + 0x48, 0xa8a8a8a8); /* IDE Address Setup Time */ pci_set_long(pci_conf + 0x4c, 0x000000ff); /* UltraDMA Extended Timing Control*/ pci_set_long(pci_conf + 0x50, 0x07070707); /* UltraDMA FIFO Control */ pci_set_long(pci_conf + 0x54, 0x00000004); /* IDE primary sector size */ pci_set_long(pci_conf + 0x60, 0x00000200); /* IDE secondary sector size */ pci_set_long(pci_conf + 0x68, 0x00000200); /* PCI PM Block */ pci_set_long(pci_conf + 0xc0, 0x00020001); }
static void mmio_ide_reset(DeviceState *dev) { MMIOState *s = MMIO_IDE(dev); ide_bus_reset(&s->bus); }
static void mmio_ide_reset(void *opaque) { MMIOState *s = opaque; ide_bus_reset(&s->bus); }