/* there are stored pio numbers from other calls of opti621_tune_drive */
static void compute_pios(ide_drive_t *drive, u8 pio)
/* Store values into drive->drive_data
* second_contr - 0 for primary controller, 1 for secondary
* slave_drive - 0 -> pio is for master, 1 -> pio is for slave
* pio - PIO mode for selected drive (for other we don't know)
*/
{
int d;
ide_hwif_t *hwif = HWIF(drive);
drive->drive_data = ide_get_best_pio_mode(drive, pio, OPTI621_MAX_PIO, NULL);
for (d = 0; d < 2; ++d) {
drive = &hwif->drives[d];
if (drive->present) {
if (drive->drive_data == PIO_DONT_KNOW)
drive->drive_data = ide_get_best_pio_mode(drive, 255, OPTI621_MAX_PIO, NULL);
#ifdef OPTI621_DEBUG
printk("%s: Selected PIO mode %d\n",
drive->name, drive->drive_data);
#endif
} else {
drive->drive_data = PIO_NOT_EXIST;
}
}
}
static int redwood_config_drive_for_dma(ide_drive_t *drive)
{
struct hd_driveid *id = drive->id;
byte speed;
int func = ide_dma_off;
/*
* Enable DMA on any drive that has multiword DMA
*/
if (id->field_valid & 2) {
if (id->dma_mword & 0x0004) {
speed = XFER_MW_DMA_2;
func = ide_dma_on;
} else if (id->dma_mword & 0x0002) {
speed = XFER_MW_DMA_1;
func = ide_dma_on;
} else if (id->dma_mword & 1) {
speed = XFER_MW_DMA_0;
func = ide_dma_on;
} else if (id->dma_1word & 0x0004) {
speed = XFER_SW_DMA_2;
func = ide_dma_on;
} else {
speed = XFER_PIO_0 +
ide_get_best_pio_mode(drive, 255, 5, NULL);
}
}
redwood_ide_tune_drive(drive, redwood_ide_dma_2_pio(speed));
return redwood_ide_dmaproc(func, drive);
}
/*
* We only deal with PIO mode here - DMA mode 'using_dma' is not
* initialised at the point that this function is called.
*/
static void tune_sl82c105(ide_drive_t *drive, byte pio)
{
ide_hwif_t *hwif = HWIF(drive);
struct pci_dev *dev = hwif->pci_dev;
ide_pio_data_t p;
unsigned short drv_ctrl = 0x909;
unsigned int xfer_mode, reg;
reg = (hwif->channel ? 0x4c : 0x44) + (drive->select.b.unit ? 4 : 0);
pio = ide_get_best_pio_mode(drive, pio, 5, &p);
switch (pio) {
default:
case 0: xfer_mode = XFER_PIO_0; break;
case 1: xfer_mode = XFER_PIO_1; break;
case 2: xfer_mode = XFER_PIO_2; break;
case 3: xfer_mode = XFER_PIO_3; break;
case 4: xfer_mode = XFER_PIO_4; break;
}
if (ide_config_drive_speed(drive, xfer_mode) == 0)
drv_ctrl = get_timing_sl82c105(&p);
pci_write_config_word(dev, reg, drv_ctrl);
pci_read_config_word(dev, reg, &drv_ctrl);
printk("%s: selected %s (%dns) (%04X)\n", drive->name,
ide_xfer_verbose(xfer_mode), p.cycle_time, drv_ctrl);
}
/*
* Set PIO mode for the specified drive.
* This function computes timing parameters
* and sets controller registers accordingly.
*/
static void ali14xx_tune_drive (ide_drive_t *drive, u8 pio)
{
int driveNum;
int time1, time2;
u8 param1, param2, param3, param4;
unsigned long flags;
ide_pio_data_t d;
int bus_speed = system_bus_clock();
pio = ide_get_best_pio_mode(drive, pio, ALI_MAX_PIO, &d);
/* calculate timing, according to PIO mode */
time1 = d.cycle_time;
time2 = ide_pio_timings[pio].active_time;
param3 = param1 = (time2 * bus_speed + 999) / 1000;
param4 = param2 = (time1 * bus_speed + 999) / 1000 - param1;
if (pio < 3) {
param3 += 8;
param4 += 8;
}
printk(KERN_DEBUG "%s: PIO mode%d, t1=%dns, t2=%dns, cycles = %d+%d, %d+%d\n",
drive->name, pio, time1, time2, param1, param2, param3, param4);
/* stuff timing parameters into controller registers */
driveNum = (HWIF(drive)->index << 1) + drive->select.b.unit;
spin_lock_irqsave(&ide_lock, flags);
outb_p(regOn, basePort);
outReg(param1, regTab[driveNum].reg1);
outReg(param2, regTab[driveNum].reg2);
outReg(param3, regTab[driveNum].reg3);
outReg(param4, regTab[driveNum].reg4);
outb_p(regOff, basePort);
spin_unlock_irqrestore(&ide_lock, flags);
}
static void tune_dtc2278 (ide_drive_t *drive, byte pio)
{
unsigned long flags;
if (pio == 255)
pio = ide_get_best_pio_mode(drive);
if (pio >= 3) {
save_flags(flags);
cli();
/*
* This enables PIO mode4 (3?) on the first interface
*/
sub22(1,0xc3);
sub22(0,0xa0);
restore_flags(flags);
} else {
/* we don't know how to set it back again.. */
}
/*
* 32bit I/O has to be enabled for *both* drives at the same time.
*/
drive->io_32bit = 1;
HWIF(drive)->drives[!drive->select.b.unit].io_32bit = 1;
}
/* 0 1 2 3 4 5 6 7 8
* 960, 480, 390, 300, 240, 180, 120, 90, 60
* 180, 150, 120, 90, 60
* DMA_Speed
* 180, 120, 90, 90, 90, 60, 30
* 11, 5, 4, 3, 2, 1, 0
*/
static void pdcnew_tune_drive(ide_drive_t *drive, u8 pio)
{
u8 speed;
if (pio == 5) pio = 4;
speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, pio, NULL);
(void)pdcnew_new_tune_chipset(drive, speed);
}
static void config_cmd64x_chipset_for_pio (ide_drive_t *drive, u8 set_speed)
{
u8 speed = 0x00;
u8 set_pio = ide_get_best_pio_mode(drive, 4, 5, NULL);
cmd64x_tuneproc(drive, set_pio);
speed = XFER_PIO_0 + set_pio;
if (set_speed)
(void) ide_config_drive_speed(drive, speed);
}
/*
* cs5530_tuneproc() handles selection/setting of PIO modes
* for both the chipset and drive.
*
* The ide_init_cs5530() routine guarantees that all drives
* will have valid default PIO timings set up before we get here.
*/
static void cs5530_tuneproc (ide_drive_t *drive, byte pio) /* pio=255 means "autotune" */
{
ide_hwif_t *hwif = HWIF(drive);
unsigned int format, basereg = CS5530_BASEREG(hwif);
static byte modes[5] = {XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3, XFER_PIO_4};
pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
if (!cs5530_set_xfer_mode(drive, modes[pio])) {
format = (inl(basereg+4) >> 31) & 1;
outl(cs5530_pio_timings[format][pio], basereg+(drive->select.b.unit<<3));
}
static int slc90e66_config_drive_for_dma (ide_drive_t *drive)
{
u8 speed = ide_dma_speed(drive, slc90e66_ratemask(drive));
if (!(speed)) {
u8 tspeed = ide_get_best_pio_mode(drive, 255, 5, NULL);
speed = slc90e66_dma_2_pio(XFER_PIO_0 + tspeed);
}
(void) slc90e66_tune_chipset(drive, speed);
return ide_dma_enable(drive);
}
static int triflex_config_drive_for_dma(ide_drive_t *drive)
{
int speed = ide_dma_speed(drive, 0); /* No ultra speeds */
if (!speed) {
u8 pspeed = ide_get_best_pio_mode(drive, 255, 4, NULL);
speed = XFER_PIO_0 + pspeed;
}
(void) triflex_tune_chipset(drive, speed);
return ide_dma_enable(drive);
}
static void tx4938ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
ide_hwif_t *hwif = drive->hwif;
struct tx4938ide_platform_info *pdata = hwif->dev->platform_data;
u8 safe = pio;
ide_drive_t *pair;
pair = ide_get_pair_dev(drive);
if (pair)
safe = min(safe, ide_get_best_pio_mode(pair, 255, 5));
tx4938ide_tune_ebusc(pdata->ebus_ch, pdata->gbus_clock, safe);
}
int ide_timing_compute(ide_drive_t *drive, u8 speed,
struct ide_timing *t, int T, int UT)
{
u16 *id = drive->id;
struct ide_timing *s, p;
s = ide_timing_find_mode(speed);
if (s == NULL)
return -EINVAL;
*t = *s;
if (id[ATA_ID_FIELD_VALID] & 2) {
memset(&p, 0, sizeof(p));
if (speed <= XFER_PIO_2)
p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO];
else if ((speed <= XFER_PIO_4) ||
(speed == XFER_PIO_5 && !ata_id_is_cfa(id)))
p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO_IORDY];
else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
p.cycle = id[ATA_ID_EIDE_DMA_MIN];
ide_timing_merge(&p, t, t, IDE_TIMING_CYCLE | IDE_TIMING_CYC8B);
}
ide_timing_quantize(t, t, T, UT);
if (speed >= XFER_SW_DMA_0) {
u8 pio = ide_get_best_pio_mode(drive, 255, 5);
ide_timing_compute(drive, XFER_PIO_0 + pio, &p, T, UT);
ide_timing_merge(&p, t, t, IDE_TIMING_ALL);
}
if (t->act8b + t->rec8b < t->cyc8b) {
t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
t->rec8b = t->cyc8b - t->act8b;
}
if (t->active + t->recover < t->cycle) {
t->active += (t->cycle - (t->active + t->recover)) / 2;
t->recover = t->cycle - t->active;
}
return 0;
}
static void config_siimage_chipset_for_pio (ide_drive_t *drive, byte set_speed)
{
u8 channel_timings = siimage_taskfile_timing(HWIF(drive));
u8 speed = 0, set_pio = ide_get_best_pio_mode(drive, 4, 5, NULL);
/* WARNING PIO timing mess is going to happen b/w devices, argh */
if ((channel_timings != set_pio) && (set_pio > channel_timings))
set_pio = channel_timings;
siimage_tuneproc(drive, set_pio);
speed = XFER_PIO_0 + set_pio;
if (set_speed)
(void) ide_config_drive_speed(drive, speed);
}
static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
{
static const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
static const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
ide_hwif_t *hwif = drive->hwif;
struct pci_dev *dev = to_pci_dev(hwif->dev);
ide_drive_t *pair = ide_get_pair_dev(drive);
u32 speedt = 0;
u16 speedp = 0;
unsigned long addr = siimage_seldev(drive, 0x04);
unsigned long tfaddr = siimage_selreg(hwif, 0x02);
unsigned long base = (unsigned long)hwif->hwif_data;
u8 tf_pio = pio;
u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
u8 addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84)
: (mmio ? 0xB4 : 0x80);
u8 mode = 0;
u8 unit = drive->dn & 1;
if (pair) {
u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4);
if (pair_pio < tf_pio)
tf_pio = pair_pio;
}
speedp = data_speed[pio];
speedt = tf_speed[tf_pio];
sil_iowrite16(dev, speedp, addr);
sil_iowrite16(dev, speedt, tfaddr);
speedp = sil_ioread16(dev, tfaddr - 2);
speedp &= ~0x200;
mode = sil_ioread8(dev, base + addr_mask);
mode &= ~(unit ? 0x30 : 0x03);
if (ide_pio_need_iordy(drive, pio)) {
speedp |= 0x200;
mode |= unit ? 0x10 : 0x01;
}
sil_iowrite16(dev, speedp, tfaddr - 2);
sil_iowrite8(dev, mode, base + addr_mask);
}
static void aec62xx_tune_drive (ide_drive_t *drive, u8 pio)
{
u8 speed = 0;
u8 new_pio = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
switch(pio) {
case 5: speed = new_pio; break;
case 4: speed = XFER_PIO_4; break;
case 3: speed = XFER_PIO_3; break;
case 2: speed = XFER_PIO_2; break;
case 1: speed = XFER_PIO_1; break;
default: speed = XFER_PIO_0; break;
}
(void) aec62xx_tune_chipset(drive, speed);
}
static int svwks_tune_chipset (ide_drive_t *drive, u8 xferspeed)
{
u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
u8 dma_modes[] = { 0x77, 0x21, 0x20 };
u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 };
ide_hwif_t *hwif = HWIF(drive);
struct pci_dev *dev = hwif->pci_dev;
u8 speed;
u8 pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
u8 unit = (drive->select.b.unit & 0x01);
u8 csb5 = svwks_csb_check(dev);
u8 ultra_enable = 0, ultra_timing = 0;
u8 dma_timing = 0, pio_timing = 0;
u16 csb5_pio = 0;
if (xferspeed == 255) /* PIO auto-tuning */
speed = XFER_PIO_0 + pio;
else
speed = ide_rate_filter(svwks_ratemask(drive), xferspeed);
/* If we are about to put a disk into UDMA mode we screwed up.
Our code assumes we never _ever_ do this on an OSB4 */
if(dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4 &&
drive->media == ide_disk && speed >= XFER_UDMA_0)
BUG();
pci_read_config_byte(dev, drive_pci[drive->dn], &pio_timing);
pci_read_config_byte(dev, drive_pci2[drive->dn], &dma_timing);
pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
pci_read_config_word(dev, 0x4A, &csb5_pio);
pci_read_config_byte(dev, 0x54, &ultra_enable);
/* Per Specified Design by OEM, and ASIC Architect */
if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
if (!drive->init_speed) {
u8 dma_stat = hwif->INB(hwif->dma_status);
dma_pio:
if (((ultra_enable << (7-drive->dn) & 0x80) == 0x80) &&
((dma_stat & (1<<(5+unit))) == (1<<(5+unit)))) {
drive->current_speed = drive->init_speed = XFER_UDMA_0 + udma_modes[(ultra_timing >> (4*unit)) & ~(0xF0)];
return 0;
} else if ((dma_timing) &&
/**
* piix_tune_drive - tune a drive attached to a PIIX
* @drive: drive to tune
* @pio: desired PIO mode
*
* Set the interface PIO mode based upon the settings done by AMI BIOS
* (might be useful if drive is not registered in CMOS for any reason).
*/
static void piix_tune_drive (ide_drive_t *drive, u8 pio)
{
ide_hwif_t *hwif = HWIF(drive);
struct pci_dev *dev = hwif->pci_dev;
int is_slave = (&hwif->drives[1] == drive);
int master_port = hwif->channel ? 0x42 : 0x40;
int slave_port = 0x44;
unsigned long flags;
u16 master_data;
u8 slave_data;
static DEFINE_SPINLOCK(tune_lock);
/* ISP RTC */
u8 timings[][2] = { { 0, 0 },
{ 0, 0 },
{ 1, 0 },
{ 2, 1 },
{ 2, 3 }, };
pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
/*
* Master vs slave is synchronized above us but the slave register is
* shared by the two hwifs so the corner case of two slave timeouts in
* parallel must be locked.
*/
spin_lock_irqsave(&tune_lock, flags);
pci_read_config_word(dev, master_port, &master_data);
if (is_slave) {
master_data = master_data | 0x4000;
if (pio > 1)
/* enable PPE, IE and TIME */
master_data = master_data | 0x0070;
pci_read_config_byte(dev, slave_port, &slave_data);
slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0);
slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0));
} else {
master_data = master_data & 0xccf8;
if (pio > 1)
/* enable PPE, IE and TIME */
master_data = master_data | 0x0007;
master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
}
pci_write_config_word(dev, master_port, master_data);
if (is_slave)
pci_write_config_byte(dev, slave_port, slave_data);
spin_unlock_irqrestore(&tune_lock, flags);
}
static void palm_bk3710_tune_drive(ide_drive_t *drive, u8 pio)
{
ide_pio_data_t piodata;
int is_slave = drive->dn & 1;
ide_drive_t *mate;
void __iomem *base = (void *)drive->hwif->dma_base;
/*
* Obtain the drive PIO data for tuning the Palm Chip registers
*/
pio = ide_get_best_pio_mode(drive, pio, 4, &piodata);
mate = ide_get_paired_drive(drive);
palm_bk3710_setpiomode(base, mate, is_slave, piodata.cycle_time, pio);
(void)ide_config_drive_speed(drive, XFER_PIO_0 + pio);
}
static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
{
static const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
static const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
ide_hwif_t *hwif = HWIF(drive);
struct pci_dev *dev = to_pci_dev(hwif->dev);
ide_drive_t *pair = ide_get_paired_drive(drive);
u32 speedt = 0;
u16 speedp = 0;
unsigned long addr = siimage_seldev(drive, 0x04);
unsigned long tfaddr = siimage_selreg(hwif, 0x02);
unsigned long base = (unsigned long)hwif->hwif_data;
u8 tf_pio = pio;
u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
u8 addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84)
: (mmio ? 0xB4 : 0x80);
u8 mode = 0;
u8 unit = drive->select.b.unit;
/* trim *taskfile* PIO to the slowest of the master/slave */
if (pair->present) {
u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4);
if (pair_pio < tf_pio)
tf_pio = pair_pio;
}
/* cheat for now and use the docs */
speedp = data_speed[pio];
speedt = tf_speed[tf_pio];
sil_iowrite16(dev, speedp, addr);
sil_iowrite16(dev, speedt, tfaddr);
/* now set up IORDY */
speedp = sil_ioread16(dev, tfaddr - 2);
speedp &= ~0x200;
if (pio > 2)
speedp |= 0x200;
sil_iowrite16(dev, speedp, tfaddr - 2);
mode = sil_ioread8(dev, base + addr_mask);
mode &= ~(unit ? 0x30 : 0x03);
mode |= unit ? 0x10 : 0x01;
sil_iowrite8(dev, mode, base + addr_mask);
}
static void palm_bk3710_setpiomode(void __iomem *base, ide_drive_t *mate,
unsigned int dev, unsigned int cycletime,
unsigned int mode)
{
u8 t2, t2i, t0;
u32 val32;
struct ide_timing *t;
t = ide_timing_find_mode(XFER_PIO_0 + mode);
/* PIO Data Setup */
t0 = DIV_ROUND_UP(cycletime, ideclk_period);
t2 = DIV_ROUND_UP(t->active, ideclk_period);
t2i = t0 - t2 - 1;
t2 -= 1;
val32 = readl(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8));
val32 |= (t2 << (dev ? 8 : 0));
writel(val32, base + BK3710_DATSTB);
val32 = readl(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8));
val32 |= (t2i << (dev ? 8 : 0));
writel(val32, base + BK3710_DATRCVR);
if (mate) {
u8 mode2 = ide_get_best_pio_mode(mate, 255, 4);
if (mode2 < mode)
mode = mode2;
}
/* TASKFILE Setup */
t0 = DIV_ROUND_UP(t->cyc8b, ideclk_period);
t2 = DIV_ROUND_UP(t->act8b, ideclk_period);
t2i = t0 - t2 - 1;
t2 -= 1;
val32 = readl(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8));
val32 |= (t2 << (dev ? 8 : 0));
writel(val32, base + BK3710_REGSTB);
val32 = readl(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8));
val32 |= (t2i << (dev ? 8 : 0));
writel(val32, base + BK3710_REGRCVR);
}
static byte ht_pio2timings(ide_drive_t *drive, byte pio)
{
int active_time, recovery_time;
int active_cycles, recovery_cycles;
ide_pio_data_t d;
int bus_speed = system_bus_clock();
if (pio) {
pio = ide_get_best_pio_mode(drive, pio, 5, &d);
/*
* Just like opti621.c we try to calculate the
* actual cycle time for recovery and activity
* according system bus speed.
*/
active_time = ide_pio_timings[pio].active_time;
recovery_time = d.cycle_time
- active_time
- ide_pio_timings[pio].setup_time;
/*
* Cycle times should be Vesa bus cycles
*/
active_cycles = (active_time * bus_speed + 999) / 1000;
recovery_cycles = (recovery_time * bus_speed + 999) / 1000;
/*
* Upper and lower limits
*/
if (active_cycles < 2) active_cycles = 2;
if (recovery_cycles < 2) recovery_cycles = 2;
if (active_cycles > 15) active_cycles = 15;
if (recovery_cycles > 15) recovery_cycles = 0; /* 0==16 */
#ifdef DEBUG
printk("ht6560b: drive %s setting pio=%d recovery=%d (%dns) active=%d (%dns)\n", drive->name, pio, recovery_cycles, recovery_time, active_cycles, active_time);
#endif
return (byte)((recovery_cycles << 4) | active_cycles);
} else {
#ifdef DEBUG
printk("ht6560b: drive %s setting pio=0\n", drive->name);
#endif
return HT_TIMING_DEFAULT; /* default setting */
}
}
static void tune_umc (ide_drive_t *drive, byte pio)
{
unsigned long flags;
ide_hwgroup_t *hwgroup = ide_hwifs[HWIF(drive)->index^1].hwgroup;
pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
printk("%s: setting umc8672 to PIO mode%d (speed %d)\n", drive->name, pio, pio_to_umc[pio]);
save_flags(flags); /* all CPUs */
cli(); /* all CPUs */
if (hwgroup && hwgroup->handler != NULL) {
printk("umc8672: other interface is busy: exiting tune_umc()\n");
} else {
current_speeds[drive->name[2] - 'a'] = pio_to_umc[pio];
umc_set_speeds (current_speeds);
}
restore_flags(flags); /* all CPUs */
}
/* Calculate PIO timings */
static void
pmac_ide_tuneproc(ide_drive_t *drive, byte pio)
{
ide_pio_data_t d;
int i;
u32 *timings;
int accessTicks, recTicks;
i = pmac_ide_find(drive);
if (i < 0)
return;
pio = ide_get_best_pio_mode(drive, pio, 4, &d);
accessTicks = SYSCLK_TICKS(ide_pio_timings[pio].active_time);
if (drive->select.all & 0x10)
timings = &pmac_ide[i].timings[1];
else
timings = &pmac_ide[i].timings[0];
if (pmac_ide[i].kind == controller_kl_ata4) {
/* The "ata-4" IDE controller of Core99 machines */
accessTicks = SYSCLK_TICKS_UDMA(ide_pio_timings[pio].active_time * 1000);
recTicks = SYSCLK_TICKS_UDMA(d.cycle_time * 1000) - accessTicks;
*timings = ((*timings) & 0x1FFFFFC00) | accessTicks | (recTicks << 5);
} else {
/* The old "ata-3" IDE controller */
accessTicks = SYSCLK_TICKS(ide_pio_timings[pio].active_time);
if (accessTicks < 4)
accessTicks = 4;
recTicks = SYSCLK_TICKS(d.cycle_time) - accessTicks - 4;
if (recTicks < 1)
recTicks = 1;
*timings = ((*timings) & 0xFFFFFF800) | accessTicks | (recTicks << 5);
}
#ifdef IDE_PMAC_DEBUG
printk(KERN_ERR "ide_pmac: Set PIO timing for mode %d, reg: 0x%08x\n",
pio, *timings);
#endif
if (drive->select.all == IN_BYTE(IDE_SELECT_REG))
pmac_ide_selectproc(drive);
}
static void tune_ht6560b (ide_drive_t *drive, byte pio)
{
unsigned int hwif, unit;
if (pio == 255) { /* auto-tune */
if (drive->media != ide_disk)
pio = 0; /* some CDROMs don't like fast modes (?) */
else
pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
}
unit = drive->select.b.unit;
hwif = HWIF(drive)->index;
ht6560b_timings[hwif][unit] = pio_to_timings[pio];
if (pio == 0)
ht6560b_selects[hwif][unit] |= 0x20;
else
ht6560b_selects[hwif][unit] &= ~0x20;
}
static int piix_config_drive_for_dma (ide_drive_t *drive)
{
u8 speed = ide_dma_speed(drive, piix_ratemask(drive));
/* Some ICH devices cannot support DMA mode 0 */
if(speed == XFER_MW_DMA_0 && piix_faulty_dma0(HWIF(drive)))
speed = 0;
/* If no DMA speed was available or the chipset has DMA bugs
then disable DMA and use PIO */
if (!speed || no_piix_dma) {
u8 tspeed = ide_get_best_pio_mode(drive, 255, 5, NULL);
speed = piix_dma_2_pio(XFER_PIO_0 + tspeed);
}
(void) piix_tune_chipset(drive, speed);
return ide_dma_enable(drive);
}
/*
* Set PIO mode for the specified drive.
* This function computes timing parameters
* and sets controller registers accordingly.
*/
static void ali14xx_tune_drive (ide_drive_t *drive, byte pio)
{
int driveNum;
int time1, time2, time1a;
byte param1, param2, param3, param4;
struct hd_driveid *id = drive->id;
unsigned long flags;
if (pio == 255)
pio = ide_get_best_pio_mode(drive);
if (pio > 3)
pio = 3;
/* calculate timing, according to PIO mode */
time1 = timeTab[pio].time1;
time2 = timeTab[pio].time2;
if (pio == 3) {
time1a = (id->capability & 0x08) ? id->eide_pio_iordy : id->eide_pio;
if (time1a != 0 && time1a < time1)
time1 = time1a;
}
param3 = param1 = (time2 * ALI_14xx_BUS_SPEED + 999) / 1000;
param4 = param2 = (time1 * ALI_14xx_BUS_SPEED + 999) / 1000 - param1;
if (pio != 3) {
param3 += 8;
param4 += 8;
}
printk("%s: PIO mode%d, t1=%dns, t2=%dns, cycles = %d+%d, %d+%d\n",
drive->name, pio, time1, time2, param1, param2, param3, param4);
/* stuff timing parameters into controller registers */
driveNum = (HWIF(drive)->index << 1) + drive->select.b.unit;
save_flags(flags);
cli();
outb_p(regOn, basePort);
outReg(param1, regTab[driveNum].reg1);
outReg(param2, regTab[driveNum].reg2);
outReg(param3, regTab[driveNum].reg3);
outReg(param4, regTab[driveNum].reg4);
outb_p(regOff, basePort);
restore_flags(flags);
}
/*
* Based on settings done by AMI BIOS
* (might be useful if drive is not registered in CMOS for any reason).
*/
static void slc90e66_tune_drive (ide_drive_t *drive, u8 pio)
{
ide_hwif_t *hwif = HWIF(drive);
struct pci_dev *dev = hwif->pci_dev;
int is_slave = (&hwif->drives[1] == drive);
int master_port = hwif->channel ? 0x42 : 0x40;
int slave_port = 0x44;
unsigned long flags;
u16 master_data;
u8 slave_data;
/* ISP RTC */
u8 timings[][2] = { { 0, 0 },
{ 0, 0 },
{ 1, 0 },
{ 2, 1 },
{ 2, 3 },
};
pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
spin_lock_irqsave(&ide_lock, flags);
pci_read_config_word(dev, master_port, &master_data);
if (is_slave) {
master_data = master_data | 0x4000;
if (pio > 1)
/* enable PPE, IE and TIME */
master_data = master_data | 0x0070;
pci_read_config_byte(dev, slave_port, &slave_data);
slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0);
slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0));
} else {
master_data = master_data & 0xccf8;
if (pio > 1)
/* enable PPE, IE and TIME */
master_data = master_data | 0x0007;
master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
}
pci_write_config_word(dev, master_port, master_data);
if (is_slave)
pci_write_config_byte(dev, slave_port, slave_data);
spin_unlock_irqrestore(&ide_lock, flags);
}
static int slc90e66_config_drive_xfer_rate (ide_drive_t *drive)
{
ide_hwif_t *hwif = HWIF(drive);
struct hd_driveid *id = drive->id;
drive->init_speed = 0;
if (id && (id->capability & 1) && drive->autodma) {
if (ide_use_dma(drive) && slc90e66_config_drive_for_dma(drive))
return hwif->ide_dma_on(drive);
goto fast_ata_pio;
} else if ((id->capability & 8) || (id->field_valid & 2)) {
fast_ata_pio:
(void) hwif->speedproc(drive, XFER_PIO_0 +
ide_get_best_pio_mode(drive, 255, 4, NULL));
return hwif->ide_dma_off_quietly(drive);
}
/* IORDY not supported */
return 0;
}
static void tune_dtc2278 (ide_drive_t *drive, u8 pio)
{
unsigned long flags;
pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
if (pio >= 3) {
spin_lock_irqsave(&ide_lock, flags);
/*
* This enables PIO mode4 (3?) on the first interface
*/
sub22(1,0xc3);
sub22(0,0xa0);
spin_unlock_irqrestore(&ide_lock, flags);
} else {
/* we don't know how to set it back again.. */
}
/*
* 32bit I/O has to be enabled for *both* drives at the same time.
*/
drive->io_32bit = 1;
HWIF(drive)->drives[!drive->select.b.unit].io_32bit = 1;
}
static void pdcnew_tune_drive(ide_drive_t *drive, u8 pio)
{
pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
(void)pdcnew_tune_chipset(drive, XFER_PIO_0 + pio);
}
