void install_irq()
{
//reprogram the PICs
init_PIC();
//install the appropriate ISRs into the IDT
idt_set_gate(32, (unsigned)irq0, 0x08, 0x8E);
idt_set_gate(33, (unsigned)irq1, 0x08, 0x8E);
idt_set_gate(34, (unsigned)irq2, 0x08, 0x8E);
//turn on interupts!
__asm__ __volatile__("sti");
}
void idt_install()
{
idtp.size = sizeof(idt);
idtp.addr = (uint64_t)idt;
idt_set_gate(0, (uint64_t)isr0, 0x08, 0x8E);
idt_set_gate(14, (uint64_t)isr14, 0x08, 0x8E);
idt_set_gate(32, (uint64_t)irq0, 0x08, 0x8E);
idt_set_gate(33, (uint64_t)irq1, 0x08, 0x8E);
idt_set_gate(128, (uint64_t)isr80, 0x08, 0xEE);
idt_load(&idtp);
}
void idt_init(void){
init_interrupt_chip();
idt_ptr.limit = sizeof(idt_entry_t) * INTERRUPT_MAX - 1;
idt_ptr.base = (uint32)&idt_entries;
for(uint32 i = 0;i < 48;i++){
idt_set_gate(i,(uint32)isr_irq_func[i],0x08,0x8E);
}
idt_set_gate(128,(uint32)isr128,0x08,0xEF);
idt_flush((uint32)&idt_ptr);
}
/* Remaps the IRQs. Sets up the IDT. */
void idt_init() {
memset((uint8_t*)&idt_entries, 0, sizeof(idt_entry_t) * 256);
//Remap the IRQ table
outb(0x20, 0x11);
outb(0xA0, 0x11);
outb(0x21, 0x20);
outb(0xA1, 0x28);
outb(0x21, 0x04);
outb(0xA1, 0x02);
outb(0x21, 0x01);
outb(0xA1, 0x01);
outb(0x21, 0x0);
outb(0xA1, 0x0);
for (int i = 0; gates[i].type != 0; i++) {
idt_set_gate(gates[i].num, gates[i].fun, gates[i].type);
}
idt_ptr.limit = (sizeof(idt_entry_t) * 256) - 1;
idt_ptr.base = (uint32_t)&idt_entries;
asm volatile ("lidt %0"::"m"(idt_ptr):"memory");
// Some setup calls that come later on are not preemptible,
// so we wait until then to enable interrupts.
}
void load_irq()
{
outb(0x20, 0x11);
outb(0xA0, 0x11);
outb(0x21, 0x20);
outb(0xA1, 0x28);
outb(0x21, 0x04);
outb(0xA1, 0x02);
outb(0x21, 0x01);
outb(0xA1, 0x01);
outb(0x21, 0x0);
outb(0xA1, 0x0);
idt_set_gate(32,8, 0, 0x8E, 0, ((uint64_t)isr32));
idt_set_gate(33,8, 0, 0x8E, 0, ((uint64_t)isr33));
__asm__("sti");
}
static void init_idt()
{
memset(&idt_entries, 0, sizeof(idt_entry_t ) * 256);
idt_ptr.limit = sizeof(idt_entry_t) * 256 - 1;
idt_ptr.base = (uint64_t)&idt_entries;
idt_set_gate(0,8, 0, 0x0e, 0, ((uint64_t)&isr0));
_x86_64_asm_igdt(&idt_ptr);
};
// 初始化中断描述符表
void init_idt(void)
{
init_interrupt_chip();
idt_ptr.limit = sizeof(idt_entry_t) * INTERRUPT_MAX - 1;
idt_ptr.base = (uint32_t)&idt_entries;
// 0~31: 用于 CPU 的中断处理
// 32~47: Intel 保留
for (uint32_t i = 0; i < 48; ++i) {
idt_set_gate(i, (uint32_t)isr_irq_func[i], 0x08, 0x8E);
}
// 128 (0x80) 将来用于实现系统调用
idt_set_gate(128, (uint32_t)isr128, 0x08, 0xEF);
// 更新设置中断描述符表
idt_flush((uint32_t)&idt_ptr);
}
void idt_install()
{
int sizeidt = sizeof(struct idt_entry);
idtp.limit =(unsigned short) (sizeidt * 256) - 1;
idtp.base = (unsigned long)&idt;
memset((unsigned char*)&idt, 0, sizeidt* 256);
idt_set_gate(14,(unsigned)page_fault,0x08,0x8E);
idt_load();
}
void idt_install(){
idtp.limit = sizeof(idt) - 1;
idtp.base = (unsigned int)idt;
char * _s = (char*)idt;
int n = sizeof(idt);
while (n > 0){
n -= 1;
_s[n] = (char)0;
}
idt_load();
idt_set_gate(0,(int)__isr0,0x8,0x8e);
}
void pic_install(){
outb(PIC_1_CTRL,0x11); //icw1_init
outb(PIC_2_CTRL,0x11); //icw1_init
outb(PIC_1_DATA,32); //icw2 map pic_1_data to offset1(32);
outb(PIC_2_DATA,40); //icw2 map pic_2_data to offset2(40);
outb(PIC_1_DATA,4); //set bit 0x00000100, use line 2 connect to slave
outb(PIC_2_DATA,2); //set bit 0x00000010, tell slave that master use line 2
outb(PIC_1_DATA,1); //8086 mode
outb(PIC_2_DATA,1); //8086 mode
outb(PIC_1_DATA,0x0); //clear mask
outb(PIC_2_DATA,0x0); //clear mask
set_timer(CLOCK_FREQ);
irq_install_handler(0,timer_handler);
idt_set_gate(32, (unsigned)__irq0, 0x08, 0x8e);
irq_install_handler(1,keyboard_handler);
idt_set_gate(33, (unsigned)__irq1, 0x08, 0x8e);
}
/* Initialize the syscall manager */
void syscalls_init()
{
/* Get the current CPU data area */
cpu_t *cpu = cpu_data_area(CPU_CURRENT);
/* Software interrupts always work */
idt_set_gate(0x80, (uint32_t) &software_int_entry, IDT_GATE_INT, true);
/* SYSENTER is supported */
if (cpu->features[0] & CPUID_FEAT_EDX_SEP)
{
/* Set the SYSENTER support flag */
sysenter = true;
/* Set the kernel ESP value */
uint32_t low = 0, high = 0;
wrmsr(IA32_MSR_SYSENTER_ESP, low, high);
/* Set the kernel CS value */
low = KERNEL_CS;
wrmsr(IA32_MSR_SYSENTER_CS, low, high);
/* Set the kernel EIP value */
low = (uint32_t) &sysenter_entry;
wrmsr(IA32_MSR_SYSENTER_EIP, low, high);
}
/* SYSCALL is supported */
if (cpu->ext_features[0] & CPUID_FEAT_EDX_SEP)
{
/* Set the SYSCALL support flag */
syscall = true;
/* Set the kernel EFLAGS mask value */
uint32_t low = 0, high = 0;
wrmsr(AMD64_MSR_SFMASK, low, high);
/* Set the kernel EIP and segment registers */
low = (uint32_t) &syscall_entry;
high = (KERNEL_CS | (USER_CS << 16));
wrmsr(AMD64_MSR_STAR, low, high);
}
}
/* Installs the IDT */
void idt_install()
{
memset(&idt, 0, sizeof(struct idt_entry) * 256);
idtp.limit = (sizeof (struct idt_entry) * 256) - 1;
idtp.base = (uint64_t)&idt;
_x86_64_asm_igdt(&idtp);
idt_set_gate(0, (uint64_t)&x86_64_isr_vector0, 0x08, 0x8e);
idt_set_gate(13, (uint64_t)&x86_64_isr_vector13, 0x08, 0x8e); //gpf handler
idt_set_gate(14, (uint64_t)&x86_64_isr_vector14, 0x08, 0x8e); //pf handleR
idt_set_gate(32, (uint64_t)&x86_64_isr_vector1, 0x08, 0x8e); //timer
idt_set_gate(33, (uint64_t)&x86_64_isr_vector2, 0x08, 0x8e); //key board
idt_set_gate(128, (uint64_t)&x86_64_isr_vector3, 0x08, 0x8e); /*putchar, exit, malloc, getpid, getppid etc syscall */
idt_set_gate(129, (uint64_t)&x86_64_isr_vector4, 0x08, 0x8e);
//_x86_64_asm_igdt(&idtp);
irq_remap();
}
void init_idt()
{
idtPtr.limit = (sizeof(struct idt_entry) * MAX_IDT); //- 1;
idtPtr.base = (uint64_t) idtEntry;
memset(&idtEntry,0,(sizeof(struct idt_entry) * MAX_IDT));
//isr
idt_set_gate(0,(uint64_t)isr0,0x08, 0x8E);
idt_set_gate(13,(uint64_t)isr13,0x08, 0x8E);
idt_set_gate(14,(uint64_t)isr14,0x08, 0x8E);
idt_set_gate(128,(uint64_t)isr128,0x08, 0xEE);
//irq
idt_set_gate(32,(uint64_t)irq0,0x08,0x8E);
idt_set_gate(33,(uint64_t)irq1,0x08,0x8E);
_x86_64_asm_lidt(&idtPtr);
}
static void init_idt(void){
_idt_ptr.limit = sizeof(idt_entry_t) * 256 -1;
_idt_ptr.base = (uint32_t)&_idt;
memset(&_idt, 0, sizeof(idt_entry_t)*256);
idt_set_gate( 0, (uint32_t)__isr0 , 0x08, 0x8E);
idt_set_gate( 1, (uint32_t)__isr1 , 0x08, 0x8E);
idt_set_gate( 2, (uint32_t)__isr2 , 0x08, 0x8E);
idt_set_gate( 3, (uint32_t)__isr3 , 0x08, 0x8E);
idt_set_gate( 4, (uint32_t)__isr4 , 0x08, 0x8E);
idt_set_gate( 5, (uint32_t)__isr5 , 0x08, 0x8E);
idt_set_gate( 6, (uint32_t)__isr6 , 0x08, 0x8E);
idt_set_gate( 7, (uint32_t)__isr7 , 0x08, 0x8E);
idt_set_gate( 8, (uint32_t)__isr8 , 0x08, 0x8E);
idt_set_gate( 9, (uint32_t)__isr9 , 0x08, 0x8E);
idt_set_gate(10, (uint32_t)__isr10, 0x08, 0x8E);
idt_set_gate(11, (uint32_t)__isr11, 0x08, 0x8E);
idt_set_gate(12, (uint32_t)__isr12, 0x08, 0x8E);
idt_set_gate(13, (uint32_t)__isr13, 0x08, 0x8E);
idt_set_gate(14, (uint32_t)__isr14, 0x08, 0x8E);
idt_set_gate(15, (uint32_t)__isr15, 0x08, 0x8E);
idt_set_gate(16, (uint32_t)__isr16, 0x08, 0x8E);
idt_set_gate(17, (uint32_t)__isr17, 0x08, 0x8E);
idt_set_gate(18, (uint32_t)__isr18, 0x08, 0x8E);
idt_set_gate(19, (uint32_t)__isr19, 0x08, 0x8E);
idt_set_gate(20, (uint32_t)__isr20, 0x08, 0x8E);
idt_set_gate(21, (uint32_t)__isr21, 0x08, 0x8E);
idt_set_gate(22, (uint32_t)__isr22, 0x08, 0x8E);
idt_set_gate(23, (uint32_t)__isr23, 0x08, 0x8E);
idt_set_gate(24, (uint32_t)__isr24, 0x08, 0x8E);
idt_set_gate(25, (uint32_t)__isr25, 0x08, 0x8E);
idt_set_gate(26, (uint32_t)__isr26, 0x08, 0x8E);
idt_set_gate(27, (uint32_t)__isr27, 0x08, 0x8E);
idt_set_gate(28, (uint32_t)__isr28, 0x08, 0x8E);
idt_set_gate(29, (uint32_t)__isr29, 0x08, 0x8E);
idt_set_gate(30, (uint32_t)__isr30, 0x08, 0x8E);
idt_set_gate(31, (uint32_t)__isr31, 0x08, 0x8E);
outb(0x20, 0x11);
outb(0xA0, 0x11);
outb(0x21, 0x20);
outb(0xA1, 0x28);
outb(0x21, 0x04);
outb(0xA1, 0x02);
outb(0x21, 0x01);
outb(0xA1, 0x01);
outb(0x21, 0x0);
outb(0xA1, 0x0);
idt_set_gate(IRQ0, (uint32_t)__irq0, 0x08, 0x8E);
idt_set_gate(IRQ1, (uint32_t)__irq1, 0x08, 0x8E);
idt_set_gate(IRQ2, (uint32_t)__irq2, 0x08, 0x8E);
idt_set_gate(IRQ3, (uint32_t)__irq3, 0x08, 0x8E);
idt_set_gate(IRQ4, (uint32_t)__irq4, 0x08, 0x8E);
idt_set_gate(IRQ5, (uint32_t)__irq5, 0x08, 0x8E);
idt_set_gate(IRQ6, (uint32_t)__irq6, 0x08, 0x8E);
idt_set_gate(IRQ7, (uint32_t)__irq7, 0x08, 0x8E);
idt_set_gate(IRQ8, (uint32_t)__irq8, 0x08, 0x8E);
idt_set_gate(IRQ9, (uint32_t)__irq9, 0x08, 0x8E);
idt_set_gate(IRQ10, (uint32_t)__irq10, 0x08, 0x8E);
idt_set_gate(IRQ11, (uint32_t)__irq11, 0x08, 0x8E);
idt_set_gate(IRQ12, (uint32_t)__irq12, 0x08, 0x8E);
idt_set_gate(IRQ13, (uint32_t)__irq13, 0x08, 0x8E);
idt_set_gate(IRQ14, (uint32_t)__irq14, 0x08, 0x8E);
idt_set_gate(IRQ15, (uint32_t)__irq15, 0x08, 0x8E);
desctab_registerIntHandler(0 , isr0 );
desctab_registerIntHandler(1 , isr1 );
desctab_registerIntHandler(8 , isr8 );
desctab_registerIntHandler(13, isr13);
__flush_idt((uint32_t)&_idt_ptr);
}
void isrs_install()
{
idt_set_gate(0, (unsigned)isr0, 0x08, 0x8E);
idt_set_gate(1, (unsigned)isr1, 0x08, 0x8E);
idt_set_gate(2, (unsigned)isr2, 0x08, 0x8E);
idt_set_gate(3, (unsigned)isr3, 0x08, 0x8E);
idt_set_gate(4, (unsigned)isr4, 0x08, 0x8E);
idt_set_gate(5, (unsigned)isr5, 0x08, 0x8E);
idt_set_gate(6, (unsigned)isr6, 0x08, 0x8E);
idt_set_gate(7, (unsigned)isr7, 0x08, 0x8E);
idt_set_gate(8, (unsigned)isr8, 0x08, 0x8E);
idt_set_gate(9, (unsigned)isr9, 0x08, 0x8E);
idt_set_gate(10, (unsigned)isr10, 0x08, 0x8E);
idt_set_gate(11, (unsigned)isr11, 0x08, 0x8E);
idt_set_gate(12, (unsigned)isr12, 0x08, 0x8E);
idt_set_gate(13, (unsigned)isr13, 0x08, 0x8E);
idt_set_gate(14, (unsigned)isr14, 0x08, 0x8E);
idt_set_gate(15, (unsigned)isr15, 0x08, 0x8E);
idt_set_gate(16, (unsigned)isr16, 0x08, 0x8E);
idt_set_gate(17, (unsigned)isr17, 0x08, 0x8E);
idt_set_gate(18, (unsigned)isr18, 0x08, 0x8E);
idt_set_gate(19, (unsigned)isr19, 0x08, 0x8E);
idt_set_gate(20, (unsigned)isr20, 0x08, 0x8E);
idt_set_gate(21, (unsigned)isr21, 0x08, 0x8E);
idt_set_gate(22, (unsigned)isr22, 0x08, 0x8E);
idt_set_gate(23, (unsigned)isr23, 0x08, 0x8E);
idt_set_gate(24, (unsigned)isr24, 0x08, 0x8E);
idt_set_gate(25, (unsigned)isr25, 0x08, 0x8E);
idt_set_gate(26, (unsigned)isr26, 0x08, 0x8E);
idt_set_gate(27, (unsigned)isr27, 0x08, 0x8E);
idt_set_gate(28, (unsigned)isr28, 0x08, 0x8E);
idt_set_gate(29, (unsigned)isr29, 0x08, 0x8E);
idt_set_gate(30, (unsigned)isr30, 0x08, 0x8E);
idt_set_gate(31, (unsigned)isr31, 0x08, 0x8E);
}
void isr_install()
{
idt_set_gate(0, (unsigned long)isr0, 0x08, 0x8E);
idt_set_gate(1, (unsigned long)isr1, 0x08, 0x8E);
idt_set_gate(2, (unsigned long)isr2, 0x08, 0x8E);
idt_set_gate(3, (unsigned long)isr3, 0x08, 0x8E);
idt_set_gate(4, (unsigned long)isr4, 0x08, 0x8E);
idt_set_gate(5, (unsigned long)isr5, 0x08, 0x8E);
idt_set_gate(6, (unsigned long)isr6, 0x08, 0x8E);
idt_set_gate(7, (unsigned long)isr7, 0x08, 0x8E);
idt_set_gate(8, (unsigned long)isr8, 0x08, 0x8E);
idt_set_gate(9, (unsigned long)isr9, 0x08, 0x8E);
idt_set_gate(10, (unsigned long)isr10, 0x08, 0x8E);
idt_set_gate(11, (unsigned long)isr11, 0x08, 0x8E);
idt_set_gate(12, (unsigned long)isr12, 0x08, 0x8E);
idt_set_gate(13, (unsigned long)isr13, 0x08, 0x8E);
//Page fault look for handle in paging.c
idt_set_gate(15, (unsigned long)isr15, 0x08, 0x8E);
idt_set_gate(16, (unsigned long)isr16, 0x08, 0x8E);
idt_set_gate(17, (unsigned long)isr17, 0x08, 0x8E);
idt_set_gate(18, (unsigned long)isr18, 0x08, 0x8E);
idt_set_gate(19, (unsigned long)isr19, 0x08, 0x8E);
idt_set_gate(20, (unsigned long)isr20, 0x08, 0x8E);
idt_set_gate(21, (unsigned long)isr21, 0x08, 0x8E);
idt_set_gate(22, (unsigned long)isr22, 0x08, 0x8E);
idt_set_gate(23, (unsigned long)isr23, 0x08, 0x8E);
idt_set_gate(24, (unsigned long)isr24, 0x08, 0x8E);
idt_set_gate(25, (unsigned long)isr25, 0x08, 0x8E);
idt_set_gate(26, (unsigned long)isr26, 0x08, 0x8E);
idt_set_gate(27, (unsigned long)isr27, 0x08, 0x8E);
idt_set_gate(28, (unsigned long)isr28, 0x08, 0x8E);
idt_set_gate(29, (unsigned long)isr29, 0x08, 0x8E);
idt_set_gate(30, (unsigned long)isr30, 0x08, 0x8E);
idt_set_gate(31, (unsigned long)isr31, 0x08, 0x8E);
}
/* Installs the IDT */
void idt_install()
{
/* Sets the special IDT pointer up, just like in 'gdt.c' */
idtp.limit = (sizeof (struct idt_entry) * 256) - 1;
idtp.base = (dword)&idt;
/* Clear out the entire IDT, initializing it to zeros */
memset((unsigned char *)&idt, 0, (sizeof(struct idt_entry) * 256));
/* ISRs to the IDT here using idt_set_gate */
idt_set_gate(0, (dword)&handler_0, 0x08, 0xEE);
idt_set_gate(1, (dword)&handler_1, 0x08, 0xEE);
idt_set_gate(2, (dword)&handler_2, 0x08, 0xEE);
idt_set_gate(3, (dword)&handler_3, 0x08, 0xEE);
idt_set_gate(4, (dword)&handler_4, 0x08, 0xEE);
idt_set_gate(5, (dword)&handler_5, 0x08, 0xEE);
idt_set_gate(6, (dword)&handler_6, 0x08, 0xEE);
idt_set_gate(7, (dword)&handler_7, 0x08, 0xEE);
idt_set_gate(8, (dword)&handler_8, 0x08, 0xEE);
idt_set_gate(9, (dword)&handler_9, 0x08, 0xEE);
idt_set_gate(10, (dword)&handler_10, 0x08, 0xEE);
idt_set_gate(11, (dword)&handler_11, 0x08, 0xEE);
idt_set_gate(12, (dword)&handler_12, 0x08, 0xEE);
idt_set_gate(13, (dword)&handler_13, 0x08, 0xEE);
idt_set_gate(14, (dword)&handler_14, 0x08, 0xEE);
idt_set_gate(15, (dword)&handler_15, 0x08, 0xEE);
idt_set_gate(16, (dword)&handler_16, 0x08, 0xEE);
idt_set_gate(17, (dword)&handler_17, 0x08, 0xEE);
idt_set_gate(18, (dword)&handler_18, 0x08, 0xEE);
idt_set_gate(19, (dword)&handler_19, 0x08, 0xEE);
idt_set_gate(20, (dword)&handler_20, 0x08, 0xEE);
/* Points the processor's internal register to the new IDT */
idt_load();
}
void syscll_install () {
idt_set_gate ( 48, ( unsigned ) sys1, 0x08, 0x8E );
}
static void init_idt()
{
idt_ptr.limit = sizeof(idt_entry_t) * 256 - 1;
idt_ptr.base = (u32int)&idt_entries;
memset(&idt_entries, 0, sizeof(idt_entry_t) * 256);
// Remap the irq table
outb(0x20, 0x11);
outb(0xA0, 0x11);
outb(0x21, 0x20);
outb(0xA1, 0x28);
outb(0x21, 0x04);
outb(0xA1, 0x02);
outb(0x21, 0x01);
outb(0xA1, 0x01);
outb(0x21, 0x0);
outb(0xA1, 0x0);
idt_set_gate( 0, (u32int)isr0 , 0x08, 0x8E);
idt_set_gate( 1, (u32int)isr1 , 0x08, 0x8E);
idt_set_gate( 2, (u32int)isr2 , 0x08, 0x8E);
idt_set_gate( 3, (u32int)isr3 , 0x08, 0x8E);
idt_set_gate( 4, (u32int)isr4 , 0x08, 0x8E);
idt_set_gate( 5, (u32int)isr5 , 0x08, 0x8E);
idt_set_gate( 6, (u32int)isr6 , 0x08, 0x8E);
idt_set_gate( 7, (u32int)isr7 , 0x08, 0x8E);
idt_set_gate( 8, (u32int)isr8 , 0x08, 0x8E);
idt_set_gate( 9, (u32int)isr9 , 0x08, 0x8E);
idt_set_gate(10, (u32int)isr10, 0x08, 0x8E);
idt_set_gate(11, (u32int)isr11, 0x08, 0x8E);
idt_set_gate(12, (u32int)isr12, 0x08, 0x8E);
idt_set_gate(13, (u32int)isr13, 0x08, 0x8E);
idt_set_gate(14, (u32int)isr14, 0x08, 0x8E);
idt_set_gate(15, (u32int)isr15, 0x08, 0x8E);
idt_set_gate(16, (u32int)isr16, 0x08, 0x8E);
idt_set_gate(17, (u32int)isr17, 0x08, 0x8E);
idt_set_gate(18, (u32int)isr18, 0x08, 0x8E);
idt_set_gate(19, (u32int)isr19, 0x08, 0x8E);
idt_set_gate(20, (u32int)isr20, 0x08, 0x8E);
idt_set_gate(21, (u32int)isr21, 0x08, 0x8E);
idt_set_gate(22, (u32int)isr22, 0x08, 0x8E);
idt_set_gate(23, (u32int)isr23, 0x08, 0x8E);
idt_set_gate(24, (u32int)isr24, 0x08, 0x8E);
idt_set_gate(25, (u32int)isr25, 0x08, 0x8E);
idt_set_gate(26, (u32int)isr26, 0x08, 0x8E);
idt_set_gate(27, (u32int)isr27, 0x08, 0x8E);
idt_set_gate(28, (u32int)isr28, 0x08, 0x8E);
idt_set_gate(29, (u32int)isr29, 0x08, 0x8E);
idt_set_gate(30, (u32int)isr30, 0x08, 0x8E);
idt_set_gate(31, (u32int)isr31, 0x08, 0x8E);
idt_set_gate(32, (u32int)irq0, 0x08, 0x8E);
idt_set_gate(33, (u32int)irq1, 0x08, 0x8E);
idt_set_gate(34, (u32int)irq2, 0x08, 0x8E);
idt_set_gate(35, (u32int)irq3, 0x08, 0x8E);
idt_set_gate(36, (u32int)irq4, 0x08, 0x8E);
idt_set_gate(37, (u32int)irq5, 0x08, 0x8E);
idt_set_gate(38, (u32int)irq6, 0x08, 0x8E);
idt_set_gate(39, (u32int)irq7, 0x08, 0x8E);
idt_set_gate(40, (u32int)irq8, 0x08, 0x8E);
idt_set_gate(41, (u32int)irq9, 0x08, 0x8E);
idt_set_gate(42, (u32int)irq10, 0x08, 0x8E);
idt_set_gate(43, (u32int)irq11, 0x08, 0x8E);
idt_set_gate(44, (u32int)irq12, 0x08, 0x8E);
idt_set_gate(45, (u32int)irq13, 0x08, 0x8E);
idt_set_gate(46, (u32int)irq14, 0x08, 0x8E);
idt_set_gate(47, (u32int)irq15, 0x08, 0x8E);
idt_flush((u32int)&idt_ptr);
}
// Initialisation routine - zeroes all the interrupt service routines, and
// initialises the IDT.
void init_idt ()
{
// Zero all interrupt handlers initially.
memset (&interrupt_handlers, 0, sizeof (interrupt_handler_t) * 256);
// Just like the GDT, the IDT has a "limit" field that is set to the last valid byte in the IDT,
// after adding in the start position (i.e. size-1).
idt_ptr.limit = sizeof (idt_entry_t) * 256 - 1;
idt_ptr.base = (uint32_t) &idt_entries;
// Zero the IDT to start with.
memset (&idt_entries, 0, sizeof (idt_entry_t) * 255);
// Remap the irq table.
outb (0x20, 0x11);
outb (0xA0, 0x11);
outb (0x21, 0x20);
outb (0xA1, 0x28);
outb (0x21, 0x04);
outb (0xA1, 0x02);
outb (0x21, 0x01);
outb (0xA1, 0x01);
outb (0x21, 0x0);
outb (0xA1, 0x0);
// Set each gate in the IDT that we care about - that is:
// 0-32: Used by the CPU to report conditions, both normal and error.
// 255: Will be used later as a way to execute system calls.
idt_set_gate ( 0, (uint32_t)isr0 , 0x08, 0x8E);
idt_set_gate ( 1, (uint32_t)isr1 , 0x08, 0x8E);
idt_set_gate ( 2, (uint32_t)isr2 , 0x08, 0x8E);
idt_set_gate ( 3, (uint32_t)isr3 , 0x08, 0x8E);
idt_set_gate ( 4, (uint32_t)isr4 , 0x08, 0x8E);
idt_set_gate ( 5, (uint32_t)isr5 , 0x08, 0x8E);
idt_set_gate ( 6, (uint32_t)isr6 , 0x08, 0x8E);
idt_set_gate ( 7, (uint32_t)isr7 , 0x08, 0x8E);
idt_set_gate ( 8, (uint32_t)isr8 , 0x08, 0x8E);
idt_set_gate ( 9, (uint32_t)isr9 , 0x08, 0x8E);
idt_set_gate (10, (uint32_t)isr10, 0x08, 0x8E);
idt_set_gate (11, (uint32_t)isr11, 0x08, 0x8E);
idt_set_gate (12, (uint32_t)isr12, 0x08, 0x8E);
idt_set_gate (13, (uint32_t)isr13, 0x08, 0x8E);
idt_set_gate (14, (uint32_t)isr14, 0x08, 0x8E);
idt_set_gate (15, (uint32_t)isr15, 0x08, 0x8E);
idt_set_gate (16, (uint32_t)isr16, 0x08, 0x8E);
idt_set_gate (17, (uint32_t)isr17, 0x08, 0x8E);
idt_set_gate (18, (uint32_t)isr18, 0x08, 0x8E);
idt_set_gate (19, (uint32_t)isr19, 0x08, 0x8E);
idt_set_gate (20, (uint32_t)isr20, 0x08, 0x8E);
idt_set_gate (21, (uint32_t)isr21, 0x08, 0x8E);
idt_set_gate (22, (uint32_t)isr22, 0x08, 0x8E);
idt_set_gate (23, (uint32_t)isr23, 0x08, 0x8E);
idt_set_gate (24, (uint32_t)isr24, 0x08, 0x8E);
idt_set_gate (25, (uint32_t)isr25, 0x08, 0x8E);
idt_set_gate (26, (uint32_t)isr26, 0x08, 0x8E);
idt_set_gate (27, (uint32_t)isr27, 0x08, 0x8E);
idt_set_gate (28, (uint32_t)isr28, 0x08, 0x8E);
idt_set_gate (29, (uint32_t)isr29, 0x08, 0x8E);
idt_set_gate (30, (uint32_t)isr30, 0x08, 0x8E);
idt_set_gate (31, (uint32_t)isr31, 0x08, 0x8E);
idt_set_gate (32, (uint32_t)irq0, 0x08, 0x8E);
idt_set_gate (33, (uint32_t)irq1, 0x08, 0x8E);
idt_set_gate (34, (uint32_t)irq2, 0x08, 0x8E);
idt_set_gate (35, (uint32_t)irq3, 0x08, 0x8E);
idt_set_gate (36, (uint32_t)irq4, 0x08, 0x8E);
idt_set_gate (37, (uint32_t)irq5, 0x08, 0x8E);
idt_set_gate (38, (uint32_t)irq6, 0x08, 0x8E);
idt_set_gate (39, (uint32_t)irq7, 0x08, 0x8E);
idt_set_gate (40, (uint32_t)irq8, 0x08, 0x8E);
idt_set_gate (41, (uint32_t)irq9, 0x08, 0x8E);
idt_set_gate (42, (uint32_t)irq10, 0x08, 0x8E);
idt_set_gate (43, (uint32_t)irq11, 0x08, 0x8E);
idt_set_gate (44, (uint32_t)irq12, 0x08, 0x8E);
idt_set_gate (45, (uint32_t)irq13, 0x08, 0x8E);
idt_set_gate (46, (uint32_t)irq14, 0x08, 0x8E);
idt_set_gate (47, (uint32_t)irq15, 0x08, 0x8E);
idt_set_gate (255, (uint32_t)isr255, 0x08, 0x8E);
// Tell the CPU about our new IDT.
idt_flush ((uint32_t)&idt_ptr);
}
void
reload_idt ()
{
idt_init ();
_x86_64_asm_lidt (&idtr);
//register CPU exception handler
idt_set_gate (0x00, (uint64_t) exception0, 0x08, 0x8E);
idt_set_gate (0x01, (uint64_t) exception1, 0x08, 0x8E);
idt_set_gate (0x02, (uint64_t) exception2, 0x08, 0x8E);
idt_set_gate (0x03, (uint64_t) exception3, 0x08, 0x8E);
idt_set_gate (0x04, (uint64_t) exception4, 0x08, 0x8E);
idt_set_gate (0x05, (uint64_t) exception5, 0x08, 0x8E);
idt_set_gate (0x06, (uint64_t) exception6, 0x08, 0x8E);
idt_set_gate (0x07, (uint64_t) exception7, 0x08, 0x8E);
idt_set_gate (0x08, (uint64_t) exception8, 0x08, 0x8E);
idt_set_gate (0x09, (uint64_t) exception9, 0x08, 0x8E);
idt_set_gate (0x0A, (uint64_t) exception10, 0x08, 0x8E);
idt_set_gate (0x0B, (uint64_t) exception11, 0x08, 0x8E);
idt_set_gate (0x0C, (uint64_t) exception12, 0x08, 0x8E);
idt_set_gate (0x0D, (uint64_t) exception13, 0x08, 0x8E);
idt_set_gate (0x0E, (uint64_t) exception14, 0x08, 0x8E);
idt_set_gate (0x0F, (uint64_t) exception15, 0x08, 0x8E);
idt_set_gate (0x10, (uint64_t) exception16, 0x08, 0x8E);
idt_set_gate (0x11, (uint64_t) exception17, 0x08, 0x8E);
idt_set_gate (0x12, (uint64_t) exception18, 0x08, 0x8E);
idt_set_gate (0x13, (uint64_t) exception19, 0x08, 0x8E);
idt_set_gate (0x14, (uint64_t) exception20, 0x08, 0x8E);
idt_set_gate (0x15, (uint64_t) exception21, 0x08, 0x8E);
idt_set_gate (0x16, (uint64_t) exception22, 0x08, 0x8E);
idt_set_gate (0x17, (uint64_t) exception23, 0x08, 0x8E);
idt_set_gate (0x18, (uint64_t) exception24, 0x08, 0x8E);
idt_set_gate (0x19, (uint64_t) exception25, 0x08, 0x8E);
idt_set_gate (0x1A, (uint64_t) exception26, 0x08, 0x8E);
idt_set_gate (0x1B, (uint64_t) exception27, 0x08, 0x8E);
idt_set_gate (0x1C, (uint64_t) exception28, 0x08, 0x8E);
idt_set_gate (0x1D, (uint64_t) exception29, 0x08, 0x8E);
idt_set_gate (0x1E, (uint64_t) exception30, 0x08, 0x8E);
idt_set_gate (0x1F, (uint64_t) exception31, 0x08, 0x8E);
//register timer & kerboard interrupt handler
idt_set_gate (0x20, (uint64_t) isr32, 0x08, 0x8E);
idt_set_gate (0x21, (uint64_t) isr33, 0x08, 0x8E);
//regiter yield func for cooperative scheduling
idt_set_gate (0x80, (uint64_t) co_yield, 0x08, 0x8E);
}
void irq_install(void) {
outb(PIC1_COMMAND, 0x11);
outb(PIC2_COMMAND, 0x11);
outb(0x21, 0x20);
outb(0xA1, 0x28);
outb(0x21, 0x04);
outb(0xA1, 0x02);
outb(0x21, 0x01);
outb(0xA1, 0x01);
outb(0x21, 0x0);
outb(0xA1, 0x0);
idt_set_gate(32, (u32_t)irq0, 0x08, 0x8E);
idt_set_gate(33, (u32_t)irq1, 0x08, 0x8E);
idt_set_gate(34, (u32_t)irq2, 0x08, 0x8E);
idt_set_gate(35, (u32_t)irq3, 0x08, 0x8E);
idt_set_gate(36, (u32_t)irq4, 0x08, 0x8E);
idt_set_gate(37, (u32_t)irq5, 0x08, 0x8E);
idt_set_gate(38, (u32_t)irq6, 0x08, 0x8E);
idt_set_gate(39, (u32_t)irq7, 0x08, 0x8E);
idt_set_gate(40, (u32_t)irq8, 0x08, 0x8E);
idt_set_gate(41, (u32_t)irq9, 0x08, 0x8E);
idt_set_gate(42, (u32_t)irq10, 0x08, 0x8E);
idt_set_gate(43, (u32_t)irq11, 0x08, 0x8E);
idt_set_gate(44, (u32_t)irq12, 0x08, 0x8E);
idt_set_gate(45, (u32_t)irq13, 0x08, 0x8E);
idt_set_gate(46, (u32_t)irq14, 0x08, 0x8E);
idt_set_gate(47, (u32_t)irq15, 0x08, 0x8E);
}
void init_idt(void)
{
idt_ptr.limit = sizeof(idt_entry_t) * 256 - 1;
idt_ptr.base = (unsigned int)&idt_entries;
/* Initialise the IDT and handlers to 0 */
memset(&idt_entries, 0, sizeof(idt_entry_t) * 256);
/* Remap the IRQ table since they share common interrupt numbers as
* CPU-generated interrupts.
*/
outb(0x20, 0x11);
outb(0xA0, 0x11);
outb(0x21, 0x20);
outb(0xA1, 0x28);
outb(0x21, 0x04);
outb(0xA1, 0x02);
outb(0x21, 0x01);
outb(0xA1, 0x01);
outb(0x21, 0x0);
outb(0xA1, 0x0);
/* Register an interrupt vector for each possible trap */
idt_set_gate(0, (unsigned int)isr0, 0x08, 0x8E);
idt_set_gate(1, (unsigned int)isr1, 0x08, 0x8E);
idt_set_gate(2, (unsigned int)isr2, 0x08, 0x8E);
idt_set_gate(3, (unsigned int)isr3, 0x08, 0x8E);
idt_set_gate(4, (unsigned int)isr4, 0x08, 0x8E);
idt_set_gate(5, (unsigned int)isr5, 0x08, 0x8E);
idt_set_gate(6, (unsigned int)isr6, 0x08, 0x8E);
idt_set_gate(7, (unsigned int)isr7, 0x08, 0x8E);
idt_set_gate(8, (unsigned int)isr8, 0x08, 0x8E);
idt_set_gate(9, (unsigned int)isr9, 0x08, 0x8E);
idt_set_gate(10, (unsigned int)isr10, 0x08, 0x8E);
idt_set_gate(11, (unsigned int)isr11, 0x08, 0x8E);
idt_set_gate(12, (unsigned int)isr12, 0x08, 0x8E);
idt_set_gate(13, (unsigned int)isr13, 0x08, 0x8E);
idt_set_gate(14, (unsigned int)isr14, 0x08, 0x8E);
idt_set_gate(15, (unsigned int)isr15, 0x08, 0x8E);
idt_set_gate(16, (unsigned int)isr16, 0x08, 0x8E);
idt_set_gate(17, (unsigned int)isr17, 0x08, 0x8E);
idt_set_gate(18, (unsigned int)isr18, 0x08, 0x8E);
idt_set_gate(19, (unsigned int)isr19, 0x08, 0x8E);
idt_set_gate(20, (unsigned int)isr20, 0x08, 0x8E);
idt_set_gate(21, (unsigned int)isr21, 0x08, 0x8E);
idt_set_gate(22, (unsigned int)isr22, 0x08, 0x8E);
idt_set_gate(23, (unsigned int)isr23, 0x08, 0x8E);
idt_set_gate(24, (unsigned int)isr24, 0x08, 0x8E);
idt_set_gate(25, (unsigned int)isr25, 0x08, 0x8E);
idt_set_gate(26, (unsigned int)isr26, 0x08, 0x8E);
idt_set_gate(27, (unsigned int)isr27, 0x08, 0x8E);
idt_set_gate(28, (unsigned int)isr28, 0x08, 0x8E);
idt_set_gate(29, (unsigned int)isr29, 0x08, 0x8E);
idt_set_gate(30, (unsigned int)isr30, 0x08, 0x8E);
idt_set_gate(31, (unsigned int)isr31, 0x08, 0x8E);
idt_set_gate(SYSCALL, (unsigned int)isr128, 0x08, 0x8E);
/* Register an interrupt vector for each IRQ */
idt_set_gate(32, (unsigned int)irq0, 0x08, 0x8E);
idt_set_gate(33, (unsigned int)irq1, 0x08, 0x8E);
idt_set_gate(34, (unsigned int)irq2, 0x08, 0x8E);
idt_set_gate(35, (unsigned int)irq3, 0x08, 0x8E);
idt_set_gate(36, (unsigned int)irq4, 0x08, 0x8E);
idt_set_gate(37, (unsigned int)irq5, 0x08, 0x8E);
idt_set_gate(38, (unsigned int)irq6, 0x08, 0x8E);
idt_set_gate(39, (unsigned int)irq7, 0x08, 0x8E);
idt_set_gate(40, (unsigned int)irq8, 0x08, 0x8E);
idt_set_gate(41, (unsigned int)irq9, 0x08, 0x8E);
idt_set_gate(42, (unsigned int)irq10, 0x08, 0x8E);
idt_set_gate(43, (unsigned int)irq11, 0x08, 0x8E);
idt_set_gate(44, (unsigned int)irq12, 0x08, 0x8E);
idt_set_gate(45, (unsigned int)irq13, 0x08, 0x8E);
idt_set_gate(46, (unsigned int)irq14, 0x08, 0x8E);
idt_set_gate(47, (unsigned int)irq15, 0x08, 0x8E);
idt_flush((unsigned int)&idt_ptr); /* declared in flush.s */
memset(&interrupt_handlers, 0, sizeof(isr_t) * 256);
}
void init_idt()
{
bzero((uint8_t *)&interrupt_handlers, sizeof(interrupt_handler_t) * 256);
idt_ptr.limit = sizeof(idt_entry_t) * 256 - 1;
idt_ptr.base = (uint32_t)&idt_entries;
bzero((uint8_t *)&idt_entries, sizeof(idt_entry_t) * 256);
idt_set_gate( 0, (uint32_t)isr0, 0x08, 0x8E);
idt_set_gate( 1, (uint32_t)isr1, 0x08, 0x8E);
idt_set_gate( 2, (uint32_t)isr2, 0x08, 0x8E);
idt_set_gate( 3, (uint32_t)isr3, 0x08, 0x8E);
idt_set_gate( 4, (uint32_t)isr4, 0x08, 0x8E);
idt_set_gate( 5, (uint32_t)isr5, 0x08, 0x8E);
idt_set_gate( 6, (uint32_t)isr6, 0x08, 0x8E);
idt_set_gate( 7, (uint32_t)isr7, 0x08, 0x8E);
idt_set_gate( 8, (uint32_t)isr8, 0x08, 0x8E);
idt_set_gate( 9, (uint32_t)isr9, 0x08, 0x8E);
idt_set_gate(10, (uint32_t)isr10, 0x08, 0x8E);
idt_set_gate(11, (uint32_t)isr11, 0x08, 0x8E);
idt_set_gate(12, (uint32_t)isr12, 0x08, 0x8E);
idt_set_gate(13, (uint32_t)isr13, 0x08, 0x8E);
idt_set_gate(14, (uint32_t)isr14, 0x08, 0x8E);
idt_set_gate(15, (uint32_t)isr15, 0x08, 0x8E);
idt_set_gate(16, (uint32_t)isr16, 0x08, 0x8E);
idt_set_gate(17, (uint32_t)isr17, 0x08, 0x8E);
idt_set_gate(18, (uint32_t)isr18, 0x08, 0x8E);
idt_set_gate(19, (uint32_t)isr19, 0x08, 0x8E);
idt_set_gate(20, (uint32_t)isr20, 0x08, 0x8E);
idt_set_gate(21, (uint32_t)isr21, 0x08, 0x8E);
idt_set_gate(22, (uint32_t)isr22, 0x08, 0x8E);
idt_set_gate(23, (uint32_t)isr23, 0x08, 0x8E);
idt_set_gate(24, (uint32_t)isr24, 0x08, 0x8E);
idt_set_gate(25, (uint32_t)isr25, 0x08, 0x8E);
idt_set_gate(26, (uint32_t)isr26, 0x08, 0x8E);
idt_set_gate(27, (uint32_t)isr27, 0x08, 0x8E);
idt_set_gate(28, (uint32_t)isr28, 0x08, 0x8E);
idt_set_gate(29, (uint32_t)isr29, 0x08, 0x8E);
idt_set_gate(30, (uint32_t)isr30, 0x08, 0x8E);
idt_set_gate(31, (uint32_t)isr31, 0x08, 0x8E);
idt_set_gate(32, (uint32_t)irq0, 0x08, 0x8E);
idt_set_gate(33, (uint32_t)irq1, 0x08, 0x8E);
idt_set_gate(34, (uint32_t)irq2, 0x08, 0x8E);
idt_set_gate(35, (uint32_t)irq3, 0x08, 0x8E);
idt_set_gate(36, (uint32_t)irq4, 0x08, 0x8E);
idt_set_gate(37, (uint32_t)irq5, 0x08, 0x8E);
idt_set_gate(38, (uint32_t)irq6, 0x08, 0x8E);
idt_set_gate(39, (uint32_t)irq7, 0x08, 0x8E);
idt_set_gate(40, (uint32_t)irq8, 0x08, 0x8E);
idt_set_gate(41, (uint32_t)irq9, 0x08, 0x8E);
idt_set_gate(42, (uint32_t)irq10, 0x08, 0x8E);
idt_set_gate(43, (uint32_t)irq11, 0x08, 0x8E);
idt_set_gate(44, (uint32_t)irq12, 0x08, 0x8E);
idt_set_gate(45, (uint32_t)irq13, 0x08, 0x8E);
idt_set_gate(46, (uint32_t)irq14, 0x08, 0x8E);
idt_set_gate(47, (uint32_t)irq15, 0x08, 0x8E);
idt_set_gate(255, (uint32_t)isr255, 0x08, 0x8E);
idt_flush((uint32_t)&idt_ptr);
outb(0x20, 0x11); //initialze master
outb(0xA0, 0x11); //initialze slave
outb(0x21, 0x20); //set master's IRQ starts from 32
outb(0xA1, 0x28); //set slave's IRQ starts from 40
outb(0x21, 0x04); //set master's IR2 line connects with slave
outb(0xA1, 0x02); //set slave's output line connects with master's IR2 line
outb(0x21, 0x01); //work as 8086
outb(0xA1, 0x01);
outb(0x21, 0x00); //enable interrupt
outb(0xA1, 0x00);
}
/* We first remap the interrupt controllers, and then we install
* the appropriate ISRs to the correct entries in the IDT. This
* is just like installing the exception handlers */
void irq_install()
{
kprintc(":: Installing ", BLACK, LIGHT_RED);
kprintc("IRQs\n", BLACK, LIGHT_CYAN);
irq_remap();
idt_set_gate(32, (unsigned)_irq0, 0x08, 0x8E);
idt_set_gate(33, (unsigned)_irq1, 0x08, 0x8E);
idt_set_gate(34, (unsigned)_irq2, 0x08, 0x8E);
idt_set_gate(35, (unsigned)_irq3, 0x08, 0x8E);
idt_set_gate(36, (unsigned)_irq4, 0x08, 0x8E);
idt_set_gate(37, (unsigned)_irq5, 0x08, 0x8E);
idt_set_gate(38, (unsigned)_irq6, 0x08, 0x8E);
idt_set_gate(39, (unsigned)_irq7, 0x08, 0x8E);
idt_set_gate(40, (unsigned)_irq8, 0x08, 0x8E);
idt_set_gate(41, (unsigned)_irq9, 0x08, 0x8E);
idt_set_gate(42, (unsigned)_irq10, 0x08, 0x8E);
idt_set_gate(43, (unsigned)_irq11, 0x08, 0x8E);
idt_set_gate(44, (unsigned)_irq12, 0x08, 0x8E);
idt_set_gate(45, (unsigned)_irq13, 0x08, 0x8E);
idt_set_gate(46, (unsigned)_irq14, 0x08, 0x8E);
idt_set_gate(47, (unsigned)_irq15, 0x08, 0x8E);
}
void irq_gates(void) {
idt_set_gate(32, _irq0, 0x08, 0x8E);
idt_set_gate(33, _irq1, 0x08, 0x8E);
idt_set_gate(34, _irq2, 0x08, 0x8E);
idt_set_gate(35, _irq3, 0x08, 0x8E);
idt_set_gate(36, _irq4, 0x08, 0x8E);
idt_set_gate(37, _irq5, 0x08, 0x8E);
idt_set_gate(38, _irq6, 0x08, 0x8E);
idt_set_gate(39, _irq7, 0x08, 0x8E);
idt_set_gate(40, _irq8, 0x08, 0x8E);
idt_set_gate(41, _irq9, 0x08, 0x8E);
idt_set_gate(42, _irq10, 0x08, 0x8E);
idt_set_gate(43, _irq11, 0x08, 0x8E);
idt_set_gate(44, _irq12, 0x08, 0x8E);
idt_set_gate(45, _irq13, 0x08, 0x8E);
idt_set_gate(46, _irq14, 0x08, 0x8E);
idt_set_gate(47, _irq15, 0x08, 0x8E);
}
/*
* This is a very repetitive function... it's not hard, it's
* just annoying. As you can see, we set the first 32 entries
* in the IDT to the first 32 ISRs. We can't use a for loop
* for this, because there is no way to get the function names
* that correspond to that given entry. We set the access
* flags to 0x8E. This means that the entry is present, is
* running in ring 0 (kernel level), and has the lower 5 bits
* set to the required '14', which is represented by 'E' in
* hex.
*/
void isrs_install(void)
{
int i;
idt_set_gate(0, (size_t)isr0, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
idt_set_gate(1, (size_t)isr1, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
// NMI Exception gets its own stack (ist1)
idt_set_gate(2, (size_t)isr2, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 1);
idt_set_gate(3, (size_t)isr3, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
idt_set_gate(4, (size_t)isr4, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
idt_set_gate(5, (size_t)isr5, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
idt_set_gate(6, (size_t)isr6, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
idt_set_gate(7, (size_t)isr7, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
// Double Fault Exception gets its own stack (ist2)
idt_set_gate(8, (size_t)isr8, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 2);
idt_set_gate(9, (size_t)isr9, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
idt_set_gate(10, (size_t)isr10, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
idt_set_gate(11, (size_t)isr11, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
idt_set_gate(12, (size_t)isr12, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
idt_set_gate(13, (size_t)isr13, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
idt_set_gate(14, (size_t)isr14, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
idt_set_gate(15, (size_t)isr15, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
idt_set_gate(16, (size_t)isr16, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
idt_set_gate(17, (size_t)isr17, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
// Machine Check Exception gets its own stack (ist3)
idt_set_gate(18, (size_t)isr18, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 3);
idt_set_gate(19, (size_t)isr19, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
idt_set_gate(20, (size_t)isr20, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
idt_set_gate(21, (size_t)isr21, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
idt_set_gate(22, (size_t)isr22, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
idt_set_gate(23, (size_t)isr23, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
idt_set_gate(24, (size_t)isr24, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
idt_set_gate(25, (size_t)isr25, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
idt_set_gate(26, (size_t)isr26, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
idt_set_gate(27, (size_t)isr27, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
idt_set_gate(28, (size_t)isr28, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
idt_set_gate(29, (size_t)isr29, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
idt_set_gate(30, (size_t)isr30, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
idt_set_gate(31, (size_t)isr31, KERNEL_CODE_SELECTOR,
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP, 0);
// install the default handler
for(i=0; i<32; i++)
irq_install_handler(i, fault_handler);
// set hanlder for fpu exceptions
irq_uninstall_handler(7);
irq_install_handler(7, fpu_handler);
}
bool irq_initialize(){
PIC_remap(0x20,0x27);
idt_set_gate(32, (uint32_t)irq0 ,0x8 ,IDT_INTERRUPT_32);
idt_set_gate(33, (uint32_t)irq1 ,0x8 ,IDT_INTERRUPT_32);
idt_set_gate(34, (uint32_t)irq2 ,0x8 ,IDT_INTERRUPT_32);
idt_set_gate(35, (uint32_t)irq3 ,0x8 ,IDT_INTERRUPT_32);
idt_set_gate(36, (uint32_t)irq4 ,0x8 ,IDT_INTERRUPT_32);
idt_set_gate(37, (uint32_t)irq5 ,0x8 ,IDT_INTERRUPT_32);
idt_set_gate(38, (uint32_t)irq6 ,0x8 ,IDT_INTERRUPT_32);
idt_set_gate(39, (uint32_t)irq7 ,0x8 ,IDT_INTERRUPT_32);
idt_set_gate(40, (uint32_t)irq8 ,0x8 ,IDT_INTERRUPT_32);
idt_set_gate(41, (uint32_t)irq9 ,0x8 ,IDT_INTERRUPT_32);
idt_set_gate(42, (uint32_t)irq10 ,0x8 ,IDT_INTERRUPT_32);
idt_set_gate(43, (uint32_t)irq11 ,0x8 ,IDT_INTERRUPT_32);
idt_set_gate(44, (uint32_t)irq12 ,0x8 ,IDT_INTERRUPT_32);
idt_set_gate(45, (uint32_t)irq13 ,0x8 ,IDT_INTERRUPT_32);
idt_set_gate(46, (uint32_t)irq14 ,0x8 ,IDT_INTERRUPT_32);
idt_set_gate(47, (uint32_t)irq15 ,0x8 ,IDT_INTERRUPT_32);
return true;
}
void irq_install()
{
irq_remap();
idt_set_gate(32, (unsigned)irq0, 0x08, 0x8E);
idt_set_gate(33, (unsigned)irq1, 0x08, 0x8E);
idt_set_gate(34, (unsigned)irq2, 0x08, 0x8E);
idt_set_gate(35, (unsigned)irq3, 0x08, 0x8E);
idt_set_gate(36, (unsigned)irq4, 0x08, 0x8E);
idt_set_gate(37, (unsigned)irq5, 0x08, 0x8E);
idt_set_gate(38, (unsigned)irq6, 0x08, 0x8E);
idt_set_gate(39, (unsigned)irq7, 0x08, 0x8E);
idt_set_gate(40, (unsigned)irq8, 0x08, 0x8E);
idt_set_gate(41, (unsigned)irq9, 0x08, 0x8E);
idt_set_gate(42, (unsigned)irq10, 0x08, 0x8E);
idt_set_gate(43, (unsigned)irq11, 0x08, 0x8E);
idt_set_gate(44, (unsigned)irq12, 0x08, 0x8E);
idt_set_gate(45, (unsigned)irq13, 0x08, 0x8E);
idt_set_gate(46, (unsigned)irq14, 0x08, 0x8E);
idt_set_gate(47, (unsigned)irq15, 0x08, 0x8E);
}
void irq_install() // Installs IRQ entries in the IDT
{
irq_remap(); // Remaps IRQ entries before installing them
idt_set_gate(32, (unsigned)irq0, 0x08, 0x8E);
idt_set_gate(33, (unsigned)irq1, 0x08, 0x8E);
idt_set_gate(34, (unsigned)irq2, 0x08, 0x8E);
idt_set_gate(35, (unsigned)irq3, 0x08, 0x8E);
idt_set_gate(36, (unsigned)irq4, 0x08, 0x8E);
idt_set_gate(37, (unsigned)irq5, 0x08, 0x8E);
idt_set_gate(38, (unsigned)irq6, 0x08, 0x8E);
idt_set_gate(39, (unsigned)irq7, 0x08, 0x8E);
idt_set_gate(40, (unsigned)irq8, 0x08, 0x8E);
idt_set_gate(41, (unsigned)irq9, 0x08, 0x8E);
idt_set_gate(42, (unsigned)irq10, 0x08, 0x8E);
idt_set_gate(43, (unsigned)irq11, 0x08, 0x8E);
idt_set_gate(44, (unsigned)irq12, 0x08, 0x8E);
idt_set_gate(45, (unsigned)irq13, 0x08, 0x8E);
idt_set_gate(46, (unsigned)irq14, 0x08, 0x8E);
idt_set_gate(47, (unsigned)irq15, 0x08, 0x8E);
}
