static void crc_sanity_checks(igt_crc_t *crc)
{
int i;
bool all_zero = true;
for (i = 0; i < crc->n_words; i++) {
igt_warn_on_f(crc->crc[i] == 0xffffffff,
"Suspicious CRC: it looks like the CRC "
"read back was from a register in a powered "
"down well\n");
if (crc->crc[i])
all_zero = false;
}
igt_warn_on_f(all_zero, "Suspicious CRC: All values are 0.\n");
}
static void do_set_stereo_mode(struct connector *c)
{
uint32_t fb_id;
fb_id = igt_create_stereo_fb(drm_fd, &c->mode,
igt_bpp_depth_to_drm_format(bpp, depth),
tiling);
igt_warn_on_f(drmModeSetCrtc(drm_fd, c->crtc, fb_id, 0, 0, &c->id, 1, &c->mode),
"failed to set mode (%dx%d@%dHz): %s\n", width, height, c->mode.vrefresh, strerror(errno));
}
static void set_single(void)
{
int sigs[] = { SIGUSR1 };
struct sigaction sa;
sa.sa_handler = sighandler;
sigemptyset(&sa.sa_mask);
igt_warn_on_f(sigaction(sigs[0], &sa, NULL) == -1,
"Could not set signal handler");
}
/**
* intel_register_write:
* @reg: register offset
* @val: value to write
*
* 32-bit write to the register at @offset. This function only works when the new
* register access helper is initialized with intel_register_access_init().
*
* Compared to OUTREG() it can do optional checking with the register access
* white lists.
*/
void
intel_register_write(uint32_t reg, uint32_t val)
{
struct intel_register_range *range;
igt_assert(mmio_data.inited);
if (intel_gen(mmio_data.i915_devid) >= 6)
igt_assert(mmio_data.key != -1);
if (!mmio_data.safe)
goto write_out;
range = intel_get_register_range(mmio_data.map,
reg,
INTEL_RANGE_WRITE);
igt_warn_on_f(!range,
"Register write blocked for safety ""(*0x%08x = 0x%x)\n", reg, val);
write_out:
*(volatile uint32_t *)((volatile char *)igt_global_mmio + reg) = val;
}
