__s32 Image_init(__u32 screen_id) { image_clk_init(screen_id); /* when access image registers, must open MODULE CLOCK of image */ image_clk_on(screen_id, 0); DE_BE_Reg_Init(screen_id); Image_open(screen_id); DE_BE_EnableINT(screen_id, DE_IMG_REG_LOAD_FINISH); DE_BE_reg_auto_load_en(screen_id, 0); if(screen_id == 0) { OSAL_RegISR(gdisp.init_para.irq[DISP_MOD_BE0],0,scaler_event_proc, (void *)screen_id,0,0); #ifndef __LINUX_OSAL__ OSAL_InterruptEnable(gdisp.init_para.irq[DISP_MOD_BE0]); #endif } else if(screen_id == 1) { OSAL_RegISR(gdisp.init_para.irq[DISP_MOD_BE1],0,scaler_event_proc, (void *)screen_id,0,0); #ifndef __LINUX_OSAL__ OSAL_InterruptEnable(gdisp.init_para.irq[DISP_MOD_BE1]); #endif } return DIS_SUCCESS; }
__s32 Image_init(__u32 sel) { image_clk_init(sel); image_clk_on(sel); //when access image registers, must open MODULE CLOCK of image DE_BE_Reg_Init(sel); if(sel == 0) { BSP_disp_sprite_init(sel); } //DE_BE_Ready_Enable(sel, TRUE); Image_open(sel); if(sel == 0) { DE_BE_EnableINT(sel, DE_IMG_IRDY_IE); }//DE_BE_EnableINT(sel , DE_IMG_IRDY_IE); //when sel == 1, can't process when image0 module clk close //image_clk_off(sel); //close MODULE CLOCK of image if(sel == 0) { OSAL_RegISR(INTC_IRQNO_IMAGE0,0,Image_event_proc, (void *)sel,0,0); //OSAL_InterruptEnable(INTC_IRQNO_IMAGE0); } else if(sel == 1) { OSAL_RegISR(INTC_IRQNO_IMAGE1,0,Image_event_proc, (void *)sel,0,0); //OSAL_InterruptEnable(INTC_IRQNO_IMAGE1); } return DIS_SUCCESS; }
__s32 Image_init(__u32 sel) { image_clk_init(sel); image_clk_on(sel, 0); //when access image registers, must open MODULE CLOCK of image DE_BE_Reg_Init(sel); BSP_disp_sprite_init(sel); DE_BE_reg_auto_load_en(sel, 0); DE_BE_DisableINT(sel, DE_IMG_REG_LOAD_FINISH); image_clk_off(sel, 0); return DIS_SUCCESS; }
__s32 Image_init(__u32 sel) { image_clk_init(sel); image_clk_on(sel); //when access image registers, must open MODULE CLOCK of image DE_BE_Reg_Init(sel); BSP_disp_sprite_init(sel); BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_LCD); Image_open(sel); DE_BE_EnableINT(sel, DE_IMG_REG_LOAD_FINISH); DE_BE_reg_auto_load_en(sel, 0); return DIS_SUCCESS; }
__s32 Image_init(__u32 sel) { image_clk_init(sel); /* when access image registers, must open MODULE CLOCK of image */ image_clk_on(sel); DE_BE_Reg_Init(sel); BSP_disp_sprite_init(sel); if (sunxi_is_sun5i()) BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_LCD, gdisp.screen[sel].iep_status & DRC_USED); Image_open(sel); DE_BE_EnableINT(sel, DE_IMG_REG_LOAD_FINISH); DE_BE_reg_auto_load_en(sel, 0); return DIS_SUCCESS; }