void imx233_lcdif_init(void) { imx233_reset_block(&HW_LCDIF_CTRL); #if IMX233_SUBTARGET >= 3700 imx233_icoll_enable_interrupt(INT_SRC_LCDIF_ERROR, true); #endif }
void imx233_lradc_init(void) { arbiter_init(&channel_arbiter, HW_LRADC_NUM_CHANNELS); arbiter_init(&delay_arbiter, HW_LRADC_NUM_DELAYS); // enable block imx233_reset_block(&HW_LRADC_CTRL0); // disable ground ref __REG_CLR(HW_LRADC_CTRL0) = HW_LRADC_CTRL0__ONCHIP_GROUNDREF; // disable temperature sensors __REG_CLR(HW_LRADC_CTRL2) = HW_LRADC_CTRL2__TEMP_SENSOR_IENABLE0 | HW_LRADC_CTRL2__TEMP_SENSOR_IENABLE1; __REG_SET(HW_LRADC_CTRL2) = HW_LRADC_CTRL2__TEMPSENSE_PWD; // set frequency __REG_CLR(HW_LRADC_CTRL3) = HW_LRADC_CTRL3__CYCLE_TIME_BM; __REG_SET(HW_LRADC_CTRL3) = HW_LRADC_CTRL3__CYCLE_TIME__6MHz; // setup battery battery_chan = 7; imx233_lradc_reserve_channel(battery_chan); /* setup them for the simplest use: no accumulation, no division*/ imx233_lradc_setup_channel(battery_chan, false, false, 0, HW_LRADC_CHANNEL_BATTERY); /* setup delay channel for battery for automatic reading and scaling */ battery_delay_chan = 0; imx233_lradc_reserve_delay(battery_delay_chan); /* setup delay to trigger battery channel and retrigger itself. * The counter runs at 2KHz so a delay of 200 will trigger 10 * conversions per seconds */ imx233_lradc_setup_delay(battery_delay_chan, 1 << battery_chan, 1 << battery_delay_chan, 0, 200); imx233_lradc_kick_delay(battery_delay_chan); /* enable automatic conversion, use Li-Ion type battery */ imx233_lradc_setup_battery_conversion(true, HW_LRADC_CONVERSION__SCALE_FACTOR__LI_ION); }
void imx233_audioin_preinit(void) { /* Enable AUDIOIN block */ imx233_reset_block(&HW_AUDIOIN_CTRL); /* Enable ADC */ __REG_CLR(HW_AUDIOIN_ANACLKCTRL) = HW_AUDIOIN_ANACLKCTRL__CLKGATE; /* Set word-length to 16-bit */ __REG_SET(HW_AUDIOIN_CTRL) = HW_AUDIOIN_CTRL__WORD_LENGTH; }
void imx233_lradc_init(void) { if (!g_f_is_initialised) { g_f_is_initialised = 1; // enable block imx233_reset_block(&HW_LRADC_CTRL0); // disable ground ref __REG_CLR(HW_LRADC_CTRL0) = HW_LRADC_CTRL0__ONCHIP_GROUNDREF; // disable temperature sensors __REG_CLR(HW_LRADC_CTRL2) = HW_LRADC_CTRL2__TEMP_SENSOR_IENABLE0 | HW_LRADC_CTRL2__TEMP_SENSOR_IENABLE1; __REG_SET(HW_LRADC_CTRL2) = HW_LRADC_CTRL2__TEMPSENSE_PWD; // set frequency __REG_CLR(HW_LRADC_CTRL3) = HW_LRADC_CTRL3__CYCLE_TIME_BM; __REG_SET(HW_LRADC_CTRL3) = HW_LRADC_CTRL3__CYCLE_TIME__6MHz; } }
void imx233_lradc_init(void) { mutex_init(&free_bm_mutex); semaphore_init(&free_bm_sema, HW_LRADC_NUM_CHANNELS, HW_LRADC_NUM_CHANNELS); free_bm = (1 << HW_LRADC_NUM_CHANNELS) - 1; // enable block imx233_reset_block(&HW_LRADC_CTRL0); // disable ground ref __REG_CLR(HW_LRADC_CTRL0) = HW_LRADC_CTRL0__ONCHIP_GROUNDREF; // disable temperature sensors __REG_CLR(HW_LRADC_CTRL2) = HW_LRADC_CTRL2__TEMP_SENSOR_IENABLE0 | HW_LRADC_CTRL2__TEMP_SENSOR_IENABLE1; __REG_SET(HW_LRADC_CTRL2) = HW_LRADC_CTRL2__TEMPSENSE_PWD; // set frequency __REG_CLR(HW_LRADC_CTRL3) = HW_LRADC_CTRL3__CYCLE_TIME_BM; __REG_SET(HW_LRADC_CTRL3) = HW_LRADC_CTRL3__CYCLE_TIME__6MHz; }
void imx233_audioout_preinit(void) { /* Enable AUDIOOUT block */ imx233_reset_block(&HW_AUDIOOUT_CTRL); /* Enable digital filter clock */ imx233_clkctrl_enable(CLK_FILT, true); /* Enable DAC */ BF_CLR(AUDIOOUT_ANACLKCTRL, CLKGATE); /* Set capless mode */ #if IMX233_AUDIO_COUPLING_MODE == ACM_CAP BF_SET(AUDIOOUT_PWRDN, CAPLESS); #else BF_CLR(AUDIOOUT_PWRDN, CAPLESS); #endif /* Set word-length to 16-bit */ BF_SET(AUDIOOUT_CTRL, WORD_LENGTH); /* Power up DAC */ BF_CLR(AUDIOOUT_PWRDN, DAC); /* Hold HP to ground to avoid pop, then release and power up HP */ BF_SET(AUDIOOUT_ANACTRL, HP_HOLD_GND); BF_CLR(AUDIOOUT_PWRDN, HEADPHONE); /* Set HP mode to AB */ BF_SET(AUDIOOUT_ANACTRL, HP_CLASSAB); /* change bias to -50% */ BF_WR(AUDIOOUT_TEST, HP_I1_ADJ, 1); BF_WR(AUDIOOUT_REFCTRL, BIAS_CTRL, 1); #if IMX233_SUBTARGET >= 3700 BF_SET(AUDIOOUT_REFCTRL, RAISE_REF); #endif BF_SET(AUDIOOUT_REFCTRL, XTAL_BGR_BIAS); /* Stop holding to ground */ BF_CLR(AUDIOOUT_ANACTRL, HP_HOLD_GND); /* Set dmawait count to 31 (see errata, workaround random stop) */ BF_WR(AUDIOOUT_CTRL, DMAWAIT_COUNT, 31); /* start converting audio */ BF_SET(AUDIOOUT_CTRL, RUN); /* unmute DAC */ HW_AUDIOOUT_DACVOLUME_CLR = BM_OR2(AUDIOOUT_DACVOLUME, MUTE_LEFT, MUTE_RIGHT); /* send a few samples to avoid pop */ HW_AUDIOOUT_DATA = 0; HW_AUDIOOUT_DATA = 0; HW_AUDIOOUT_DATA = 0; HW_AUDIOOUT_DATA = 0; }
void imx233_audioout_preinit(void) { /* Enable AUDIOOUT block */ imx233_reset_block(&HW_AUDIOOUT_CTRL); /* Enable digital filter clock */ imx233_clkctrl_enable_xtal(XTAL_FILT, true); /* Enable DAC */ __REG_CLR(HW_AUDIOOUT_ANACLKCTRL) = HW_AUDIOOUT_ANACLKCTRL__CLKGATE; /* Set capless mode */ __REG_CLR(HW_AUDIOOUT_PWRDN) = HW_AUDIOOUT_PWRDN__CAPLESS; /* Set word-length to 16-bit */ __REG_SET(HW_AUDIOOUT_CTRL) = HW_AUDIOOUT_CTRL__WORD_LENGTH; /* Power up DAC */ __REG_CLR(HW_AUDIOOUT_PWRDN) = HW_AUDIOOUT_PWRDN__DAC; /* Hold HP to ground to avoid pop, then release and power up HP */ __REG_SET(HW_AUDIOOUT_ANACTRL) = HW_AUDIOOUT_ANACTRL__HP_HOLD_GND; __REG_CLR(HW_AUDIOOUT_PWRDN) = HW_AUDIOOUT_PWRDN__HEADPHONE; /* Set HP mode to AB */ __REG_SET(HW_AUDIOOUT_ANACTRL) = HW_AUDIOOUT_ANACTRL__HP_CLASSAB; /* change biais to -50% */ __REG_CLR(HW_AUDIOOUT_TEST) = HW_AUDIOOUT_TEST__HP_I1_ADJ_BM; __REG_SET(HW_AUDIOOUT_TEST) = HW_AUDIOOUT_TEST__HP_I1_ADJ_M_50; __REG_CLR(HW_AUDIOOUT_REFCTRL) = HW_AUDIOOUT_REFCTRL__BIAS_CTRL_BM; __REG_SET(HW_AUDIOOUT_REFCTRL) = 1 << HW_AUDIOOUT_REFCTRL__BIAS_CTRL_BP; __REG_SET(HW_AUDIOOUT_REFCTRL) = HW_AUDIOOUT_REFCTRL__RAISE_REF; __REG_SET(HW_AUDIOOUT_REFCTRL) = HW_AUDIOOUT_REFCTRL__XTAL_BGR_BIAS; /* Stop holding to ground */ __REG_CLR(HW_AUDIOOUT_ANACTRL) = HW_AUDIOOUT_ANACTRL__HP_HOLD_GND; /* Set dmawait count to 31 (see errata, workaround random stop) */ __REG_CLR(HW_AUDIOOUT_CTRL) = HW_AUDIOOUT_CTRL__DMAWAIT_COUNT_BM; __REG_SET(HW_AUDIOOUT_CTRL) = 31 << HW_AUDIOOUT_CTRL__DMAWAIT_COUNT_BP; /* start converting audio */ __REG_SET(HW_AUDIOOUT_CTRL) = HW_AUDIOOUT_CTRL__RUN; /* unmute DAC */ __REG_CLR(HW_AUDIOOUT_DACVOLUME) = HW_AUDIOOUT_DACVOLUME__MUTE_LEFT | HW_AUDIOOUT_DACVOLUME__MUTE_RIGHT; /* send a few samples to avoid pop */ HW_AUDIOOUT_DATA = 0; HW_AUDIOOUT_DATA = 0; HW_AUDIOOUT_DATA = 0; HW_AUDIOOUT_DATA = 0; /* wait for everything to stabilize before unmuting */ timeout_register(&hp_unmute_oneshort, hp_unmute_cb, HZ / 2, 0); }
static void imx233_i2c_reset(void) { /* clear softreset */ imx233_reset_block(&HW_I2C_CTRL0); /* Errata (imx233): * When RETAIN_CLOCK is set, the ninth clock pulse (ACK) is not generated. However, the SDA * line is read at the proper timing interval. If RETAIN_CLOCK is cleared, the ninth clock pulse is * generated. * HW_I2C_CTRL1[ACK_MODE] has default value of 0. It should be set to 1 to enable the fix for * this issue. */ #if IMX233_SUBTARGET >= 3780 BF_SET(I2C_CTRL1, ACK_MODE); #endif BF_SET(I2C_CTRL0, CLKGATE); /* Fast-mode @ 400K */ HW_I2C_TIMING0 = 0x000F0007; /* tHIGH=0.6us, read at 0.3us */ HW_I2C_TIMING1 = 0x001F000F; /* tLOW=1.3us, write at 0.6us */ HW_I2C_TIMING2 = 0x0015000D; }
void system_init(void) { imx233_reset_block(&HW_ICOLL_CTRL); /* disable all interrupts */ for(int i = 0; i < INT_SRC_NR_SOURCES; i++) { /* priority = 0, disable, disable fiq */ HW_ICOLL_INTERRUPT(i) = 0; } /* setup vbase as isr_table */ HW_ICOLL_VBASE = (uint32_t)&isr_table; /* enable final irq bit */ __REG_SET(HW_ICOLL_CTRL) = HW_ICOLL_CTRL__IRQ_FINAL_ENABLE; imx233_pinctrl_init(); imx233_timrot_init(); imx233_dma_init(); imx233_ssp_init(); imx233_dcp_init(); }
void imx233_dcp_init(void) { /* Reset block */ imx233_reset_block(&HW_DCP_CTRL); /* Setup contexte pointer */ HW_DCP_CONTEXT = (uint32_t)PHYSICAL_ADDR(&dcp_context); /* Enable context switching and caching */ __REG_SET(HW_DCP_CTRL) = HW_DCP_CTRL__ENABLE_CONTEXT_CACHING | HW_DCP_CTRL__ENABLE_CONTEXT_SWITCHING; /* Check that there are sufficiently many channels */ if(__XTRACT(HW_DCP_CAPABILITY0, NUM_CHANNELS) != HW_DCP_NUM_CHANNELS) panicf("DCP has %lu channels but was configured to use %d !", __XTRACT(HW_DCP_CAPABILITY0, NUM_CHANNELS), HW_DCP_NUM_CHANNELS); /* Setup channel arbiter to use */ arbiter_init(&channel_arbiter, HW_DCP_NUM_CHANNELS); /* Merge channel0 interrupt */ __REG_SET(HW_DCP_CHANNELCTRL) = HW_DCP_CHANNELCTRL__CH0_IRQ_MERGED; /* setup semaphores */ for(int i = 0; i< HW_DCP_NUM_CHANNELS; i++) semaphore_init(&channel_sema[i], 1, 0); }
void imx233_pwm_init(void) { imx233_reset_block(&HW_PWM_CTRL); imx233_clkctrl_enable(CLK_PWM, true); }
void dma_init(void) { /* Enable APHB and APBX */ imx233_reset_block(&HW_APBH_CTRL0); imx233_reset_block(&HW_APBX_CTRL0); }
void imx233_lcdif_reset(void) { imx233_reset_block(&HW_LCDIF_CTRL); }
void imx233_timrot_init(void) { imx233_reset_block(&HW_TIMROT_ROTCTRL); /* enable xtal path to timrot */ imx233_clkctrl_enable(CLK_TIMROT, true); }