/** Initialize the PIC. */
__init_text void pic_init(void) {
/* Send an initialization command to both PICs (ICW1). */
out8(PIC_MASTER_COMMAND, PIC_ICW1_INIT | PIC_ICW1_ICW4);
out8(PIC_SLAVE_COMMAND, PIC_ICW1_INIT | PIC_ICW1_ICW4);
/* Set the interrupt vectors to use (ICW2). */
out8(PIC_MASTER_DATA, 32);
out8(PIC_SLAVE_DATA, 32 + 8);
/* Set how the PICs are connected to each other (ICW3). */
out8(PIC_MASTER_DATA, 0x04);
out8(PIC_SLAVE_DATA, 0x02);
/* Set other behaviour flags (ICW4). */
out8(PIC_MASTER_DATA, PIC_ICW4_8086);
out8(PIC_SLAVE_DATA, PIC_ICW4_8086);
/* Set initial IRQ masks. */
out8(PIC_MASTER_DATA, pic_mask_master);
out8(PIC_SLAVE_DATA, pic_mask_slave);
/* Get the trigger modes. */
pic_level_triggered = (in8(PIC_SLAVE_ELCR) << 8) | in8(PIC_MASTER_ELCR);
/* Initialize the IRQ handling system. */
irq_init(&pic_irq_controller);
}
/** Pre-handling function.
* @param num IRQ number.
* @return True if IRQ should be handled. */
static bool pic_pre_handle(unsigned num) {
assert(num < 16);
/* Check for spurious IRQs. */
if(num == 7) {
/* Read the In-Service Register, check the high bit. */
out8(0x23, 3);
if((in8(0x20) & 0x80) == 0) {
kprintf(LOG_DEBUG, "pic: spurious IRQ7 (master), ignoring...\n");
return false;
}
} else if(num == 15) {
/* Read the In-Service Register, check the high bit. */
out8(0xA3, 3);
if((in8(0xA0) & 0x80) == 0) {
kprintf(LOG_DEBUG, "pic: spurious IRQ15 (slave), ignoring...\n");
return false;
}
}
/* Edge-triggered interrupts must be acked before we handle. */
if(!(pic_level_triggered & (1 << num)))
pic_eoi(num);
return true;
}
void irqctrl_disable(unsigned int irq) {
if (irq < 8) {
out8(in8(PIC1_DATA) | (1 << irq), PIC1_DATA);
} else {
out8(in8(PIC2_DATA) | (1 << (irq - 8)), PIC2_DATA);
}
}
int irqctrl_pending(unsigned int irq) {
if (irq < 8) {
return in8(PIC1_COMMAND) & (1 << irq);
} else {
return in8(PIC2_COMMAND) & (1 << (irq - 8));
}
}
static int init_dma(pci_bus_cookie *cookie)
{
addr_t temp;
uint8 val = in8(cookie->io_port + BM_STATUS_REG );
TRACE(("entering init_dma status = %d\n",val));
if (!( val &( BM_SR_MASK_DRV1 | BM_SR_MASK_DRV0 )))
{
TRACE(("BM_STATUS is wrong %d\n",val));
return -1;
}
cookie->prd_region_id = vm_create_anonymous_region(vm_get_kernel_aspace_id(), "ide_prd_buf", (void **)&cookie->prd_buf_address,
REGION_ADDR_ANY_ADDRESS, 4096, REGION_WIRING_WIRED_CONTIG, LOCK_KERNEL|LOCK_RW);
cookie->stat_reg = in8( cookie->io_port + + BM_STATUS_REG );
cookie->stat_reg = cookie->stat_reg & 0xe0;
memset(cookie->prd_buf_address, 0, 4096);
vm_get_page_mapping(vm_get_kernel_aspace_id(), (addr_t)cookie->prd_buf_address, &cookie->prd_phy_address);
cookie->raw_buffer = (uint8*)0x80000;
vm_map_physical_memory(vm_get_kernel_aspace_id(), "test", (void *)&cookie->mapped_address, REGION_ADDR_ANY_ADDRESS,0x10000, LOCK_RW|LOCK_KERNEL, (addr_t)cookie->raw_buffer);
TRACE(("mapped address is %X\n",cookie->mapped_address));
return 0;
}
char
arch_debug_serial_getchar(void)
{
while ((in8(sSerialBasePort + SERIAL_LINE_STATUS) & 0x1) == 0)
asm volatile ("pause;");
return in8(sSerialBasePort + SERIAL_RECEIVE_BUFFER);
}
int checkboard(void)
{
printf ("Board: MPC8641HPCN, System ID: 0x%02x, "
"System Version: 0x%02x, FPGA Version: 0x%02x\n",
in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
in8(PIXIS_BASE + PIXIS_PVER));
return 0;
}
int readkbd_one(u8* buf)
{
u8 flag = in8(0x64);
if( (flag&1) == 0)return 0;
buf[0] = in8(0x60);
return 1;
}
unsigned long
get_board_sys_clk(ulong dummy)
{
u8 i, go_bit, rd_clks;
ulong val = 0;
go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
go_bit &= 0x01;
rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
rd_clks &= 0x1C;
/*
* Only if both go bit and the SCLK bit in VCFGEN0 are set
* should we be using the AUX register. Remember, we also set the
* GO bit to boot from the alternate bank on the on-board flash
*/
if (go_bit) {
if (rd_clks == 0x1c)
i = in8(PIXIS_BASE + PIXIS_AUX);
else
i = in8(PIXIS_BASE + PIXIS_SPD);
} else {
i = in8(PIXIS_BASE + PIXIS_SPD);
}
i &= 0x07;
switch (i) {
case 0:
val = 33333333;
break;
case 1:
val = 40000000;
break;
case 2:
val = 50000000;
break;
case 3:
val = 66666666;
break;
case 4:
val = 83000000;
break;
case 5:
val = 100000000;
break;
case 6:
val = 133333333;
break;
case 7:
val = 166666666;
break;
}
return val;
}
static cycle_t i8253_read(void) {
unsigned char lsb, msb;
out8(PIT_SEL0 | PIT_LATCH, MODE_REG);
lsb = in8(CHANNEL0);
msb = in8(CHANNEL0);
return PIT_LOAD - ((msb << 8) | lsb);
}
//*** AD関連 *************************************************************
int AD_Read(int ch) //AD読み込み シングルエンド・バイポーラ
{
int data;
out8(ADCVT,(8+(ch-1)));
while((in8(ADSTS) & 0x80) == 0){;}
data=((in8(ADU)<<8)+(in8(ADL)));
if(data>=2048) data=data-4096;
return data;
}
void
pic_disable(uint16& enabledInterrupts)
{
enabledInterrupts = ~(in8(PIC_MASTER_MASK) | in8(PIC_SLAVE_MASK) << 8);
enabledInterrupts &= 0xfffb; // remove slave PIC from the mask
// Mask off all interrupts on master and slave
out8(0xff, PIC_MASTER_MASK);
out8(0xff, PIC_SLAVE_MASK);
}
char arch_dbg_con_read(void)
{
#if BOCHS_E9_HACK
return in8(0xe9);
#else
while ((in8(serial_ioport_base+5) & 1) == 0)
;
return in8(serial_ioport_base);
#endif
}
void Hal::laufbandStop() {
halMutex->lock();
uint8_t val = in8(DIO_BASE + DIO_OFFS_A);
out8(DIO_BASE + DIO_OFFS_A, val & ~BIT_0);
val = in8(DIO_BASE + DIO_OFFS_A);
out8(DIO_BASE + DIO_OFFS_A, val & ~BIT_1);
val = in8(DIO_BASE + DIO_OFFS_A);
out8(DIO_BASE + DIO_OFFS_A, val | BIT_3);
halMutex->unlock();
}
static int uart_post_getc (unsigned long dev_base)
{
int i;
/* Wait for character available */
for (i = 0; i < 3500; i++) {
if (in8 (dev_base + UART_LSR) & asyncLSRDataReady1)
break;
udelay (100);
}
return 0xff & in8 (dev_base + UART_RBR);
}
static void arch_reset_kbd(void) {
while (in8(0x64) & 0x2) {
}
out8(0x60, 0x64);
while (in8(0x64) & 0x2) {
}
out8(0x4, 0x60);
while (in8(0x64) & 0x2) {
}
out8(0xfe, 0x64);
}
static void _i2c_bus_reset (void)
{
int i, status;
/* Reset status register */
/* write 1 in SCMP and IRQA to clear these fields */
out8 (IIC_STS, 0x0A);
/* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
out8 (IIC_EXTSTS, 0x8F);
__asm__ volatile ("eieio");
/*
* Get current state, reset bus
* only if no transfers are pending.
*/
i = 10;
do {
/* Get status */
status = in8 (IIC_STS);
udelay (500); /* 500us */
i--;
} while ((status & IIC_STS_PT) && (i > 0));
/* Soft reset controller */
status = in8 (IIC_XTCNTLSS);
out8 (IIC_XTCNTLSS, (status | IIC_XTCNTLSS_SRST));
__asm__ volatile ("eieio");
/* make sure where in initial state, data hi, clock hi */
out8 (IIC_DIRECTCNTL, 0xC);
for (i = 0; i < 10; i++) {
if ((in8 (IIC_DIRECTCNTL) & 0x3) != 0x3) {
/* clock until we get to known state */
out8 (IIC_DIRECTCNTL, 0x8); /* clock lo */
udelay (100); /* 100us */
out8 (IIC_DIRECTCNTL, 0xC); /* clock hi */
udelay (100); /* 100us */
} else {
break;
}
}
/* send start condition */
out8 (IIC_DIRECTCNTL, 0x4);
udelay (1000); /* 1ms */
/* send stop condition */
out8 (IIC_DIRECTCNTL, 0xC);
udelay (1000); /* 1ms */
/* Unreset controller */
out8 (IIC_XTCNTLSS, (status & ~IIC_XTCNTLSS_SRST));
udelay (1000); /* 1ms */
}
int main(int argc, char *argv[]) {
int privity_err;
uintptr_t ctrl_handle_chennalReg;
uintptr_t ctrl_handle_Inputgain;
uintptr_t ctrl_handle_commandRegMSB;
uintptr_t ctrl_handle_commandRegLSB;
uintptr_t ctrl_handle_portA;
int LSB, MSB, DATA;
struct timespec my_timer_value;
my_timer_value.tv_nsec = 10000; //10us
/* Give this thread root permissions to access the hardware */
privity_err = ThreadCtl( _NTO_TCTL_IO, NULL );
if ( privity_err == -1 )
{
fprintf( stderr, "can't get root permissions\n" );
return -1;
}
ctrl_handle_commandRegLSB = mmap_device_io( PORT_LENGTH, BASE_ADDR);
ctrl_handle_commandRegMSB = mmap_device_io( PORT_LENGTH, BASE_ADDR+1);
ctrl_handle_chennalReg = mmap_device_io( PORT_LENGTH, BASE_ADDR + 2);
ctrl_handle_Inputgain = mmap_device_io( PORT_LENGTH, BASE_ADDR + 3);
ctrl_handle_portA = mmap_device_io( PORT_LENGTH, BASE_ADDR + 8);
ctrl_handle_DIO = mmap_device_io(PORT_LENGTH, BASE_ADDR + B);
out8(ctrl_handle_chennalReg, 0xF0);
// Set Analog Input as -5V to +5V
out8( ctrl_handle_Inputgain, 0x01 );
int port_value = in8(ctrl_handle_Inputgain);
while (port_value & 0x20)
{
//nanospin( &my_timer_value );
port_value = in8(ctrl_handle_Inputgain);
}
out8(ctrl_handle_commandRegLSB, 0x80);
while (in8(ctrl_handle_Inputgain) & 0x80);
LSB = in8(ctrl_handle_commandRegLSB);
MSB = in8(ctrl_handle_commandRegMSB);
DATA = MSB*256 + LSB;
printf("Welcome to the QNX Momentics IDE\n");
return EXIT_SUCCESS;
}
int
arch_debug_serial_try_getchar(void)
{
uint8 lineStatus = in8(sSerialBasePort + SERIAL_LINE_STATUS);
if (lineStatus == 0xff) {
// The "data available" bit is set, but also all error bits. Likely we
// don't have a valid I/O port.
return -1;
}
if ((lineStatus & 0x1) == 0)
return -1;
return in8(sSerialBasePort + SERIAL_RECEIVE_BUFFER);
}
void serial_init(uint16_t port)
{
while (!(in8(port + 5) & 0x60)); /* wait until not busy */
out8(port + 1, 0x00); /* disable generating interrupts */
out8(port + 3, 0x80); /* line control register: command: set divisor */
out8(port, 0x01); /* set low byte of divisor to 0x01 = 115200 baud */
out8(port + 1, 0x00); /* set high byte of divisor to 0x00 */
out8(port + 3, 0x03); /* line control register: set 8 bit, no parity, 1 stop bit */
out8(port + 4, 0x0b); /* modem control register: set DTR/RTS/OUT2 */
in8(port); /* clear recevier port */
in8(port + 5); /* clear line status port */
in8(port + 6); /* clear modem status port */
}
void
pic_init()
{
static const interrupt_controller picController = {
"8259 PIC",
&pic_enable_io_interrupt,
&pic_disable_io_interrupt,
&pic_configure_io_interrupt,
&pic_is_spurious_interrupt,
&pic_is_level_triggered_interrupt,
&pic_end_of_interrupt
};
// Start initialization sequence for the master and slave PICs
out8(PIC_INIT1 | PIC_INIT1_SEND_INIT4, PIC_MASTER_INIT1);
out8(PIC_INIT1 | PIC_INIT1_SEND_INIT4, PIC_SLAVE_INIT1);
// Set start of interrupts to 0x20 for master, 0x28 for slave
out8(ARCH_INTERRUPT_BASE, PIC_MASTER_INIT2);
out8(ARCH_INTERRUPT_BASE + PIC_SLAVE_INT_BASE, PIC_SLAVE_INIT2);
// Specify cascading through interrupt 2
out8(PIC_INIT3_IR2_IS_SLAVE, PIC_MASTER_INIT3);
out8(PIC_INIT3_SLAVE_ID2, PIC_SLAVE_INIT3);
// Set both to operate in 8086 mode
out8(PIC_INIT4_x86_MODE, PIC_MASTER_INIT4);
out8(PIC_INIT4_x86_MODE, PIC_SLAVE_INIT4);
out8(0xfb, PIC_MASTER_MASK); // Mask off all interrupts (except slave pic line IRQ 2).
out8(0xff, PIC_SLAVE_MASK); // Mask off interrupts on the slave.
// determine which interrupts are level or edge triggered
#if 0
// should set everything possible to level triggered
out8(0xf8, PIC_MASTER_TRIGGER_MODE);
out8(0xde, PIC_SLAVE_TRIGGER_MODE);
#endif
sLevelTriggeredInterrupts = in8(PIC_MASTER_TRIGGER_MODE)
| (in8(PIC_SLAVE_TRIGGER_MODE) << 8);
TRACE(("PIC level trigger mode: 0x%08lx\n", sLevelTriggeredInterrupts));
// make the pic controller the current one
arch_int_set_interrupt_controller(picController);
}
static status_t
pci_mech1_read_config(void *cookie, uint8 bus, uint8 device, uint8 function,
uint8 offset, uint8 size, uint32 *value)
{
cpu_status cpu;
status_t status = B_OK;
PCI_LOCK_CONFIG(cpu);
out32(PCI_MECH1_REQ_DATA(bus, device, function, offset), PCI_MECH1_REQ_PORT);
switch (size) {
case 1:
*value = in8(PCI_MECH1_DATA_PORT + (offset & 3));
break;
case 2:
*value = in16(PCI_MECH1_DATA_PORT + (offset & 3));
break;
case 4:
*value = in32(PCI_MECH1_DATA_PORT);
break;
default:
status = B_ERROR;
break;
}
PCI_UNLOCK_CONFIG(cpu);
return status;
}
static status_t
pci_mech2_read_config(void *cookie, uint8 bus, uint8 device, uint8 function,
uint8 offset, uint8 size, uint32 *value)
{
cpu_status cpu;
status_t status = B_OK;
PCI_LOCK_CONFIG(cpu);
out8((uint8)(0xf0 | (function << 1)), PCI_MECH2_ENABLE_PORT);
out8(bus, PCI_MECH2_FORWARD_PORT);
switch (size) {
case 1:
*value = in8(PCI_MECH2_CONFIG_PORT(device, offset));
break;
case 2:
*value = in16(PCI_MECH2_CONFIG_PORT(device, offset));
break;
case 4:
*value = in32(PCI_MECH2_CONFIG_PORT(device, offset));
break;
default:
status = B_ERROR;
break;
}
out8(0, PCI_MECH2_ENABLE_PORT);
PCI_UNLOCK_CONFIG(cpu);
return status;
}
/*
* uart_data_send_u8()
*/
void uart_data_send_u8(void *srv, u8_t ch)
{
isr_disable();
debug_set_lights(0x05);
isr_spinlock_lock(&data_isr_lock);
while (!(in8(USR) & BV(UDRE))) {
out8(UCR, in8(UCR) | BV(UDRIE));
isr_context_wait(&data_isr_lock);
}
out8(UDR, ch);
isr_spinlock_unlock(&data_isr_lock);
isr_enable();
}
static void
pic_enable_io_interrupt(int32 num)
{
// interrupt is specified "normalized"
if (num < 0 || num > PIC_NUM_INTS)
return;
// enable PIC 8259 controlled interrupt
TRACE(("pic_enable_io_interrupt: irq %ld\n", num));
if (num < PIC_SLAVE_INT_BASE)
out8(in8(PIC_MASTER_MASK) & ~(1 << num), PIC_MASTER_MASK);
else
out8(in8(PIC_SLAVE_MASK) & ~(1 << (num - PIC_SLAVE_INT_BASE)), PIC_SLAVE_MASK);
}
static int mc146818_read8(int reg)
{
#ifdef CONFIG_SYS_RTC_REG_BASE_ADDR
return in8(CONFIG_SYS_RTC_REG_BASE_ADDR + reg);
#else
int ofs = 0;
if (reg >= 128) {
ofs = 2;
reg -= 128;
}
out8(RTC_PORT_MC146818 + ofs, reg);
return in8(RTC_PORT_MC146818 + ofs + 1);
#endif
}
static int finish_dma(void *cookie)
{
pci_bus_cookie *bus_cookie = cookie;
uint8 status;
TRACE(("waiting for DMA to finish\n"));
out8( BM_CR_MASK_STOP,bus_cookie->io_port + BM_COMMAND_REG); // disable dma_channel
status = read_register( cookie,CB_STAT );
TRACE(("first status = %d\n",status));
if ( status & ( CB_STAT_BSY | CB_STAT_DF | CB_STAT_DRQ | CB_STAT_ERR ) )
return -1;
status = in8( bus_cookie->io_port + BM_STATUS_REG );
TRACE(("second status = %d %d\n",status,status & BM_SR_MASK_INT));
TRACE(("pci_ide will copy %d bytes\n",bus_cookie->current_dma_length));
bcopy(bus_cookie->mapped_address,bus_cookie->current_dma,bus_cookie->current_dma_length);
switch(status & 0x5) {
case 0:
TRACE(("IDE -- finish_dma: DMA transfer failed\n"));
return -1;
case 1:
TRACE(("IDE -- finish_dma: DMA transfer aborted\n"));
return -1;
case 4:
return 0;
case 5:
TRACE(("IDE -- finish_dma: PRD size > device transfer size!\n"));
return -1;
}
return 0;
}
u_char
esp_read_reg(struct ncr53c9x_softc *sc, int reg)
{
struct esp_softc *esc = (struct esp_softc *)sc;
return in8(&esc->sc_reg[reg * 16]);
}
static int kbd_read(int reg)
{
if (!kbd_output_full())
return -1;
return in8(reg);
}
static u_char ndfc_read_byte(struct mtd_info *mtdinfo)
{
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
return (in8(base + NDFC_DATA));
}
