void init_HW(void)
{
#if defined(USE_PLL) && USE_PLL
setup_flash(6);
init_clocks(true);
setup_flash(5); // 100 MHz
#else
init_clocks(false);
setup_flash(0);
#endif
}
int qemu_init_main_loop(Error **errp)
{
int ret;
GSource *src;
Error *local_error = NULL;
init_clocks(qemu_timer_notify_cb);
ret = qemu_signal_init(errp);
if (ret) {
return ret;
}
qemu_aio_context = aio_context_new(&local_error);
if (!qemu_aio_context) {
error_propagate(errp, local_error);
return -EMFILE;
}
qemu_notify_bh = qemu_bh_new(notify_event_cb, NULL);
gpollfds = g_array_new(FALSE, FALSE, sizeof(GPollFD));
src = aio_get_g_source(qemu_aio_context);
g_source_set_name(src, "aio-context");
g_source_attach(src, NULL);
g_source_unref(src);
src = iohandler_get_g_source();
g_source_set_name(src, "io-handler");
g_source_attach(src, NULL);
g_source_unref(src);
return 0;
}
int qemu_init_main_loop(void)
{
init_clocks();
init_timer_alarm(1);
qemu_clock_enable(vm_clock, false);
return main_loop_init();
}
int main(int argc, char **argv)
{
GSource *src;
init_clocks();
ctx = aio_context_new();
src = aio_get_g_source(ctx);
g_source_attach(src, NULL);
g_source_unref(src);
do {} while (g_main_context_iteration(NULL, false));
/* tests in the same order as the header function declarations */
g_test_init(&argc, &argv, NULL);
g_test_add_func("/throttle/leak_bucket", test_leak_bucket);
g_test_add_func("/throttle/compute_wait", test_compute_wait);
g_test_add_func("/throttle/init", test_init);
g_test_add_func("/throttle/destroy", test_destroy);
g_test_add_func("/throttle/have_timer", test_have_timer);
g_test_add_func("/throttle/detach_attach", test_detach_attach);
g_test_add_func("/throttle/config/enabled", test_enabled);
g_test_add_func("/throttle/config/conflicting", test_conflicting_config);
g_test_add_func("/throttle/config/is_valid", test_is_valid);
g_test_add_func("/throttle/config_functions", test_config_functions);
g_test_add_func("/throttle/accounting", test_accounting);
return g_test_run();
}
extern void start_kernel(void)
{
// char *ptr = 0x2000001;
init_memory();
init_page();
init_sched();
init_tasks();
init_itc();
init_clocks();
spark_registerSysCallHandler(&system_call, 0x90);
//spark_print(" ========== Guest 1 :: STARTED\n");
while(1) {
int i,j,k, dummy =0;
for (k=0; k< 5; k++)
{
for( i = 0 ; i < 10000; i++) {
for(j = 0 ; j < 1000; j++) {
// dummy += 5;
// if(dummy > 500)
// dummy = 0;
}
}
}
}
}
void init_HW(void)
{
// RCC system reset(for debug purpose)
// Set HSION bit
RCC->CR |= RCC_CR_HSION;
// Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits
#ifndef STM32F10X_CL
RCC->CFGR &= (uint32_t)0xF8FF0000;
#else
RCC->CFGR &= (uint32_t)0xF0FF0000;
#endif
// Reset HSEON, CSSON and PLLON bits
RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
// Reset HSEBYP bit
RCC->CR &= ~RCC_CR_HSEBYP;
// Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits
RCC->CFGR &= (uint32_t)0xFF80FFFF;
#ifdef STM32F10X_CL
// Reset PLL2ON and PLL3ON bits
RCC->CR &= (uint32_t)0xEBFFFFFF;
// Disable all interrupts and clear pending bits
RCC->CIR = 0x00FF0000;
// Reset CFGR2 register
RCC->CFGR2 = 0x00000000;
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)
// Disable all interrupts and clear pending bits
RCC->CIR = 0x009F0000;
// Reset CFGR2 register
RCC->CFGR2 = 0x00000000;
#else
// Disable all interrupts and clear pending bits
RCC->CIR = 0x009F0000;
#endif
init_clocks();
// enable IOPx periph
RCC->APB2ENR |=
RCC_APB2ENR_IOPAEN |
RCC_APB2ENR_IOPBEN |
RCC_APB2ENR_IOPCEN |
RCC_APB2ENR_IOPDEN |
#ifdef RCC_APB2ENR_IOPEEN
RCC_APB2ENR_IOPEEN |
#endif
RCC_APB2ENR_AFIOEN;
// NVIC_SetPriorityGrouping(7); // no preemption, 4 bit of subprio
NVIC_SetPriorityGrouping(6); // 1 bit preemption, 3 bit of subprio
// NVIC_SetPriorityGrouping(5); // 2 bit preemption, 2 bit of subprio
// NVIC_SetPriorityGrouping(4); // 3 bit preemption, 1 bit of subprio
// NVIC_SetPriorityGrouping(3); // 4 bit preemption, 0 bit of subprio
}
void Rx_irq_handler(void *arg)
{
init_clocks();
GPIO_CLK_INIT(USARTx_RX_GPIO_CLK, ENABLE);
USARTx_CLK_INIT(USARTx_CLK, ENABLE);
RCC_AHB1PeriphClockCmd(DMA_CLK_INIT,ENABLE);
gpio_irq_disable(USARTx_RX_GPIO_PORT, USARTx_IRQ_PIN);
mico_mcu_powersave_config(mxDisable);
mico_rtos_set_semaphore(&wakeup);
}
int main(int argc, char **argv)
{
init_clocks();
do {} while (g_main_context_iteration(NULL, false));
/* tests in the same order as the header function declarations */
g_test_init(&argc, &argv, NULL);
g_test_add_func("/throttle/leak_bucket", test_leak_bucket);
g_test_add_func("/throttle/compute_wait", test_compute_wait);
g_test_add_func("/throttle/init", test_init);
g_test_add_func("/throttle/destroy", test_destroy);
g_test_add_func("/throttle/have_timer", test_have_timer);
g_test_add_func("/throttle/config/enabled", test_enabled);
g_test_add_func("/throttle/config/conflicting", test_conflicting_config);
g_test_add_func("/throttle/config/is_valid", test_is_valid);
g_test_add_func("/throttle/config_functions", test_config_functions);
g_test_add_func("/throttle/accounting", test_accounting);
return g_test_run();
}
int qemu_init_main_loop(void)
{
int ret;
GSource *src;
init_clocks();
ret = qemu_signal_init();
if (ret) {
return ret;
}
gpollfds = g_array_new(FALSE, FALSE, sizeof(GPollFD));
qemu_aio_context = aio_context_new();
src = aio_get_g_source(qemu_aio_context);
g_source_attach(src, NULL);
g_source_unref(src);
return 0;
}
int __low_level_init( void )
{
extern void init_clocks(void);
extern void init_memory(void);
/* IAR allows init functions in __low_level_init(), but it is run before global
* variables have been initialised, so the following init still needs to be done
* When using GCC, this is done in crt0_GCC.c
*/
/* Setup the interrupt vectors address */
SCB->VTOR = (unsigned long )__section_begin(".intvec");
/* Enable CPU Cycle counting */
DWT->CYCCNT = 0;
DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
init_clocks();
init_memory();
return 1; /* return 1 to force memory init */
}
int main(void)
{
//mico_logic_partition_t *partition;
init_clocks();
init_memory();
init_architecture();
init_platform_bootloader();
mico_set_bootload_ver();
//update();
enable_protection();
#ifdef MICO_ENABLE_STDIO_TO_BOOT
if (stdio_break_in() == 1)
goto BOOT;
#endif
if( MicoShouldEnterBootloader() == false )
bootloader_start_app( (MicoFlashGetInfo(MICO_PARTITION_APPLICATION))->partition_start_addr );
/*else if( MicoShouldEnterMFGMode() == true )
bootloader_start_app( (MicoFlashGetInfo(MICO_PARTITION_APPLICATION))->partition_start_addr );
else if( MicoShouldEnterATEMode() ){
partition = MicoFlashGetInfo( MICO_PARTITION_ATE );
if (partition->partition_owner != MICO_FLASH_NONE) {
bootloader_start_app( partition->partition_start_addr );
}
}*/
#ifdef MICO_ENABLE_STDIO_TO_BOOT
BOOT:
#endif
_mount();
printf ( menu, MODEL, Bootloader_REVISION, HARDWARE_REVISION );
while(1){
Main_Menu ();
}
}
int main(void)
{
/* Call board init functions */
Board_initGeneral();
Board_initGPIO();
Board_initUART();
init_clocks();
init_lcd();
init_adc();
/* Turn on user LED */
//GPIO_write(Board_LED0, Board_LED_ON);
//GPIO_write(Board_LED1, Board_LED_ON);
System_flush();
/* Start BIOS */
BIOS_start();
return (0);
}
/* device. */
int __low_level_init( void )
{
extern void init_clocks(void);
extern void init_memory(void);
/* IAR allows init functions in __low_level_init(), but it is run before global
* variables have been initialised, so the following init still needs to be done
* When using GCC, this is done in crt0_GCC.c
*/
#ifdef BOOTLOADER
/* Set the Vector Table base location at 0x20000000 */
*SCB_VTOR_ADDRESS = 0x20000000;
#else
/* Setup the interrupt vectors address */
*SCB_VTOR_ADDRESS = (unsigned long)&Image$$ER_IROM1$$Base;
init_clocks();
init_memory();
#endif
return 1; /* return 1 to force memory init */
}
int qemu_init_main_loop(void)
{
int ret;
GSource *src;
init_clocks();
if (init_timer_alarm() < 0) {
fprintf(stderr, "could not initialize alarm timer\n");
exit(1);
}
ret = qemu_signal_init();
if (ret) {
return ret;
}
qemu_aio_context = aio_context_new();
src = aio_get_g_source(qemu_aio_context);
g_source_attach(src, NULL);
g_source_unref(src);
return 0;
}
int qemu_init_main_loop(Error **errp)
{
int ret;
GSource *src;
Error *local_error = NULL;
init_clocks();
ret = qemu_signal_init();
if (ret) {
return ret;
}
qemu_aio_context = aio_context_new(&local_error);
if (!qemu_aio_context) {
error_propagate(errp, local_error);
return -EMFILE;
}
gpollfds = g_array_new(FALSE, FALSE, sizeof(GPollFD));
src = aio_get_g_source(qemu_aio_context);
g_source_attach(src, NULL);
g_source_unref(src);
return 0;
}
void init() {
init_clocks();
init_modules();
init_interrupts();
tcs_init();
}
static void __attribute__((constructor)) init_main_loop(void)
{
init_clocks();
init_timer_alarm();
qemu_clock_enable(vm_clock, false);
}
/*
* u_int initarm(...)
*
* Initial entry point on startup. This gets called before main() is
* entered.
* It should be responsible for setting up everything that must be
* in place when main is called.
* This includes
* Taking a copy of the boot configuration structure.
* Initialising the physical console so characters can be printed.
* Setting up page tables for the kernel
* Relocating the kernel to the bottom of physical memory
*/
u_int
initarm(void *arg)
{
/*
* When we enter here, we are using a temporary first level
* translation table with section entries in it to cover the TIPB
* peripherals and SDRAM. The temporary first level translation table
* is at the end of SDRAM.
*/
/* Heads up ... Setup the CPU / MMU / TLB functions. */
if (set_cpufuncs())
panic("cpu not recognized!");
init_clocks();
/* The console is going to try to map things. Give pmap a devmap. */
pmap_devmap_register(devmap);
consinit();
#ifdef KGDB
kgdb_port_init();
#endif
#ifdef VERBOSE_INIT_ARM
/* Talk to the user */
printf("\nNetBSD/evbarm (OSK5912) booting ...\n");
#endif
#ifdef BOOT_ARGS
char mi_bootargs[] = BOOT_ARGS;
parse_mi_bootargs(mi_bootargs);
#endif
#ifdef VERBOSE_INIT_ARM
printf("initarm: Configuring system ...\n");
#endif
/*
* Set up the variables that define the availability of physical
* memory.
*/
physical_start = KERNEL_BASE_PHYS;
physical_end = physical_start + MEMSIZE_BYTES;
physmem = MEMSIZE_BYTES / PAGE_SIZE;
/* Fake bootconfig structure for the benefit of pmap.c. */
bootconfig.dramblocks = 1;
bootconfig.dram[0].address = physical_start;
bootconfig.dram[0].pages = physmem;
/*
* Our kernel is at the beginning of memory, so set our free space to
* all the memory after the kernel.
*/
physical_freestart = KERN_VTOPHYS(round_page((vaddr_t) _end));
physical_freeend = physical_end;
free_pages = (physical_freeend - physical_freestart) / PAGE_SIZE;
/*
* This is going to do all the hard work of setting up the first and
* and second level page tables. Pages of memory will be allocated
* and mapped for other structures that are required for system
* operation. When it returns, physical_freestart and free_pages will
* have been updated to reflect the allocations that were made. In
* addition, kernel_l1pt, kernel_pt_table[], systempage, irqstack,
* abtstack, undstack, kernelstack, msgbufphys will be set to point to
* the memory that was allocated for them.
*/
setup_real_page_tables();
/*
* Moved from cpu_startup() as data_abort_handler() references
* this during uvm init.
*/
proc0paddr = (struct user *)kernelstack.pv_va;
lwp0.l_addr = proc0paddr;
#ifdef VERBOSE_INIT_ARM
printf("bootstrap done.\n");
#endif
arm32_vector_init(ARM_VECTORS_LOW, ARM_VEC_ALL);
/*
* Pages were allocated during the secondary bootstrap for the
* stacks for different CPU modes.
* We must now set the r13 registers in the different CPU modes to
* point to these stacks.
* Since the ARM stacks use STMFD etc. we must set r13 to the top end
* of the stack memory.
*/
#ifdef VERBOSE_INIT_ARM
printf("init subsystems: stacks ");
#endif
set_stackptr(PSR_IRQ32_MODE, irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE);
set_stackptr(PSR_ABT32_MODE, abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE);
set_stackptr(PSR_UND32_MODE, undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE);
/*
* Well we should set a data abort handler.
* Once things get going this will change as we will need a proper
* handler.
* Until then we will use a handler that just panics but tells us
* why.
* Initialisation of the vectors will just panic on a data abort.
* This just fills in a slightly better one.
*/
#ifdef VERBOSE_INIT_ARM
printf("vectors ");
#endif
data_abort_handler_address = (u_int)data_abort_handler;
prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
undefined_handler_address = (u_int)undefinedinstruction_bounce;
/* Initialise the undefined instruction handlers */
#ifdef VERBOSE_INIT_ARM
printf("undefined ");
#endif
undefined_init();
/* Load memory into UVM. */
#ifdef VERBOSE_INIT_ARM
printf("page ");
#endif
uvm_setpagesize(); /* initialize PAGE_SIZE-dependent variables */
uvm_page_physload(atop(physical_freestart), atop(physical_freeend),
atop(physical_freestart), atop(physical_freeend),
VM_FREELIST_DEFAULT);
/* Boot strap pmap telling it where the kernel page table is */
#ifdef VERBOSE_INIT_ARM
printf("pmap ");
#endif
pmap_bootstrap(KERNEL_VM_BASE, KERNEL_VM_BASE + KERNEL_VM_SIZE);
#ifdef VERBOSE_INIT_ARM
printf("done.\n");
#endif
#ifdef KGDB
if (boothowto & RB_KDB) {
kgdb_debug_init = 1;
kgdb_connect(1);
}
#endif
#ifdef DDB
db_machine_init();
/* Firmware doesn't load symbols. */
ddb_init(0, NULL, NULL);
if (boothowto & RB_KDB)
Debugger();
#endif
/* We return the new stack pointer address */
return(kernelstack.pv_va + USPACE_SVC_STACK_TOP);
}
static unsigned long wait_mode_power_down_hook( unsigned long delay_ms )
{
bool jtag_enabled = ( ( CoreDebug ->DHCSR & CoreDebug_DEMCR_TRCENA_Msk ) != 0 ) ? true : false;
bool jtag_delay_elapsed = ( mico_get_time() > JTAG_DEBUG_SLEEP_DELAY_MS ) ? true : false;
uint32_t elapsed_cycles = 0;
/* Criteria to enter WAIT mode
* 1. Clock needed counter is 0 and no JTAG debugging
* 2. Clock needed counter is 0, in JTAG debugging session, and MiCO system tick has progressed over 3 seconds.
* This is to give OpenOCD enough time to poke the JTAG tap before the CPU enters WAIT mode.
*/
if ( ( samg5x_clock_needed_counter == 0 ) && ( ( jtag_enabled == false ) || ( ( jtag_enabled == true ) && ( jtag_delay_elapsed == true ) ) ) )
{
uint32_t total_sleep_cycles;
uint32_t total_delay_cycles;
/* Start real-time timer */
rtt_init( RTT, RTT_CLOCK_PRESCALER );
/* Start atomic operation */
DISABLE_INTERRUPTS;
/* Ensure deep sleep bit is enabled, otherwise system doesn't go into deep sleep */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
/* Disable SysTick */
SysTick->CTRL &= ( ~( SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk ) );
/* End atomic operation */
ENABLE_INTERRUPTS;
/* Expected total time CPU executing in this function (including WAIT mode time) */
total_sleep_cycles = MS_TO_CYCLES( delay_ms );
/* Total cycles in WAIT mode loop */
total_delay_cycles = ( total_sleep_cycles / RTT_MAX_CYCLES + 1 ) * RC_OSC_DELAY_CYCLES + WAIT_MODE_ENTER_DELAY_CYCLES + WAIT_MODE_EXIT_DELAY_CYCLES;
if ( total_sleep_cycles > total_delay_cycles )
{
/* Adjust total sleep cycle to exclude exit delay */
total_sleep_cycles -= WAIT_MODE_EXIT_DELAY_CYCLES;
/* Prepare platform specific settings before entering powersave */
// platform_enter_powersave();
///* Prepare WLAN bus before entering powersave */
//platform_bus_enter_powersave();
/* Disable brownout detector */
supc_disable_brownout_detector( SUPC );
/* Backup system I/0 functions and set all to GPIO to save power */
system_io_backup_value = matrix_get_system_io();
matrix_set_system_io( 0x0CF0 );
/* Switch Master Clock to Main Clock (internal fast RC oscillator) */
pmc_switch_mck_to_mainck( PMC_PCK_PRES_CLK_1 );
/* Switch on internal fast RC oscillator, switch Main Clock source to internal fast RC oscillator and disables external fast crystal */
pmc_switch_mainck_to_fastrc( CKGR_MOR_MOSCRCF_8_MHz );
/* Disable external fast crystal */
pmc_osc_disable_xtal( 0 );
/* Disable PLLA */
pmc_disable_pllack( );
/* This above process introduces certain delay. Add delay to the elapsed cycles */
elapsed_cycles += rtt_read_timer_value( RTT );
while ( wake_up_interrupt_triggered == false && elapsed_cycles < total_sleep_cycles )
{
uint32_t current_sleep_cycles = total_sleep_cycles - elapsed_cycles;
/* Start real-time timer and alarm */
rtt_init( RTT, RTT_CLOCK_PRESCALER );
rtt_write_alarm_time( RTT, ( current_sleep_cycles > RTT_MAX_CYCLES ) ? RTT_MAX_CYCLES - RC_OSC_DELAY_CYCLES : current_sleep_cycles - RC_OSC_DELAY_CYCLES );
__asm("wfi");
/* Enter WAIT mode */
//pmc_enable_waitmode();
/* Clear wake-up status */
rtt_get_status( RTT );
/* Add sleep time to the elapsed cycles */
elapsed_cycles += rtt_read_timer_value( RTT );
}
/* Re-enable real-time timer to time clock reinitialisation delay */
rtt_init( RTT, RTT_CLOCK_PRESCALER );
/* Reinit fast clock. This takes ~19ms, but the timing has been compensated */
init_clocks();
/* Disable unused clock to save power */
pmc_osc_disable_fastrc();
/* Restore system I/O pins */
matrix_set_system_io( system_io_backup_value );
/* Restore WLAN bus */
//platform_bus_exit_powersave();
// /* Restore platform-specific settings */
// platform_exit_powersave();
/* Add clock reinitialisation delay to elapsed cycles */
elapsed_cycles += rtt_read_timer_value( RTT );
/* Disable RTT to save power */
RTT->RTT_MR = (uint32_t)( 1 << 20 );
}
}
/* Start atomic operation */
DISABLE_INTERRUPTS;
/* Switch SysTick back on */
SysTick->CTRL |= ( SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk );
/* Clear flag indicating interrupt triggered by wake up pin */
wake_up_interrupt_triggered = false;
/* End atomic operation */
ENABLE_INTERRUPTS;
/* Return total time in milliseconds */
return CYCLES_TO_MS( elapsed_cycles );
}
static unsigned long stop_mode_power_down_hook( unsigned long sleep_ms )
{
unsigned long retval;
unsigned long wut_ticks_passed;
unsigned long scale_factor = 0;
UNUSED_PARAMETER(sleep_ms);
UNUSED_PARAMETER(rtc_timeout_start_time);
UNUSED_PARAMETER(scale_factor);
if ( ( ( SCB->SCR & (unsigned long)SCB_SCR_SLEEPDEEP_Msk) != 0) && sleep_ms < 5 ){
SCB->SCR &= (~((unsigned long)SCB_SCR_SLEEPDEEP_Msk));
__asm("wfi");
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
/* Note: We return 0 ticks passed because system tick is still going when wfi instruction gets executed */
ENABLE_INTERRUPTS;
return 0;
}
if ( ( ( SCB->SCR & (unsigned long)SCB_SCR_SLEEPDEEP_Msk) ) != 0 )
{
/* pick up the appropriate prescaler for a requested delay */
select_wut_prescaler_calculate_wakeup_time(&rtc_timeout_start_time, sleep_ms, &scale_factor );
DISABLE_INTERRUPTS;
SysTick->CTRL &= (~(SysTick_CTRL_TICKINT_Msk|SysTick_CTRL_ENABLE_Msk)); /* systick IRQ off */
RTC_ITConfig(RTC_IT_WUT, ENABLE);
EXTI_ClearITPendingBit( RTC_INTERRUPT_EXTI_LINE );
PWR_ClearFlag(PWR_FLAG_WU);
RTC_ClearFlag(RTC_FLAG_WUTF);
RTC_SetWakeUpCounter( rtc_timeout_start_time );
RTC_WakeUpCmd( ENABLE );
platform_rtc_enter_powersave();
DBGMCU->CR |= 0x03; /* Enable debug in stop mode */
/* This code will be running with BASEPRI register value set to 0, the main intention behind that is that */
/* all interrupts must be allowed to wake the CPU from the power-down mode */
/* the PRIMASK is set to 1( see DISABLE_INTERRUPTS), thus we disable all interrupts before entering the power-down mode */
/* This may sound contradictory, however according to the ARM CM3 documentation power-management unit */
/* takes into account only the contents of the BASEPRI register and it is an external from the CPU core unit */
/* PRIMASK register value doesn't affect its operation. */
/* So, if the interrupt has been triggered just before the wfi instruction */
/* it remains pending and wfi instruction will be treated as a nop */
__asm("wfi");
/* After CPU exits powerdown mode, the processer will not execute the interrupt handler(PRIMASK is set to 1) */
/* Disable rtc for now */
RTC_WakeUpCmd( DISABLE );
RTC_ITConfig(RTC_IT_WUT, DISABLE);
/* Initialise the clocks again */
init_clocks( );
/* Enable CPU ticks */
SysTick->CTRL |= (SysTick_CTRL_TICKINT_Msk|SysTick_CTRL_ENABLE_Msk);
/* Get the time of how long the sleep lasted */
wut_ticks_passed = rtc_timeout_start_time - RTC_GetWakeUpCounter();
UNUSED_VARIABLE(wut_ticks_passed);
platform_rtc_exit_powersave( sleep_ms, (uint32_t *)&retval );
/* as soon as interrupts are enabled, we will go and execute the interrupt handler */
/* which triggered a wake up event */
ENABLE_INTERRUPTS;
wake_up_interrupt_triggered = false;
UNUSED_VARIABLE(wake_up_interrupt_triggered);
return retval;
}
else
{
UNUSED_PARAMETER(wut_ticks_passed);
ENABLE_INTERRUPTS;
__asm("wfi");
/* Note: We return 0 ticks passed because system tick is still going when wfi instruction gets executed */
return 0;
}
}
int qemu_init_main_loop(void)
{
init_clocks();
init_timer_alarm();
return main_loop_init();
}
/*
* Application's entry point dynamic schedule. Main is somewhat too large because of the MQTT stuff
* allmighty whileloop
*/
int main(int argc, char** argv)
{
/* Stop WDT and initialize lcd, clcks, main interfaces */
stopWDT();
init_clocks(); //init clock for LCD
init_lcd();
initClk(); //init clock for wifi
Delay(5);
init_main();
Delay(5);
load_data();
int rc = 0;
unsigned char buf[100];
unsigned char readbuf[100];
NewNetwork(&n);
rc = ConnectNetwork(&n, MQTT_BROKER_SERVER, 1883);
if (rc != 0) {
CLI_Write(" Failed to connect to MQTT broker \n\r");
}
MQTTClient(&hMQTTClient, &n, 1000, buf, 100, readbuf, 100);
MQTTPacket_connectData cdata = MQTTPacket_connectData_initializer;
cdata.MQTTVersion = 3;
cdata.clientID.cstring = "daniel";
rc = MQTTConnect(&hMQTTClient, &cdata);
if (rc != 0) {
CLI_Write(" Failed to start MQTT client \n\r");
//LOOP_FOREVER();
}
rc = MQTTSubscribe(&hMQTTClient, SUBSCRIBE_TOPIC, QOS0, messageArrived);
if (rc != 0) {
CLI_Write(" Failed to subscribe to /msp/cc3100/demo topic \n\r");
//LOOP_FOREVER();
}
MQTTYield(&hMQTTClient, 10);
int8_t buffer[2] = "on";
MQTTMessage msg;
msg.dup = 0;
msg.id = 0;
msg.payload = buffer;
msg.payloadlen = 8;
msg.qos = QOS0;
msg.retained = 0;
MQTTPublish(&hMQTTClient, PUBLISH_TOPIC, &msg);
Delay(20);
backlight_off();
while(1) {
MQTTYield(&hMQTTClient, 10);
debounce++;
if(send_goal_bool) {
int8_t buffer2[15] = " ";
sprintf(buffer2, "%d", goal_steps);
msg;
msg.dup = 0;
msg.id = 0;
msg.payload = buffer2;
msg.payloadlen = 15;
msg.qos = QOS0;
msg.retained = 0;
MQTTPublish(&hMQTTClient, PUBLISH_TOPIC, &msg);
Delay(20);
send_goal_bool = 0;
}else if(send_on_bool) {
int8_t buffer2[2] = "on";
msg;
msg.dup = 0;
msg.id = 0;
msg.payload = buffer2;
msg.payloadlen = 2;
msg.qos = QOS0;
msg.retained = 0;
MQTTPublish(&hMQTTClient, PUBLISH_TOPIC, &msg);
Delay(20);
send_on_bool = 0;
} else if( (P3IN & BIT5) == 0 && debounce > 20) {
debounce = 0;
menu_select();
} else if ( (P1IN & BIT4) == 0 && debounce > 10) {
debounce = 0;
menu();
} else if ( steps_taken >= goal_steps && active_bool == 1 ) {
P1OUT &= ~BIT0;
int8_t buffer2[1] = "g";
msg;
msg.dup = 0;
msg.id = 0;
msg.payload = buffer2;
msg.payloadlen = 1;
msg.qos = QOS0;
msg.retained = 0;
MQTTPublish(&hMQTTClient, "on", &msg);
Delay(20);
MAP_Interrupt_disableInterrupt(INT_ADC14);
active_bool = 0;
view_goal_menu();
}
}
}
//-------------------------------
// main function
int main(void) {
//u32 del;
// turn on execution counter
// default .crt does this for us
// __asm__ __volatile__("R0 = 0x32; SYSCFG = R0; CSYNC;":::"R0");
// initialize clocks and power
init_clocks();
// configure programmable flags
init_flags();
READY_LO;
// intialize the sdram controller
init_EBIU();
// intialize the flash controller (which, weirdly, handles gpio)
// init_flash();
/// initialize the CV dac (reset)
init_cv();
// intialize the sport0 for audio rx/tx
init_sport0();
// intialize the sport1 for cv out
init_sport1();
// intialize DMA for audio
init_DMA();
// // put the spi back in slave mode to receive param changes from avr32
init_spi_slave();
// intialize the audio processing unit (assign memory)
module_init();
// assign interrupts
init_interrupts();
// begin audio transfers
enable_DMA_sport0();
// begin cv transfers
enable_DMA_sport1();
// initialize the codec
init_1939();
// leds on
LED3_HI;
LED4_HI;
// signal the ready flag
READY_HI;
while(1) {
// fixme: everything happens in ISRs!
// ;;
/*
//// TODO / FIXME:
update a param change FIFO here?
for now, the answer is no:
instead, we are asking avr32 to hold off sending params
for as long as the ready-pin is deasserted by frame or control change processing.
*/
/// while frame processing
// ctl_next_frame();
// ctl_perform_last_change();
}
}
//====================================
static int rtc_standby( lua_State* L )
{
char buff[60];
uint8_t mode = luaL_checkinteger( L, 1 );
if (mode > 1) {
l_message( NULL, "mode has to be 0 or 1" );
return 0;
}
if (mode==1 && use_wwdg == 0) {
l_message(NULL,"IWDG active, cannot enter STOP mode.");
return 0;
}
int nsec = luaL_checkinteger( L, 2 );
if ((nsec < 1) || (nsec > 84559)) {
l_message(NULL,"wrong interval (1~84599)");
return 0;
}
TM_RTC_DisableAlarm(TM_RTC_Alarm_A);
TM_RTC_DisableAlarm(TM_RTC_Alarm_B);
platform_rtc_time_t time;
uint32_t currentSecond;
RTC_AlarmTypeDef RTC_AlarmStructure;
platform_rtc_get_time(&time);
currentSecond = time.hr*3600 + time.min*60 + time.sec;
currentSecond += nsec;
RTC_AlarmStructure.RTC_AlarmTime.RTC_H12 = RTC_HourFormat_24;
RTC_AlarmStructure.RTC_AlarmTime.RTC_Hours = currentSecond/3600%24;
RTC_AlarmStructure.RTC_AlarmTime.RTC_Minutes = currentSecond/60%60;
RTC_AlarmStructure.RTC_AlarmTime.RTC_Seconds = currentSecond%60;
RTC_AlarmStructure.RTC_AlarmDateWeekDay = 0x31;
RTC_AlarmStructure.RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date;
RTC_AlarmStructure.RTC_AlarmMask = RTC_AlarmMask_DateWeekDay ;
RTC_SetAlarm(RTC_Format_BIN, RTC_Alarm_A, &RTC_AlarmStructure);
// Enable RTC Alarm A Interrupt
RTC_ITConfig(RTC_IT_ALRA, ENABLE);
// Enable the Alarm A
RTC_AlarmCmd(RTC_Alarm_A, ENABLE);
/* Clear Alarm A pending bit */
/* Clear RTC Alarm Flag */
RTC_ClearFlag(RTC_FLAG_ALRAF);
RTC_ClearFlag(RTC_IT_ALRA);
if (mode == 0) sprintf(buff,"Going to STANDBY MODE...\r\n");
else if (mode == 1) sprintf(buff,"Going to STOP MODE...\r\n");
l_message(NULL,buff);
sprintf(buff,"Wake up in %d second(s)\r\n", nsec);
l_message(NULL,buff);
//mico_rtos_suspend_all_thread();
if (mode == 0) {
PWR_EnterSTANDBYMode();
// RESET
}
else if (mode == 1) {
PWR_EnterSTOPMode(PWR_Regulator_LowPower, PWR_STOPEntry_WFI);
// restore clocks
init_clocks();
}
//mico_rtos_resume_all_thread();
// *** Back from stop ***
TM_RTC_DisableAlarm(TM_RTC_Alarm_A);
TM_RTC_DisableAlarm(TM_RTC_Alarm_B);
luaWdgReload();
l_message(NULL,"Back from power save mode.");
return 0;
}
//=========================================
static int rtc_standbyUntil( lua_State* L )
{
uint8_t h,m,s;
RTC_AlarmTypeDef RTC_AlarmStructure;
char buff[64];
uint8_t mode = luaL_checkinteger( L, 1 );
if (mode > 1) {
l_message( NULL, "mode has to be 0 or 1" );
return 0;
}
if (mode==1 && use_wwdg == 0) {
l_message(NULL,"IWDG active, cannot enter STOP mode.");
return 0;
}
if (!lua_istable(L, 2)) {
l_message( NULL, "table arg needed" );
return 0;
}
if (lua_objlen( L, 2 ) != 3) {
l_message( NULL, "hour,minute,second expected" );
return 0;
}
lua_rawgeti( L, 2, 1 );
h = ( int )luaL_checkinteger( L, -1 );
lua_pop( L, 1 );
lua_rawgeti( L, 2, 2 );
m = ( int )luaL_checkinteger( L, -1 );
lua_pop( L, 1 );
lua_rawgeti( L, 2, 3 );
s = ( int )luaL_checkinteger( L, -1 );
lua_pop( L, 1 );
TM_RTC_DisableAlarm(TM_RTC_Alarm_A);
TM_RTC_DisableAlarm(TM_RTC_Alarm_B);
RTC_AlarmStructure.RTC_AlarmTime.RTC_H12 = RTC_HourFormat_24;
RTC_AlarmStructure.RTC_AlarmTime.RTC_Hours = h;
RTC_AlarmStructure.RTC_AlarmTime.RTC_Minutes = m;
RTC_AlarmStructure.RTC_AlarmTime.RTC_Seconds = s;
RTC_AlarmStructure.RTC_AlarmDateWeekDay = 0x31;
RTC_AlarmStructure.RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date;
RTC_AlarmStructure.RTC_AlarmMask = RTC_AlarmMask_DateWeekDay ;
RTC_AlarmCmd(RTC_Alarm_A, DISABLE);
/* Disable the Alarm A */
RTC_ITConfig(RTC_IT_ALRA, DISABLE);
/* Clear RTC Alarm Flag */
RTC_ClearFlag(RTC_FLAG_ALRAF);
RTC_ClearFlag(RTC_IT_ALRA);
RTC_SetAlarm(RTC_Format_BIN, RTC_Alarm_A, &RTC_AlarmStructure);
/* Enable RTC Alarm A Interrupt: this Interrupt will wake-up the system from
STANDBY mode (RTC Alarm IT not enabled in NVIC) */
RTC_ITConfig(RTC_IT_ALRA, ENABLE);
/* Enable the Alarm A */
RTC_AlarmCmd(RTC_Alarm_A, ENABLE);
if (mode == 0) sprintf(buff,"Going to STANDBY MODE...\r\n");
else if (mode == 1) sprintf(buff,"Going to STOP MODE...\r\n");
l_message(NULL,buff);
sprintf(buff,"Wake up at %02d:%02d:%02d\r\n", RTC_AlarmStructure.RTC_AlarmTime.RTC_Hours, RTC_AlarmStructure.RTC_AlarmTime.RTC_Minutes, RTC_AlarmStructure.RTC_AlarmTime.RTC_Seconds);
l_message(NULL,buff);
//mico_rtos_suspend_all_thread();
if (mode == 0) {
PWR_EnterSTANDBYMode();
}
else if (mode == 1) {
PWR_EnterSTOPMode(PWR_Regulator_LowPower, PWR_STOPEntry_WFI);
init_clocks();
}
//mico_rtos_resume_all_thread();
// *** Back from stop ***
TM_RTC_DisableAlarm(TM_RTC_Alarm_A);
TM_RTC_DisableAlarm(TM_RTC_Alarm_B);
luaWdgReload();
l_message(NULL,"Back from power save mode.");
return 0;
}
/*
* u_int initarm(...)
*
* Initial entry point on startup. This gets called before main() is
* entered.
* It should be responsible for setting up everything that must be
* in place when main is called.
* This includes
* Taking a copy of the boot configuration structure.
* Initialising the physical console so characters can be printed.
* Setting up page tables for the kernel
* Relocating the kernel to the bottom of physical memory
*/
u_int
initarm(void *arg)
{
/*
* Heads up ... Setup the CPU / MMU / TLB functions
*/
if (set_cpufuncs())
panic("cpu not recognized!");
/* map some peripheral registers */
pmap_devmap_bootstrap((vaddr_t)armreg_ttbr_read() & -L1_TABLE_SIZE,
netwalker_devmap);
cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
/* Register devmap for devices we mapped in start */
pmap_devmap_register(netwalker_devmap);
setup_ioports();
consinit();
#ifdef NO_POWERSAVE
cpu_do_powersave=0;
#endif
init_clocks();
#ifdef KGDB
kgdb_port_init();
#endif
/* Talk to the user */
printf("\nNetBSD/evbarm (" ___STRING(EVBARM_BOARDTYPE) ") booting ...\n");
#ifdef BOOT_ARGS
char mi_bootargs[] = BOOT_ARGS;
parse_mi_bootargs(mi_bootargs);
#endif
bootargs[0] = '\0';
#if defined(VERBOSE_INIT_ARM) || 1
printf("initarm: Configuring system");
printf(", CLIDR=%010o CTR=%#x",
armreg_clidr_read(), armreg_ctr_read());
printf("\n");
#endif
/*
* Ok we have the following memory map
*
* Physical Address Range Description
* ----------------------- ----------------------------------
*
* 0x90000000 - 0xAFFFFFFF DDR SDRAM (512MByte)
*
* The initarm() has the responsibility for creating the kernel
* page tables.
* It must also set up various memory pointers that are used
* by pmap etc.
*/
#ifdef VERBOSE_INIT_ARM
printf("initarm: Configuring system ...\n");
#endif
/* Fake bootconfig structure for the benefit of pmap.c */
/* XXX must make the memory description h/w independent */
bootconfig.dramblocks = 1;
bootconfig.dram[0].address = MEMSTART;
bootconfig.dram[0].pages = (MEMSIZE * 1024 * 1024) / PAGE_SIZE;
psize_t ram_size = bootconfig.dram[0].pages * PAGE_SIZE;
#ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS
if (ram_size > KERNEL_VM_BASE - KERNEL_BASE) {
printf("%s: dropping RAM size from %luMB to %uMB\n",
__func__, (unsigned long) (ram_size >> 20),
(KERNEL_VM_BASE - KERNEL_BASE) >> 20);
ram_size = KERNEL_VM_BASE - KERNEL_BASE;
}
int main(void){
uint16_t max = 0, j=0;
uint16_t temp = 0;
//Stop watchdog timer
WDTCTL = WDTPW + WDTHOLD;
// FET pins for smart load all low
smart_load_init();
// Set gain on INA225
//set_gain_low();
set_gain_high();
// LED
led_init();
// Setup clocks
init_clocks();
// Configure ADC for V_SENSE and I_SENSE
P1SEL0 |= BIT1 + BIT0;
P1SEL1 |= BIT1 + BIT0;
ADC10CTL0 &= ~ADC10ENC;
ADC10CTL0 |= ADC10ON + ADC10SHT_0;
ADC10CTL1 |= ADC10DIV_4 + ADC10SHP;
ADC10CTL2 |= ADC10RES + ADC10PDIV_0; // 10-bit results
ADC10MCTL0 = ADC10INCH_1 + REF_SELECTOR;
ADC10CTL0 |= ADC10ENC;
// By default, REFMSTR=1 => REFCTL is used to configure the internal reference
while(REFCTL0 & REFGENBUSY); // If ref generator busy, WAIT
REFCTL0 |= REFVSEL_0+REFON; // Select internal ref = 1.5V, Internal Reference ON
__delay_cycles(1000); // ref delay
// Init results
tx_buffer[0] = DEVICE_ID;
// Radio startup
Radio.Init();
Radio.SetDataRate(3); // Needs to be the same in Tx and Rx
Radio.SetLogicalChannel(0); // Needs to be the same in Tx and Rx
Radio.SetTxPower(0);
Radio.Sleep();
// Main loop
while(1) {
led_toggle();
// Get three IV curves to fill up packet
for(j=0;j<3;j++) {
smart_load();
memcpy(&tx_buffer[1+BUF_SIZE_BYTES * 2 * j], v_samples, BUF_SIZE_BYTES);
memcpy(&tx_buffer[1+BUF_SIZE_BYTES+BUF_SIZE_BYTES * 2 * j], i_samples, BUF_SIZE_BYTES);
}
// Turn on radio, for speed, don't sleep / wakeup
Radio.Wakeup();
__delay_cycles(100);
Radio.SendData(tx_buffer, TX_BUFFER_SIZE);
Radio.Sleep();
}
return 1;
}
