void hi6220_pll_init(void)
{
uint32_t data;
init_pll();
init_freq();
/*
* Init DDR with 533MHz. Otherwise, DDR initialization
* may fail on 800MHz on some boards.
*/
ddr_phy_reset();
init_ddr(0);
/* Init DDR with 800MHz. */
ddr_phy_reset();
init_ddr(1);
ddrc_common_init(1);
dienum_det_and_rowcol_cfg();
detect_ddr_chip_info();
data = mmio_read_32(0xf7032000 + 0x010);
data &= ~0x1;
mmio_write_32(0xf7032000 + 0x010, data);
data = mmio_read_32(0xf7032000 + 0x010);
/*
* Test memory access. Do not use address 0x0 because the compiler
* may assume it is not a valid address and generate incorrect code
* (GCC 4.9.1 without -fno-delete-null-pointer-checks for instance).
*/
mmio_write_32(0x4, 0xa5a55a5a);
INFO("ddr test value:0x%x\n", mmio_read_32(0x4));
init_ddrc_qos();
init_mmc0_pll();
reset_mmc0_clk();
init_media_clk();
dsb();
init_mmc1_pll();
reset_mmc1_clk();
}
void init_all(void)
{
init_uart();
init_pll();
act8600_setting();
init_ddr();
// init_lcd();
init_i2c();
// init_pwm();
}
int main()
{
int my_addr;
init_platform();
print("What's up World!\n");
/* to set up the empty allocation tree */
init_ddr();
init_ddr();
my_addr = hw_malloc(1000); //malloc
print("Allocated memory address is ");
putnum(result);
hw_mfree(my_addr);//mfree
return 0;
}
int main()
{
init_platform();
init_ddr();
print("Hello World\n\r");
int log2ListSize;
XClistnew myIP;
int list_set_up;
int i;
for(i = 0; i < 21; i++){
log2ListSize = i;
list_set_up = XClistnew_Initialize(&myIP, XPAR_CLISTNEW_0_DEVICE_ID);
list_set_up = XClistnew_IsReady(&myIP);
Xil_Out32(LIST_BASE + 0x20, log2ListSize);
// start list IP
XClistnew_Start(&myIP);
// check if list IP is done
int flag_done = 0;
flag_done = XClistnew_IsDone(&myIP);
while(flag_done != 1){
flag_done = XClistnew_IsDone(&myIP);
}
// read counter result back
putnum(Xil_In32(COUNTER_BASE + 4 * 1));
print(" ");
putnum(Xil_In32(COUNTER_BASE + 4 * 2));
print(" ");
putnum(Xil_In32(COUNTER_BASE + 4 * 3));
print("\n");
// reset counter
Xil_Out32(COUNTER_BASE + 4 * 1,RESET);
Xil_Out32(COUNTER_BASE + 4 * 2,RESET);
Xil_Out32(COUNTER_BASE + 4 * 3,RESET);
}
print("\n all done\n");
cleanup_platform();
return 0;
}
int main()
{
init_platform();
init_ddr();
print("Hello World\n\r");
/*
int l;
int addr;
print("mallocs\n");
for(l = 0; l < 1000000; l ++){
addr = hw_malloc(8);
Xil_Out32(DEBUG_BASE + 4 * l, addr);
}
putnum(addr);
print("frees\n");
for(l = 0; l < 1000000; l ++){
addr = Xil_In32(DEBUG_BASE + 4 * l);
hw_mfree(addr);
}
putnum(addr);
print("done!\n");
putnum(hw_malloc(8));
*/
XClist myIP;
int list_set_up;
list_set_up = XClist_Initialize(&myIP, XPAR_CLIST_0_DEVICE_ID);
list_set_up = XClist_IsReady(&myIP);
Xil_Out32(LIST_BASE + 0x20, 10);
// start list IP
XClist_Start(&myIP);
// check if list IP is done
int flag_done = 0;
flag_done = XClist_IsDone(&myIP);
while(flag_done != 1) {
flag_done = XClist_IsDone(&myIP);
}
// read counter result back
print("Overall ");
putnum(Xil_In32(COUNTER_BASE + 4 * 0));
print("\n");
print("Creating ");
putnum(Xil_In32(COUNTER_BASE + 4 * 1));
print("\n");
print("Reversing ");
putnum(Xil_In32(COUNTER_BASE + 4 * 2));
print("\n");
print("Destroying ");
putnum(Xil_In32(COUNTER_BASE + 4 * 3));
print("\n");
int myPtr;
myPtr = Xil_In32(LIST_BASE + 0x10);
putnum(myPtr);
// putnum(hw_malloc(8));
/*
int hdPtr;
hdPtr = Xil_In32(LIST_BASE + 0x10);
print("hdPtr = ");
putnum(hdPtr);
print("\n");
signed offset;
offset = Xil_In32(hdPtr);
print("offset = ");
putnum(offset);
print("\n");
int data;
data = Xil_In32(hdPtr + 4);
print("data = ");
putnum(data);
print("\n");
*/
//-----------
/*
hdPtr = hdPtr + offset;
print("hdPtr = ");
putnum(hdPtr);
print("\n");
offset = Xil_In32(hdPtr);
print("offset = ");
putnum(offset);
print("\n");
data = Xil_In32(hdPtr + 4);
print("data = ");
putnum(data);
print("\n");
*/
//-----------
/*
int l;
int nowPtr;
l = 0;
int i;
// while(hdPtr != 0){
for(i = 0; i <10; i++){
nowPtr = hdPtr;
offset = Xil_In32(hdPtr);
hdPtr = hdPtr + offset;
hw_mfree(nowPtr);
putnum(hdPtr);
print("\n");
}
print("finished processing\n");
putnum(hw_malloc(8));
*/
cleanup_platform();
return 0;
}
int main()
{
init_platform();
init_ddr(); // uncomment if using SysAlloc
print("Hello World\n\r");
int log2_tree_size;
/*
// Code for measuring the latency of RNG
int k;
for(k = 0; k <10; k++){
XIo_Out32(COUNTER_BASE + 4 * k, START);
RandGen(10);
XIo_Out32(COUNTER_BASE + 4 * k, STOP);
putnum(XIo_In32(COUNTER_BASE + 4 * k));
XIo_Out32(COUNTER_BASE + 4 * k,RESET);
print("\n");
}
*/
int *root = NULL;
int i,j;
//for(i = 0; i < 21; i++){
log2_tree_size = 6;
root = NULL;
xor_rng_init();
XIo_Out32(COUNTER_BASE + 4 * 1, START);
root = PM_1_INSERTION(root, log2_tree_size);
XIo_Out32(COUNTER_BASE + 4 * 1, STOP);
XIo_Out32(COUNTER_BASE + 4 * 2, START);
root = PM_2_CHECK_INSERTION(root, log2_tree_size);
XIo_Out32(COUNTER_BASE + 4 * 2, STOP);
XIo_Out32(COUNTER_BASE + 4 * 3, START);
root = PM_3_UPDATE(root, log2_tree_size);
XIo_Out32(COUNTER_BASE + 4 * 3, STOP);
XIo_Out32(COUNTER_BASE + 4 * 4, START);
root = PM_4_DELETION(root);
XIo_Out32(COUNTER_BASE + 4 * 4, STOP);
// read counter result back
for(j = 1; j<5; j++){
if(i > 17){
putnum(XIo_In32(COUNTER_BASE + 4 * (j + 8) ));
}
putnum(XIo_In32(COUNTER_BASE + 4 * j));
print(" ");
// reset counter
XIo_Out32(COUNTER_BASE + 4 * j, RESET);
}
print("\n");
//}
print("\n all done\n");
cleanup_platform();
return 0;
}
int main(void)
{
int disk;
int stage2ImageNumber;
int status;
/* remove the pending reset again */
writel(0xFFFFFFFF, GPIO_B_CLR_OE);
writel((readl(SYS_CTRL_GPIO_TERSEL_CTRL1) & ~0x4),
SYS_CTRL_GPIO_TERSEL_CTRL1);
writel((readl(SYS_CTRL_GPIO_SECSEL_CTRL1) & ~0x4),
SYS_CTRL_GPIO_SECSEL_CTRL1);
writel((readl(SYS_CTRL_GPIO_PRIMSEL_CTRL1) & ~0x4),
SYS_CTRL_GPIO_PRIMSEL_CTRL1);
ddr_control = 0;
stage2_size = 120000;
stage2ImageNumber = 0;
stage2_ram_addr = 0x48d00000;
header_length = (u32 *) (stage2_ram_addr - 8);
header_crc = (u32 *) (stage2_ram_addr - 4);
// Base the UART divider on the system clock
int baud_divisor_x16 = NOMINAL_SYSCLK / 115200;
if (readl(CONFIG_REGISTER) != readl(START_OF_ROM)) {
/* use FPGA system clock speed. */
baud_divisor_x16 = FPGA_CLK / 115200;
} else {
/* use ASIC nominal system clock. */
baud_divisor_x16 = NOMINAL_SYSCLK / 115200;
}
start_timer();
set_pll();
// Initialise the UART to be used by the CoPro for debug messages
debug_uart = (NS16550_t) UART_2_BASE;
init_NS16550(debug_uart, baud_divisor_x16);
putc_NS16550(debug_uart, 'N');
init_ddr();
putc_NS16550(debug_uart, 'A');
test_memory(stage2_ram_addr); /* sends 'S' after writing */
putc_NS16550(debug_uart, 'O');
/* no need to re-initialise SATA controller just load details. */
if ((readl(BOOT_STATUS0) == 0x01)
|| (readl(BOOT_VERSION) == 0x36303030ul)) {
disk = 0;
} else {
disk = 1;
}
do {
init_sata_hw();
status =
run_sata(stage2_disk_sector[stage2ImageNumber], stage2_size,
(u32 *) header_length, disk);
if (status == 0) {
putstr(debug_uart, "X");
} else {
putstr(debug_uart, "x");
}
if (stage2ImageNumber > 0) {
putstr(debug_uart, "R");
} else {
putstr(debug_uart, "_");
}
putc_NS16550(debug_uart, (char) ('0' + (char) disk));
/* try the backup stage2 on this disk first (first tim round, at least we know
it is working to some extent, go to next disk if this wraps round */
if (++stage2ImageNumber >= numStage2Images) {
stage2ImageNumber = 0;
if (++disk > 1) {
disk = 0;
}
}
} while (!
(status != 0 && *header_length
&& *header_length <= stage2_size
&& *header_crc == crc32(0, (unsigned char *) stage2_ram_addr,
*header_length)));
putstr(debug_uart, "800\r\n");
putstr(debug_uart, build_string);
putc_NS16550(debug_uart, '\r');
putc_NS16550(debug_uart, '\n');
#if (OVERCLOCK_PLL)
putstr(debug_uart, "Overclocking with ");
putstr(debug_uart, ultohex(OVERCLOCK_PLL));
putc_NS16550(debug_uart, ' ');
#endif // OVERCLOCK_PLL
((void (*)(void)) stage2_ram_addr) ();
return 0;
}
