static void __init ep88xc_setup_arch(void)
{
struct device_node *np;
cpm_reset();
init_ioports();
np = of_find_compatible_node(NULL, NULL, "fsl,ep88xc-bcsr");
if (!np) {
printk(KERN_CRIT "Could not find fsl,ep88xc-bcsr node\n");
return;
}
ep88xc_bcsr = of_iomap(np, 0);
of_node_put(np);
if (!ep88xc_bcsr) {
printk(KERN_CRIT "Could not remap BCSR\n");
return;
}
setbits8(&ep88xc_bcsr[7], BCSR7_SCC2_ENABLE);
setbits8(&ep88xc_bcsr[8], BCSR8_PHY1_ENABLE | BCSR8_PHY1_POWER |
BCSR8_PHY2_ENABLE | BCSR8_PHY2_POWER);
}
void kgdb_params_early_init(void)
{
mtspr(SPRN_M_TWB, virt_to_phys(tmp_sw_page));
#ifdef CONFIG_PPC_8xx
__initial_memory_limit = 0x800000;
#endif
get_from_flat_dt("cpu", "clock-frequency", &ppc_proc_freq);
get_from_flat_dt("soc", "reg", &immrbase);
get_from_flat_dt("cpm", "brg-frequency", &brgfreq);
#ifdef CONFIG_PPC_EP88XC
cpm_reset();
init_ioports();
#ifdef CONFIG_KGDB_CPM_UART_SMC1
cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX);
#endif
#ifdef CONFIG_KGDB_CPM_UART_SCC2
cpm1_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX);
cpm1_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX);
#endif
#else
/* early dpmem init */
m8xx_cpm_dpinit();
#endif
}
static void __init mpc86xads_setup_arch(void)
{
struct device_node *np;
u32 __iomem *bcsr_io;
cpm_reset();
init_ioports();
np = of_find_compatible_node(NULL, NULL, "fsl,mpc866ads-bcsr");
if (!np) {
printk(KERN_CRIT "Could not find fsl,mpc866ads-bcsr node\n");
return;
}
bcsr_io = of_iomap(np, 0);
of_node_put(np);
if (bcsr_io == NULL) {
printk(KERN_CRIT "Could not remap BCSR\n");
return;
}
clrbits32(bcsr_io, BCSR1_RS232EN_1 | BCSR1_RS232EN_2 | BCSR1_ETHEN);
iounmap(bcsr_io);
}
void kgdb_params_early_init(void)
{
if (cpm_uart_nr)
return;
get_from_flat_dt("cpu", "clock-frequency", &ppc_proc_freq);
get_from_flat_dt("cpm", "brg-frequency", &brgfreq);
get_from_flat_dt("soc", "reg", &immrbase);
#ifdef CONFIG_FSL_BOOKE
/* MMU configuration for early access to IMMR and memory */
settlbcam(num_tlbcam_entries - 1, immrbase, immrbase, 0x100000, _PAGE_IO, 0);
settlbcam(0, KERNELBASE, 0, lmb_end_of_DRAM(), _PAGE_KERNEL, 0);
#else
/* Set up BAT for early access to IMMR */
mb();
mtspr(SPRN_DBAT1L, (immrbase & 0xffff0000) | 0x2a);
mtspr(SPRN_DBAT1U, (immrbase & 0xffff0000) | BL_256M << 2 | 2);
mb();
setbat(1, immrbase, immrbase, 0x10000000, _PAGE_IO);
#endif
#ifdef CONFIG_MPC8272_ADS
/* Enable serial ports in BCSR */
clrbits32((u32 *)0xf4500000, BCSR1_RS232_EN1 | BCSR1_RS232_EN2);
#endif
cpm2_reset();
init_ioports();
}
static void __init mpc8272_ads_setup_arch(void)
{
struct device_node *np;
__be32 __iomem *bcsr;
if (ppc_md.progress)
ppc_md.progress("mpc8272_ads_setup_arch()", 0);
cpm2_reset();
np = of_find_compatible_node(NULL, NULL, "fsl,mpc8272ads-bcsr");
if (!np) {
printk(KERN_ERR "No bcsr in device tree\n");
return;
}
bcsr = of_iomap(np, 0);
of_node_put(np);
if (!bcsr) {
printk(KERN_ERR "Cannot map BCSR registers\n");
return;
}
#define BCSR1_FETHIEN 0x08000000
#define BCSR1_FETH_RST 0x04000000
#define BCSR1_RS232_EN1 0x02000000
#define BCSR1_RS232_EN2 0x01000000
#define BCSR3_USB_nEN 0x80000000
#define BCSR3_FETHIEN2 0x10000000
#define BCSR3_FETH2_RST 0x08000000
clrbits32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN);
setbits32(&bcsr[1], BCSR1_FETH_RST);
clrbits32(&bcsr[3], BCSR3_FETHIEN2);
setbits32(&bcsr[3], BCSR3_FETH2_RST);
clrbits32(&bcsr[3], BCSR3_USB_nEN);
iounmap(bcsr);
init_ioports();
pq2_init_pci();
if (ppc_md.progress)
ppc_md.progress("mpc8272_ads_setup_arch(), finish", 0);
}
static void __init mgcoge_setup_arch(void)
{
if (ppc_md.progress)
ppc_md.progress("mgcoge_setup_arch()", 0);
cpm2_reset();
/* When this is set, snooping CPM DMA from RAM causes
* machine checks. See erratum SIU18.
*/
clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP);
init_ioports();
if (ppc_md.progress)
ppc_md.progress("mgcoge_setup_arch(), finish", 0);
}
/*
* Setup the architecture
*/
static void __init ksi8560_setup_arch(void)
{
struct device_node *cpld;
cpld = of_find_compatible_node(NULL, NULL, "emerson,KSI8560-cpld");
if (cpld)
cpld_base = of_iomap(cpld, 0);
else
printk(KERN_ERR "Can't find CPLD in device tree\n");
if (ppc_md.progress)
ppc_md.progress("ksi8560_setup_arch()", 0);
#ifdef CONFIG_CPM2
cpm2_reset();
init_ioports();
#endif
}
static void __init sbc8560_setup_arch(void)
{
#ifdef CONFIG_PCI
struct device_node *np;
#endif
if (ppc_md.progress)
ppc_md.progress("sbc8560_setup_arch()", 0);
#ifdef CONFIG_CPM2
cpm2_reset();
init_ioports();
#endif
#ifdef CONFIG_PCI
for_each_compatible_node(np, "pci", "fsl,mpc8540-pci")
fsl_add_bridge(np, 1);
#endif
}
static void __init pq2fads_setup_arch(void)
{
struct device_node *np;
__be32 __iomem *bcsr;
if (ppc_md.progress)
ppc_md.progress("pq2fads_setup_arch()", 0);
cpm2_reset();
np = of_find_compatible_node(NULL, NULL, "fsl,pq2fads-bcsr");
if (!np) {
printk(KERN_ERR "No fsl,pq2fads-bcsr in device tree\n");
return;
}
bcsr = of_iomap(np, 0);
of_node_put(np);
if (!bcsr) {
printk(KERN_ERR "Cannot map BCSR registers\n");
return;
}
/* Enable the serial and ethernet ports */
clrbits32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN);
setbits32(&bcsr[1], BCSR1_FETH_RST);
clrbits32(&bcsr[3], BCSR3_FETHIEN2);
setbits32(&bcsr[3], BCSR3_FETH2_RST);
iounmap(bcsr);
init_ioports();
/* Enable external IRQs */
clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_siumcr, 0x0c000000);
pq2_init_pci();
if (ppc_md.progress)
ppc_md.progress("pq2fads_setup_arch(), finish", 0);
}
static void __init ep8248e_setup_arch(void)
{
if (ppc_md.progress)
ppc_md.progress("ep8248e_setup_arch()", 0);
cpm2_reset();
/* When this is set, snooping CPM DMA from RAM causes
* machine checks. See erratum SIU18.
*/
clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP);
ep8248e_bcsr_node =
of_find_compatible_node(NULL, NULL, "fsl,ep8248e-bcsr");
if (!ep8248e_bcsr_node) {
printk(KERN_ERR "No bcsr in device tree\n");
return;
}
ep8248e_bcsr = of_iomap(ep8248e_bcsr_node, 0);
if (!ep8248e_bcsr) {
printk(KERN_ERR "Cannot map BCSR registers\n");
of_node_put(ep8248e_bcsr_node);
ep8248e_bcsr_node = NULL;
return;
}
setbits8(&ep8248e_bcsr[7], BCSR7_SCC2_ENABLE);
setbits8(&ep8248e_bcsr[8], BCSR8_PHY1_ENABLE | BCSR8_PHY1_POWER |
BCSR8_PHY2_ENABLE | BCSR8_PHY2_POWER);
init_ioports();
if (ppc_md.progress)
ppc_md.progress("ep8248e_setup_arch(), finish", 0);
}
static void __init adder875_setup(void)
{
cpm_reset();
init_ioports();
}
static void __init tqm8xx_setup_arch(void)
{
cpm_reset();
init_ioports();
}
static void __init mpc885ads_setup_arch(void)
{
struct device_node *np;
cpm_reset();
init_ioports();
np = of_find_compatible_node(NULL, NULL, "fsl,mpc885ads-bcsr");
if (!np) {
printk(KERN_CRIT "Could not find fsl,mpc885ads-bcsr node\n");
return;
}
bcsr = of_iomap(np, 0);
bcsr5 = of_iomap(np, 1);
of_node_put(np);
if (!bcsr || !bcsr5) {
printk(KERN_CRIT "Could not remap BCSR\n");
return;
}
clrbits32(&bcsr[1], BCSR1_RS232EN_1);
#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
setbits32(&bcsr[1], BCSR1_RS232EN_2);
#else
clrbits32(&bcsr[1], BCSR1_RS232EN_2);
#endif
clrbits32(bcsr5, BCSR5_MII1_EN);
setbits32(bcsr5, BCSR5_MII1_RST);
udelay(1000);
clrbits32(bcsr5, BCSR5_MII1_RST);
#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
clrbits32(bcsr5, BCSR5_MII2_EN);
setbits32(bcsr5, BCSR5_MII2_RST);
udelay(1000);
clrbits32(bcsr5, BCSR5_MII2_RST);
#else
setbits32(bcsr5, BCSR5_MII2_EN);
#endif
#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
clrbits32(&bcsr[4], BCSR4_ETH10_RST);
udelay(1000);
setbits32(&bcsr[4], BCSR4_ETH10_RST);
setbits32(&bcsr[1], BCSR1_ETHEN);
np = of_find_node_by_path("/soc@ff000000/cpm@9c0/serial@a80");
#else
np = of_find_node_by_path("/soc@ff000000/cpm@9c0/ethernet@a40");
#endif
/* The SCC3 enet registers overlap the SMC1 registers, so
* one of the two must be removed from the device tree.
*/
if (np) {
of_detach_node(np);
of_node_put(np);
}
}
