/*
* Out of reset, the low-level assembly code calls this routine to
* initialize the mcf5206e for this board. A temporary stack has been
* setup in the internal SRAM, and the stack pointer will be changed
* to point to DRAM once this routine returns.
*/
void __initialize_hardware(void)
{
/*******************************************************
* Out of reset, the low-level assembly code calls this
* routine to initialize the MCF52221 modules for the
* M522223EVB board.
********************************************************/
asm {
/* Initialize IPSBAR */
move.l #__IPSBAR,d0
andi.l #0xC0000000,d0 // need to mask
add.l #0x1,d0
move.l d0,0x40000000
/* Initialize FLASHBAR */
move.l #__FLASHBAR,d0
andi.l #0xFFF80000,d0 // need to mask
add.l #0x61,d0
movec d0,FLASHBAR
}
/* Set real time clock freq */
MCF_CLOCK_RTCDR = 48000000;
pll_init();
scm_init();
initialize_exceptions();
}
void __initialize_hardware(void)
{
/*******************************************************
* Out of reset, the low-level assembly code calls this
* routine to initialize the MCF52259 modules.
********************************************************/
asm
{
/* Initialize IPSBAR */
move.l #__IPSBAR,d0
andi.l #0xC0000000,d0 // need to mask
add.l #0x1,d0
move.l d0,0x40000000
/* Initialize FLASHBAR */
move.l #__FLASHBAR,d0
andi.l #0xFFF80000,d0 // need to mask
add.l #0x61,d0
movec d0,FLASHBAR
}
pll_init();
scm_init();
initialize_exceptions();
}
init_print (void)
{
PyObject *m, *d;
init_pygobject ();
m = Py_InitModule ("_print", pyprint_functions);
d = PyModule_GetDict (m);
initialize_exceptions (d);
pyprint_register_classes (d);
pyprint_add_defined_constants (m);
}
void __initialize_hardware(void)
{
/*******************************************************
* Out of reset, the low-level assembly code calls this
* routine to initialize the derivative modules for the
* board.
********************************************************/
//DM gpio_init();
fbcs_init();
sdramc_init();
/* enabling peripheral clocks */
MCF_PMM_PPMLR0 &= ~(MCF_PMM_PPMLR0_CD18); /* ICTRL0 */
MCF_PMM_PPMLR0 &= ~(MCF_PMM_PPMLR0_CD19); /* ICTRL1 */
MCF_PMM_PPMLR0 &= ~(MCF_PMM_PPMLR0_CD20); /* ICTRL2 */
initialize_exceptions();
}
/*
* bsp_start()
*
* Board-specific initialization code. Called from the generic boot_card()
* function defined in rtems/c/src/lib/libbsp/shared/main.c. That function
* does some of the board independent initialization. It is called from the
* SS555 entry point _start() defined in
* rtems/c/src/lib/libbsp/powerpc/ss555/start/start.S
*
* _start() has set up a stack, has zeroed the .bss section, has set up the
* .data section from contents stored in ROM, has turned off interrupts,
* and placed the processor in the supervisor mode. boot_card() has left
* the processor in that state when bsp_start() was called.
*
* Input parameters: NONE
*
* Output parameters: NONE
*
* Return values: NONE
*/
void bsp_start(void)
{
ppc_cpu_id_t myCpu;
ppc_cpu_revision_t myCpuRevision;
register unsigned char* intrStack;
/*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type()
* function stores the result in global variables so that it can be used
* later.
*/
myCpu = get_ppc_cpu_type();
myCpuRevision = get_ppc_cpu_revision();
/*
* Initialize some SPRG registers related to irq handling
*/
intrStack = (((unsigned char*)&intrStackPtr) - PPC_MINIMUM_STACK_FRAME_SIZE);
_write_SPRG1((unsigned int)intrStack);
/*
* Install our own set of exception vectors
*/
initialize_exceptions();
/*
* initialize the device driver parameters
*/
bsp_clicks_per_usec = BSP_CRYSTAL_HZ / 4 / 1000000;
bsp_clock_speed = BSP_CLOCK_HZ; /* for SCI baud rate generator */
bsp_timer_least_valid = 0;
bsp_timer_average_overhead = 0;
rtems_counter_initialize_converter(BSP_CRYSTAL_HZ / 4);
/*
* Initalize RTEMS IRQ system
*/
BSP_rtems_irq_mng_init(0);
}
void __initialize_hardware(void)
{
/*******************************************************
* Out of reset, the low-level assembly code calls this
* routine to initialize the MCF52233 modules for the
* M52233DEMO board.
********************************************************/
asm
{
/* Initialize IPSBAR */
move.l #__IPSBAR,d0
andi.l #0xC0000000,d0 // need to mask
add.l #0x1,d0
move.l d0,0x40000000
/* Initialize FLASHBAR */
move.l #__FLASHBAR,d0
andi.l #0xFFF80000,d0 // need to mask
add.l #0x61,d0
movec d0,FLASHBAR
}
/*
* Allow interrupts from ABORT, SW1, SW2, and SW3 (IRQ[1,4,7,11])
*/
/* Enable IRQ signals on the port */
MCF_GPIO_PNQPAR = 0
| MCF_GPIO_PNQPAR_IRQ1_IRQ1
| MCF_GPIO_PNQPAR_IRQ4_IRQ4
| MCF_GPIO_PNQPAR_IRQ7_IRQ7;
MCF_GPIO_PGPPAR = 0
| MCF_GPIO_PGPPAR_IRQ11_IRQ11;
/* Set EPORT to look for rising edges */
MCF_EPORT0_EPPAR = 0
| MCF_EPORT_EPPAR_EPPA1_RISING
| MCF_EPORT_EPPAR_EPPA4_RISING
| MCF_EPORT_EPPAR_EPPA7_RISING;
MCF_EPORT1_EPPAR = 0
| MCF_EPORT_EPPAR_EPPA11_RISING;
/* Clear any currently triggered events on the EPORT */
MCF_EPORT0_EPIER = 0
| MCF_EPORT_EPIER_EPIE1
| MCF_EPORT_EPIER_EPIE4
| MCF_EPORT_EPIER_EPIE7;
MCF_EPORT1_EPIER = 0
| MCF_EPORT_EPIER_EPIE11;
/* Enable interrupts in the interrupt controller */
MCF_INTC0_IMRL &= ~(0
| MCF_INTC_IMRL_INT_MASK1
| MCF_INTC_IMRL_INT_MASK4
| MCF_INTC_IMRL_INT_MASK7
| MCF_INTC_IMRL_MASKALL);
MCF_INTC1_IMRH &= ~(0
| MCF_INTC_IMRH_INT_MASK35);
MCF_INTC1_ICR35 = MCF_INTC_ICR_IL(4);
MCF_GPIO_PDDPAR = 0x0F;
/* Set real time clock freq */
MCF_CLOCK_RTCDR = 25000000;
/* Set GPIO for UART0 */
MCF_GPIO_PUAPAR = 0
| MCF_GPIO_PUAPAR_URXD0_URXD0
| MCF_GPIO_PUAPAR_UTXD0_UTXD0;
wtm_init();
pll_init();
scm_init();
initialize_exceptions();
}
/*
* bsp_start()
*
* Board-specific initialization code. Called from the generic boot_card()
* function defined in rtems/c/src/lib/libbsp/shared/main.c. That function
* does some of the board independent initialization. It is called from the
* SS555 entry point _start() defined in
* rtems/c/src/lib/libbsp/powerpc/ss555/startup/start.S
*
* _start() has set up a stack, has zeroed the .bss section, has set up the
* .data section from contents stored in ROM, has turned off interrupts,
* and placed the processor in the supervisor mode. boot_card() has left
* the processor in that state when bsp_start() was called.
*
* Input parameters: NONE
*
* Output parameters: NONE
*
* Return values: NONE
*/
void bsp_start(void)
{
extern char _WorkspaceBase[];
ppc_cpu_id_t myCpu;
ppc_cpu_revision_t myCpuRevision;
register unsigned char* intrStack;
/*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type()
* function stores the result in global variables so that it can be used
* later.
*/
myCpu = get_ppc_cpu_type();
myCpuRevision = get_ppc_cpu_revision();
/*
* Initialize some SPRG registers related to irq handling
*/
intrStack = (((unsigned char*)&intrStackPtr) - PPC_MINIMUM_STACK_FRAME_SIZE);
_write_SPRG1((unsigned int)intrStack);
/* signal them that we have fixed PR288 - eventually, this should go away */
_write_SPRG0(PPC_BSP_HAS_FIXED_PR288);
/*
* Install our own set of exception vectors
*/
initialize_exceptions();
/*
* Allocate the memory for the RTEMS Work Space. This can come from
* a variety of places: hard coded address, malloc'ed from outside
* RTEMS world (e.g. simulator or primitive memory manager), or (as
* typically done by stock BSPs) by subtracting the required amount
* of work space from the last physical address on the CPU board.
*
* In this case, the memory is not malloc'ed. It is just
* "pulled from the air".
*/
BSP_Configuration.work_space_start = _WorkspaceBase;
/*
* initialize the CPU table for this BSP
*/
Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */
Cpu_table.postdriver_hook = bsp_postdriver_hook;
if( Cpu_table.interrupt_stack_size < 4 * 1024 )
Cpu_table.interrupt_stack_size = 4 * 1024;
Cpu_table.clicks_per_usec = BSP_CRYSTAL_HZ / 4 / 1000000;
Cpu_table.clock_speed = BSP_CLOCK_HZ; /* for SCI baud rate generator */
/*
* Call this in case we use TERMIOS for console I/O
*/
m5xx_uart_reserve_resources( &BSP_Configuration );
/*
* Initalize RTEMS IRQ system
*/
BSP_rtems_irq_mng_init(0);
}
void bsp_start(void)
{
extern void *_WorkspaceBase;
ppc_cpu_id_t myCpu;
ppc_cpu_revision_t myCpuRevision;
register unsigned char* intrStack;
/* Set MPC8260ADS board LEDS and Uart enable lines */
_BSP_GPLED0_off();
_BSP_GPLED1_off();
_BSP_Uart1_enable();
_BSP_Uart2_enable();
/*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
* store the result in global variables so that it can be used latter...
*/
myCpu = get_ppc_cpu_type();
myCpuRevision = get_ppc_cpu_revision();
cpu_init();
/*
mmu_init();
*/
/*
* Initialize some SPRG registers related to irq handling
*/
intrStack = (((unsigned char*)&intrStackPtr) - PPC_MINIMUM_STACK_FRAME_SIZE);
_write_SPRG1((unsigned int)intrStack);
/* signal that we have fixed PR288 - eventually, this should go away */
_write_SPRG0(PPC_BSP_HAS_FIXED_PR288);
/*
printk( "About to call initialize_exceptions\n" );
*/
/*
* Install our own set of exception vectors
*/
initialize_exceptions();
/*
mmu_init();
*/
/*
* Enable instruction and data caches. Do not force writethrough mode.
*/
#if INSTRUCTION_CACHE_ENABLE
rtems_cache_enable_instruction();
#endif
#if DATA_CACHE_ENABLE
rtems_cache_enable_data();
#endif
/*
* Allocate the memory for the RTEMS Work Space. This can come from
* a variety of places: hard coded address, malloc'ed from outside
* RTEMS world (e.g. simulator or primitive memory manager), or (as
* typically done by stock BSPs) by subtracting the required amount
* of work space from the last physical address on the CPU board.
*/
/*
* Need to "allocate" the memory for the RTEMS Workspace and
* tell the RTEMS configuration where it is. This memory is
* not malloc'ed. It is just "pulled from the air".
*/
BSP_Configuration.work_space_start = (void *)&_WorkspaceBase;
/*
BSP_Configuration.microseconds_per_tick = 1000;
*/
/*
* initialize the CPU table for this BSP
*/
Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */
Cpu_table.postdriver_hook = bsp_postdriver_hook;
if( Cpu_table.interrupt_stack_size < 4*1024 )
Cpu_table.interrupt_stack_size = 4 * 1024;
Cpu_table.clicks_per_usec = 10; /* for 40MHz extclk */
Cpu_table.serial_per_sec = 40000000;
Cpu_table.serial_external_clock = 0;
Cpu_table.serial_xon_xoff = 0;
Cpu_table.serial_cts_rts = 0;
Cpu_table.serial_rate = 9600;
Cpu_table.timer_average_overhead = 3;
Cpu_table.timer_least_valid = 3;
Cpu_table.clock_speed = 40000000;
#ifdef REV_0_2
/* set up some board specific registers */
m8260.siumcr &= 0xF3FFFFFF; /* set TBEN ** BUG FIX ** */
m8260.siumcr |= 0x08000000;
#endif
/* use BRG1 to generate 32kHz timebase */
/*
m8260.brgc1 = M8260_BRG_EN + (uint32_t)(((uint16_t)((40016384)/(32768)) - 1) << 1) + 0;
*/
/*
* Initalize RTEMS IRQ system
*/
BSP_rtems_irq_mng_init(0);
/*
* Call this in case we use TERMIOS for console I/O
*/
m8xx_uart_reserve_resources(&BSP_Configuration);
/*
rtems_termios_initialize();
*/
#ifdef SHOW_MORE_INIT_SETTINGS
printk("Exit from bspstart\n");
#endif
}