static void intel_dsi_pre_enable(struct intel_encoder *encoder)
{
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
int pipe = intel_crtc->pipe;
DRM_DEBUG_KMS("\n");
intel_enable_dsi_pll(intel_dsi);
if (is_cmd_mode(intel_dsi)) {
/* XXX: Implement me */
I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4);
}
else {
intel_dsi->hs = 0;
dpi_send_cmd(intel_dsi, TURN_ON);
usleep_range(1000, 1500);
if (intel_dsi->dev.dev_ops->enable)
intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);
intel_dsi_port_enable(encoder);
}
}
static void intel_dsi_pre_enable(struct intel_encoder *encoder)
{
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
int pipe = intel_crtc->pipe;
bool is_dsi;
u32 temp;
DRM_DEBUG_KMS("\n");
is_dsi = intel_pipe_has_type(encoder->base.crtc, INTEL_OUTPUT_DSI);
intel_enable_dsi_pll(intel_dsi);
printk("====>DLP3430 debug 2.20.\n");
if (is_cmd_mode(intel_dsi)) {
/* XXX: Implement me */
I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4);
}
else {
intel_dsi->hs = 1;
dpi_send_cmd(intel_dsi, TURN_ON);
usleep_range(1000, 1500);
if (intel_dsi->dev.dev_ops->enable)
intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);
temp = I915_READ(MIPI_PORT_CTRL(pipe));
temp = temp | intel_dsi->port_bits;
if (is_dsi && intel_crtc->config.dither)
temp |= DITHERING_ENABLE;
I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE);
usleep_range(2000, 2500);
}
}
void intel_dsi_device_ready(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
int pipe = intel_crtc->pipe;
u32 tmp;
DRM_DEBUG_KMS("\n");
/* program rcomp for compliance
* reduce form 50 ohms to 45 ohms */
intel_flisdsi_write32(dev_priv, 0x04, 0x00f0);
band_gap_reset(dev_priv);
#ifdef CONFIG_CRYSTAL_COVE
/* Panel Enable */
if (BYT_CR_CONFIG) {
/* cabc disable */
vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PCONF0, 0x2000CC00);
vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PAD, 0x00000004);
/* panel enable */
vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PCONF0, 0x2000CC00);
vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PAD, 0x00000005);
udelay(500);
} else
intel_mid_pmic_writeb(PMIC_PANEL_EN, 0x01);
#else
/* need to code for BYT-CR for example where things have changed */
DRM_ERROR("PANEL Enable to supported yet\n");
#endif
msleep(intel_dsi->panel_on_delay);
if (intel_dsi->dev.dev_ops->panel_reset)
intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);
/* Disable DPOunit clock gating, can stall pipe */
tmp = I915_READ(DPLL(pipe));
tmp |= DPLL_RESERVED_BIT;
I915_WRITE(DPLL(pipe), tmp);
tmp = I915_READ(DSPCLK_GATE_D);
tmp |= VSUNIT_CLOCK_GATE_DISABLE;
I915_WRITE(DSPCLK_GATE_D, tmp);
intel_enable_dsi_pll(intel_dsi);
//in dual display config, dsi 0 is not init. so this function may not
//be called with pipe0. set this flag for pipe0 so that pipe b can work
#ifdef BYT_DUAL_MIPI_DSI
if(pipe != 0)
{
I915_WRITE_BITS(MIPI_PORT_CTRL(0), LP_OUTPUT_HOLD,
LP_OUTPUT_HOLD);
usleep_range(1000, 1500);
}
#endif
I915_WRITE_BITS(MIPI_PORT_CTRL(pipe), LP_OUTPUT_HOLD,
LP_OUTPUT_HOLD);
usleep_range(1000, 1500);
I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), DEVICE_READY |
ULPS_STATE_EXIT, DEVICE_READY |
ULPS_STATE_MASK);
usleep_range(2000, 2500);
I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), DEVICE_READY,
DEVICE_READY | ULPS_STATE_MASK);
usleep_range(2000, 2500);
I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), 0x00,
DEVICE_READY | ULPS_STATE_MASK);
usleep_range(2000, 2500);
I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), DEVICE_READY,
DEVICE_READY | ULPS_STATE_MASK);
usleep_range(2000, 2500);
}
void intel_dsi_device_ready(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
int pipe = intel_crtc->pipe;
u32 tmp;
int count = 1;
DRM_DEBUG_KMS("\n");
/* program rcomp for compliance
* reduce form 50 ohms to 45 ohms */
intel_flisdsi_write32(dev_priv, 0x04, 0x0004);
band_gap_reset(dev_priv);
#ifdef CONFIG_CRYSTAL_COVE
if (BYT_CR_CONFIG) {
/* cabc disable */
vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PCONF0, 0x2000CC00);
vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PAD, 0x00000004);
/* panel enable */
vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PCONF0, 0x2000CC00);
vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PAD, 0x00000005);
udelay(500);
} else
intel_mid_pmic_writeb(PMIC_PANEL_EN, 0x01);
#else
/* need to code for BYT-CR for example where things have changed */
DRM_ERROR("PANEL Enable to supported yet\n");
#endif
msleep(intel_dsi->panel_on_delay);
if (intel_dsi->dev.dev_ops->panel_reset)
intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);
/* Disable DPOunit clock gating, can stall pipe */
tmp = I915_READ(DPLL(pipe));
tmp |= DPLL_RESERVED_BIT;
I915_WRITE(DPLL(pipe), tmp);
tmp = I915_READ(DSPCLK_GATE_D);
tmp |= VSUNIT_CLOCK_GATE_DISABLE;
I915_WRITE(DSPCLK_GATE_D, tmp);
intel_enable_dsi_pll(intel_dsi);
if (intel_dsi->operation_mode == DSI_VIDEO_MODE) {
I915_WRITE_BITS(MIPI_PORT_CTRL(pipe), LP_OUTPUT_HOLD,
LP_OUTPUT_HOLD);
usleep_range(1000, 1500);
if (intel_dsi->dual_link)
count = 2;
do {
I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), DEVICE_READY |
ULPS_STATE_EXIT, DEVICE_READY |
ULPS_STATE_MASK);
usleep_range(2000, 2500);
I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), DEVICE_READY,
DEVICE_READY | ULPS_STATE_MASK);
usleep_range(2000, 2500);
I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), 0x00,
DEVICE_READY | ULPS_STATE_MASK);
usleep_range(2000, 2500);
I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), DEVICE_READY,
DEVICE_READY | ULPS_STATE_MASK);
usleep_range(2000, 2500);
/* For Port C for dual link */
pipe = PIPE_B;
} while (--count > 0);
}
}
