/**
* Returns the mask of how many bits of x and y must be handled through the
* depthbuffer's draw offset x and y fields.
*
* The draw offset x/y field of the depthbuffer packet is unfortunately shared
* between the depth, hiz, and stencil buffers. Because it can be hard to get
* all 3 to agree on this value, we want to do as much drawing offset
* adjustment as possible by moving the base offset of the 3 buffers, which is
* restricted to tile boundaries.
*
* For each buffer, the remainder must be applied through the x/y draw offset.
* This returns the worst-case mask of the low bits that have to go into the
* packet. If the 3 buffers don't agree on the drawing offset ANDed with this
* mask, then we're in trouble.
*/
void
brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt,
uint32_t depth_level,
uint32_t depth_layer,
struct intel_mipmap_tree *stencil_mt,
uint32_t *out_tile_mask_x,
uint32_t *out_tile_mask_y)
{
uint32_t tile_mask_x = 0, tile_mask_y = 0;
if (depth_mt) {
intel_miptree_get_tile_masks(depth_mt, &tile_mask_x, &tile_mask_y, false);
if (intel_miptree_level_has_hiz(depth_mt, depth_level)) {
uint32_t hiz_tile_mask_x, hiz_tile_mask_y;
intel_miptree_get_tile_masks(depth_mt->hiz_mt,
&hiz_tile_mask_x, &hiz_tile_mask_y,
false);
/* Each HiZ row represents 2 rows of pixels */
hiz_tile_mask_y = hiz_tile_mask_y << 1 | 1;
tile_mask_x |= hiz_tile_mask_x;
tile_mask_y |= hiz_tile_mask_y;
}
}
if (stencil_mt) {
if (stencil_mt->stencil_mt)
stencil_mt = stencil_mt->stencil_mt;
if (stencil_mt->format == MESA_FORMAT_S_UINT8) {
/* Separate stencil buffer uses 64x64 tiles. */
tile_mask_x |= 63;
tile_mask_y |= 63;
} else {
uint32_t stencil_tile_mask_x, stencil_tile_mask_y;
intel_miptree_get_tile_masks(stencil_mt,
&stencil_tile_mask_x,
&stencil_tile_mask_y, false);
tile_mask_x |= stencil_tile_mask_x;
tile_mask_y |= stencil_tile_mask_y;
}
}
*out_tile_mask_x = tile_mask_x;
*out_tile_mask_y = tile_mask_y;
}
/**
* Split x_offset and y_offset into a base offset (in bytes) and a remaining
* x/y offset (in pixels). Note: we can't do this by calling
* intel_renderbuffer_tile_offsets(), because the offsets may have been
* adjusted to account for Y vs. W tiling differences. So we compute it
* directly from the adjusted offsets.
*/
uint32_t
brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x,
uint32_t *tile_y) const
{
uint32_t mask_x, mask_y;
intel_miptree_get_tile_masks(mt, &mask_x, &mask_y, map_stencil_as_y_tiled);
*tile_x = x_offset & mask_x;
*tile_y = y_offset & mask_y;
return intel_miptree_get_aligned_offset(mt, x_offset & ~mask_x,
y_offset & ~mask_y,
map_stencil_as_y_tiled);
}
