int intel_mid_pwm(int id, int value)
{
int ret;
struct pwm_info *pi = &pwm_info;
int msic_reg_pwmclkdiv0 = *(pi->msic_reg_clkdiv0 + id);
int msic_reg_pwmclkdiv1 = *(pi->msic_reg_clkdiv1 + id);
int msic_reg_pwmdutycyc = *(pi->msic_reg_dutycyc + id);
if (!pi->initialized)
return -ENODEV;
if (value < 0 || value > MAX_DUTYCYCLE_PERCENTAGE) {
dev_err(pi->dev, "duty cycle value invalid\n");
return -EINVAL;
}
value = (value == 100) ? 99 : value;
mutex_lock(&pi->lock);
ret = intel_scu_ipc_iowrite8(msic_reg_pwmclkdiv1, 0x00);
if (ret) {
dev_err(pi->dev, "set MSIC_REG_PWMCLKDIV1 failed\n");
goto out;
}
ret = intel_scu_ipc_iowrite8(msic_reg_pwmclkdiv0, value ? 0x03 : 0x00);
if (ret) {
dev_err(pi->dev, "set MSIC_REG_PWMCLKDIV0 failed\n");
goto out;
}
ret = intel_scu_ipc_iowrite8(msic_reg_pwmdutycyc, value);
if (ret)
dev_err(pi->dev, "set MSIC_REG_PWMDUTYCYCLE failed\n");
out:
mutex_unlock(&pi->lock);
return ret;
}
bool ps_hdmi_power_rails_off(void)
{
int ret = 0;
pr_debug("Entered %s\n", __func__);
ret = intel_scu_ipc_iowrite8(PS_MSIC_VCC330CNT, PS_VCC330_OFF);
if (ret) {
pr_debug("%s: Failed to power off VCC330.\n", __func__);
return false;
}
return true;
}
static int ps_hdmi_hpd_resume(struct device *dev)
{
int ret = 0;
pr_debug("Entered %s\n", __func__);
ret = intel_scu_ipc_iowrite8(PS_MSIC_VCC330CNT, PS_VCC330_ON);
if (ret) {
pr_debug("%s: Failed to power on VCC330.\n",
__func__);
goto err;
}
/* MSIC documentation requires that there be a 500us delay
after enabling VCC330 before you can enable VHDMI */
usleep_range(500, 1000);
ret = intel_scu_ipc_iowrite8(PS_MSIC_VHDMICNT,
PS_VHDMI_ON | PS_VHDMI_DB_30MS);
if (ret) {
pr_debug("%s: Failed to power on VHDMI.\n",
__func__);
goto err;
}
/* We schedule a delayed wok item to be executed only after the
* the full system has resumed.
*/
queue_work(g_context->post_resume_wq, &g_context->post_resume_work);
pr_debug("Exiting %s\n", __func__);
return ret;
err:
pr_debug("Exiting %s\n", __func__);
return ret;
}
static int program_bcu(void *ocd_smip_addr)
{
int ret, i;
u8 *smip_data;
if (!ocd_smip_addr)
return -ENXIO;
smip_data = (u8 *)ocd_smip_addr;
mutex_lock(&ocd_update_lock);
for (i = 0; i < NUM_SMIP_BYTES-1 ; i++, smip_data++) {
ret = intel_scu_ipc_iowrite8(VWARN1_CFG + i, *smip_data);
if (ret)
goto ipc_fail;
}
/* MBCUIRQ register address not consecutive with other BCU registers */
ret = intel_scu_ipc_iowrite8(MBCUIRQ, *smip_data);
ipc_fail:
mutex_unlock(&ocd_update_lock);
return ret;
}
static void enable_volt_trip_points(void)
{
int i, ret;
uint8_t data;
/*
* Enable the Voltage comparator logic, so that the output
* signals are asserted when a voltage drop occurs.
*/
for (i = 0; i < NUM_VOLT_LEVELS; i++) {
ret = intel_scu_ipc_ioread8(VWARN1_CFG + i, &data);
if (!ret)
intel_scu_ipc_iowrite8(VWARN1_CFG + i,
(data | VWARN_EN));
}
}
static void enable_current_trip_points(void)
{
int i, ret;
uint8_t data;
/*
* Enable the Current comparator logic, so that the output
* signals are asserted when the platform current surges.
*/
for (i = 0; i < NUM_CURR_LEVELS; i++) {
ret = intel_scu_ipc_ioread8(MAXVCC_CFG + i, &data);
if (!ret)
intel_scu_ipc_iowrite8(MAXVCC_CFG + i,
(data | ICCMAX_EN));
}
}
static void __vpro2_power_ctrl(bool on)
{
u8 addr, value;
addr = 0xad;
if (intel_scu_ipc_ioread8(addr, &value))
DRM_ERROR("%s: %d: failed to read vPro2\n", __func__, __LINE__);
/* Control vPROG2 power rail with 2.85v. */
if (on)
value |= 0x1;
else
value &= ~0x1;
if (intel_scu_ipc_iowrite8(addr, value))
DRM_ERROR("%s: %d: failed to write vPro2\n",
__func__, __LINE__);
}
/* Board specific cleanup related to SD goes here */
static void mrfl_sd_cleanup(struct sdhci_pci_data *data)
{
u8 vldocnt = 0;
int err;
err = intel_scu_ipc_ioread8(MRFLD_PMIC_VLDOCNT, &vldocnt);
if (err) {
pr_err("PMIC vldocnt IPC read error: %d\n", err);
return;
}
vldocnt &= MRFLD_PMIC_VLDOCNT_PW_OFF;
err = intel_scu_ipc_iowrite8(MRFLD_PMIC_VLDOCNT, vldocnt);
if (err)
pr_err("PMIC vldocnt IPC write error: %d\n", err);
return;
}
/**
* configure_adc - enables/disables the ADC for conversion
* @val: zero: disables the ADC non-zero:enables the ADC
*
* Enable/Disable the ADC depending on the argument
*
* Can sleep
*/
static int configure_adc(int val)
{
int ret;
uint8_t data;
ret = intel_scu_ipc_ioread8(MSIC_THERM_ADC1CNTL1, &data);
if (ret)
return ret;
if (val) {
/* Enable and start the ADC */
data |= (MSIC_ADC_ENBL | MSIC_ADC_START);
} else {
/* Just stop the ADC */
data &= (~MSIC_ADC_START);
}
return intel_scu_ipc_iowrite8(MSIC_THERM_ADC1CNTL1, data);
}
static int set_threshold(u16 reg_addr, int pos)
{
int ret;
uint8_t data;
mutex_lock(&ocd_update_lock);
ret = intel_scu_ipc_ioread8(reg_addr, &data);
if (ret)
goto ipc_fail;
/* Set bits [0-2] to value of pos */
data = (data & 0xF8) | pos;
ret = intel_scu_ipc_iowrite8(reg_addr, data);
ipc_fail:
mutex_unlock(&ocd_update_lock);
return ret;
}
static ssize_t blink_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct led_classdev *led_cdev = dev_get_drvdata(dev);
struct led_info_data *led_dat = container_of(led_cdev, struct led_info_data, cdev);
int value, ret=0;
uint8_t ctrldata, pwmdata;
sscanf(buf, "%d", &value);
#ifdef CONTROL_LED
if(disable_led_flag==0) {
#endif
if(value==0) {
/* stop blink */
if(!strcmp(led_dat->cdev.name, "red")&&(red_blink_flag==1)) {
ret = intel_scu_ipc_ioread8(CHRLEDCTRL, &ctrldata);
if (ret) {
LED_err(" IPC Failed to read %d\n", ret);
}
ctrldata &= ~BLEDON;
ctrldata &= ~CHRLEDBP;
ret = intel_scu_ipc_iowrite8(CHRLEDCTRL, ctrldata);
if (ret) {
LED_err(" IPC Failed to write %d\n", ret);
}
red_blink_flag = 0;
}else if(!strcmp(led_dat->cdev.name, "green")&&(green_blink_flag==1)) {
ret = intel_scu_ipc_ioread8(CHRLEDCTRL, &ctrldata);
if (ret) {
LED_err(" IPC Failed to read %d\n", ret);
}
ctrldata &= ~BLEDON;
ctrldata &= ~CHRLEDBP;
ret = intel_scu_ipc_iowrite8(CHRLEDCTRL, ctrldata);
if (ret) {
LED_err(" IPC Failed to write %d\n", ret);
}
green_blink_flag = 0;
}
/*power off*/
if(!strcmp(led_dat->cdev.name, "red")) {
gpio_direction_output(RED_LED_GPIO, 0);
red_led_flag = 0;
}else if(!strcmp(led_dat->cdev.name, "green")) {
gpio_direction_output(GREEN_LED_GPIO, 0);
green_led_flag = 0;
}
LED_info("%s, disable blink and register ctrldata=0x%x\n", __func__, ctrldata);
}
else if(value>0&&value<=100) {
/* power on*/
if(!strcmp(led_dat->cdev.name, "red")) {
gpio_direction_output(RED_LED_GPIO, 1);
red_led_flag = 1;
red_blink_flag = 1;
}else if(!strcmp(led_dat->cdev.name, "green")) {
gpio_direction_output(GREEN_LED_GPIO, 1);
green_led_flag = 1;
green_blink_flag = 1;
}
/* start blink */
ret = intel_scu_ipc_ioread8(CHRLEDCTRL, &ctrldata);
if (ret) {
LED_err(" IPC Failed to read %d\n", ret);
}
ctrldata &= ~BLEDON;
ctrldata &= ~CHRLEDBP;
ret = intel_scu_ipc_iowrite8(CHRLEDCTRL, ctrldata);
if (ret) {
LED_err(" IPC Failed to write %d\n", ret);
}
if(!strcmp(led_dat->cdev.name, "red"))
value = 99; //0.025s per 4s
else
value = 99; //0.025s per 2s
pwmdata = (uint8_t)value*255/100;
ret = intel_scu_ipc_iowrite8(CHRLEDPWM, pwmdata);
if (ret) {
LED_err(" IPC Failed to write %d\n", ret);
}
ret = intel_scu_ipc_ioread8(CHRLEDPWM, &pwmdata);
if (ret) {
LED_err(" IPC Failed to read %d\n", ret);
}
ret = intel_scu_ipc_ioread8(CHRLEDCTRL, &ctrldata);
if (ret) {
LED_err(" IPC Failed to read %d\n", ret);
}
ctrldata |= BLEDON;
ctrldata |= CHRLEDBP;
if(!strcmp(led_dat->cdev.name, "red")) { //4s
ctrldata &= ~(BIT(3));
ctrldata &= ~(BIT(4));
}else if(!strcmp(led_dat->cdev.name, "green")) { //2s
ctrldata |= (BIT(3));
ctrldata &= ~(BIT(4));
}
ret = intel_scu_ipc_iowrite8(CHRLEDCTRL, ctrldata);
if (ret) {
LED_err(" IPC Failed to write %d\n", ret);
}
ret = intel_scu_ipc_ioread8(CHRLEDCTRL, &ctrldata);
if (ret) {
LED_err(" IPC Failed to read %d\n", ret);
}
LED_info("%s, enable blink and value=%d, register pwmdata=0x%x, ctrldata=0x%x\n", __func__, value, pwmdata, ctrldata);
}else
LED_info("%s, incorrect pwm value:%d (0-100).\n", __func__, value);
#ifdef CONTROL_LED
}
#endif
return count;
}
static
void jdi_cmd_controller_init(
struct mdfld_dsi_config *dsi_config)
{
struct mdfld_dsi_hw_context *hw_ctx =
&dsi_config->dsi_hw_context;
#ifdef ENABLE_CSC_GAMMA /*FIXME*/
struct drm_device *dev = dsi_config->dev;
struct csc_setting csc = {
.pipe = 0,
.type = CSC_REG_SETTING,
.enable_state = true,
.data_len = CSC_REG_COUNT,
.data.csc_reg_data = {
0xFFB0424, 0xFDF, 0x4320FF1,
0xFDC, 0xFF50FF5, 0x415}
};
struct gamma_setting gamma = {
.pipe = 0,
.type = GAMMA_REG_SETTING,
.enable_state = true,
.data_len = GAMMA_10_BIT_TABLE_COUNT,
.gamma_tableX100 = {
0x000000, 0x030303, 0x050505, 0x070707,
0x090909, 0x0C0C0C, 0x0E0E0E, 0x101010,
0x121212, 0x141414, 0x171717, 0x191919,
0x1B1B1B, 0x1D1D1D, 0x1F1F1F, 0x212121,
0x232323, 0x252525, 0x282828, 0x2A2A2A,
0x2C2C2C, 0x2E2E2E, 0x303030, 0x323232,
0x343434, 0x363636, 0x383838, 0x3A3A3A,
0x3C3C3C, 0x3E3E3E, 0x404040, 0x424242,
0x444444, 0x464646, 0x484848, 0x4A4A4A,
0x4C4C4C, 0x4E4E4E, 0x505050, 0x525252,
0x545454, 0x565656, 0x585858, 0x5A5A5A,
0x5C5C5C, 0x5E5E5E, 0x606060, 0x626262,
0x646464, 0x666666, 0x686868, 0x6A6A6A,
0x6C6C6C, 0x6E6E6E, 0x707070, 0x727272,
0x747474, 0x767676, 0x787878, 0x7A7A7A,
0x7C7C7C, 0x7E7E7E, 0x808080, 0x828282,
0x848484, 0x868686, 0x888888, 0x8A8A8A,
0x8C8C8C, 0x8E8E8E, 0x909090, 0x929292,
0x949494, 0x969696, 0x989898, 0x999999,
0x9B9B9B, 0x9D9D9D, 0x9F9F9F, 0xA1A1A1,
0xA3A3A3, 0xA5A5A5, 0xA7A7A7, 0xA9A9A9,
0xABABAB, 0xADADAD, 0xAFAFAF, 0xB1B1B1,
0xB3B3B3, 0xB5B5B5, 0xB6B6B6, 0xB8B8B8,
0xBABABA, 0xBCBCBC, 0xBEBEBE, 0xC0C0C0,
0xC2C2C2, 0xC4C4C4, 0xC6C6C6, 0xC8C8C8,
0xCACACA, 0xCCCCCC, 0xCECECE, 0xCFCFCF,
0xD1D1D1, 0xD3D3D3, 0xD5D5D5, 0xD7D7D7,
0xD9D9D9, 0xDBDBDB, 0xDDDDDD, 0xDFDFDF,
0xE1E1E1, 0xE3E3E3, 0xE4E4E4, 0xE6E6E6,
0xE8E8E8, 0xEAEAEA, 0xECECEC, 0xEEEEEE,
0xF0F0F0, 0xF2F2F2, 0xF4F4F4, 0xF6F6F6,
0xF7F7F7, 0xF9F9F9, 0xFBFBFB, 0xFDFDFD}
};
#endif
PSB_DEBUG_ENTRY("\n");
/*reconfig lane configuration*/
dsi_config->lane_count = 3;
dsi_config->lane_config = MDFLD_DSI_DATA_LANE_4_0;
/* FIXME: enable CSC and GAMMA */
/*dsi_config->enable_gamma_csc = ENABLE_GAMMA | ENABLE_CSC;*/
/* This is for 400 mhz. Set it to 0 for 800mhz */
hw_ctx->cck_div = 1;
hw_ctx->pll_bypass_mode = 0;
if (IS_ANN(dev)) {
hw_ctx->mipi_control = 0x18;
hw_ctx->intr_en = 0xFFFFFFFF;
hw_ctx->hs_tx_timeout = 0xFFFFFF;
hw_ctx->lp_rx_timeout = 0xFFFFFF;
hw_ctx->device_reset_timer = 0xff;
hw_ctx->turn_around_timeout = 0xffff;
hw_ctx->high_low_switch_count = 0x20;
hw_ctx->clk_lane_switch_time_cnt = 0x21000e;
hw_ctx->lp_byteclk = 0x4;
hw_ctx->dphy_param = 0x1b104315;
hw_ctx->eot_disable = 0x1;
hw_ctx->init_count = 0x7d0;
hw_ctx->dbi_bw_ctrl = 1390;
hw_ctx->hs_ls_dbi_enable = 0x0;
hw_ctx->dsi_func_prg = ((DBI_DATA_WIDTH_OPT2 << 13) |
dsi_config->lane_count);
hw_ctx->mipi = SEL_FLOPPED_HSTX | PASS_FROM_SPHY_TO_AFE |
BANDGAP_CHICKEN_BIT | TE_TRIGGER_GPIO_PIN;
} else {
hw_ctx->mipi_control = 0x0;
hw_ctx->intr_en = 0xFFFFFFFF;
hw_ctx->hs_tx_timeout = 0xFFFFFF;
hw_ctx->lp_rx_timeout = 0xFFFFFF;
hw_ctx->device_reset_timer = 0xffff;
hw_ctx->turn_around_timeout = 0x1a;
hw_ctx->high_low_switch_count = 0x21;
hw_ctx->clk_lane_switch_time_cnt = 0x21000f;
hw_ctx->lp_byteclk = 0x5;
hw_ctx->dphy_param = 0x25155b1e;
hw_ctx->eot_disable = 0x3;
hw_ctx->init_count = 0xf0;
hw_ctx->dbi_bw_ctrl = 1390;
hw_ctx->hs_ls_dbi_enable = 0x0;
hw_ctx->dsi_func_prg = ((DBI_DATA_WIDTH_OPT2 << 13) |
dsi_config->lane_count);
hw_ctx->mipi = PASS_FROM_SPHY_TO_AFE |
BANDGAP_CHICKEN_BIT |
TE_TRIGGER_GPIO_PIN;
}
hw_ctx->video_mode_format = 0xf;
#ifdef ENABLE_CSC_GAMMA /*FIXME*/
if (dsi_config->enable_gamma_csc & ENABLE_CSC) {
/* setting the tuned csc setting */
drm_psb_enable_color_conversion = 1;
mdfld_intel_crtc_set_color_conversion(dev, &csc);
}
if (dsi_config->enable_gamma_csc & ENABLE_GAMMA) {
/* setting the tuned gamma setting */
drm_psb_enable_gamma = 1;
mdfld_intel_crtc_set_gamma(dev, &gamma);
}
#endif
}
static
int jdi_cmd_panel_connection_detect(
struct mdfld_dsi_config *dsi_config)
{
int status;
int pipe = dsi_config->pipe;
PSB_DEBUG_ENTRY("\n");
if (pipe == 0) {
status = MDFLD_DSI_PANEL_CONNECTED;
} else {
DRM_INFO("%s: do NOT support dual panel\n",
__func__);
status = MDFLD_DSI_PANEL_DISCONNECTED;
}
return status;
}
static
int jdi_cmd_power_on(
struct mdfld_dsi_config *dsi_config)
{
struct mdfld_dsi_pkg_sender *sender =
mdfld_dsi_get_pkg_sender(dsi_config);
int err = 0;
PSB_DEBUG_ENTRY("\n");
if (!sender) {
DRM_ERROR("Failed to get DSI packet sender\n");
return -EINVAL;
}
err = mdfld_dsi_send_mcs_short_hs(sender,
set_address_mode, 0x0, 1,
MDFLD_DSI_SEND_PACKAGE);
if (err) {
DRM_ERROR("%s: %d: Set Address Mode\n",
__func__, __LINE__);
goto power_err;
}
usleep_range(20000, 20100);
err = mdfld_dsi_send_mcs_short_hs(sender,
set_pixel_format, 0x77, 1,
MDFLD_DSI_SEND_PACKAGE);
if (err) {
DRM_ERROR("%s: %d: Set Pixel format\n",
__func__, __LINE__);
goto power_err;
}
/*turn on display*/
err = mdfld_dsi_send_dcs(sender,
set_display_on,
NULL,
0,
CMD_DATA_SRC_SYSTEM_MEM,
MDFLD_DSI_SEND_PACKAGE);
if (err) {
DRM_ERROR("faild to set_display_on mode\n");
goto power_err;
}
usleep_range(20000, 20100);
power_err:
return err;
}
static void __vpro2_power_ctrl(bool on)
{
u8 addr, value;
addr = 0xad;
if (intel_scu_ipc_ioread8(addr, &value))
DRM_ERROR("%s: %d: failed to read vPro2\n",
__func__, __LINE__);
/* Control vPROG2 power rail with 2.85v. */
if (on)
value |= 0x1;
else
value &= ~0x1;
if (intel_scu_ipc_iowrite8(addr, value))
DRM_ERROR("%s: %d: failed to write vPro2\n",
__func__, __LINE__);
}
static int m10mo_power_ctrl(struct v4l2_subdev *sd, int flag)
{
int ret = 0;
pr_info("M10MO power control. flag=%d\n", flag);
if(Read_PROJ_ID() != PROJ_ID_ZX550ML){
pr_err("M10MO, this is not ZX550ML, break! \n");
return -1;
}
set_flis_value(0x3221, 0x2D18);
#ifdef CONFIG_CRYSTAL_COVE
if (flag) {
ret = intel_mid_pmic_writeb(VPROG_2P8V, VPROG_ENABLE);
if (ret) {
pr_err("Failed to power on V2P8SX.\n");
return ret;
}
ret = intel_mid_pmic_writeb(VPROG_1P2V, VPROG_ENABLE);
if (ret) {
pr_err("Failed to power on V1P2SX.\n");
/* Turn all powers off if one is failed. */
intel_mid_pmic_writeb(VPROG_2P8V, VPROG_DISABLE);
return ret;
}
/* Wait for 8ms to make all the power supplies to be stable. */
usleep_range(8000, 8000);
} else {
/* Turn all powers off even when some are failed. */
if (intel_mid_pmic_writeb(VPROG_2P8V, VPROG_DISABLE))
pr_err("Failed to power off V2P8SX.\n");
if (intel_mid_pmic_writeb(VPROG_1P2V, VPROG_DISABLE))
pr_err("Failed to power off V1P2SX.\n");
}
#else
if (camera_1p2_en < 0) {
lnw_gpio_set_alt(55, LNW_GPIO);
ret = camera_sensor_gpio(55,"INT_CAM_1V2_EN", GPIOF_DIR_OUT, 0);
if (ret < 0){
printk("camera_1p2_en is not available.\n");
return ret;
}
camera_1p2_en = ret;
printk(KERN_INFO "M10MO, gpio number, camera_1p2_en is %d\n", camera_1p2_en);
}
switch (Read_HW_ID()) {
case HW_ID_EVB:
case HW_ID_SR1:
case HW_ID_SR2:
case HW_ID_ER:
case HW_ID_ER1_1:
case HW_ID_ER1_2:
case HW_ID_PR:
case HW_ID_pre_PR:
case HW_ID_MP:
if (camera_3p3_en2 < 0) {
gpio_free(58);/////// temp WA.
lnw_gpio_set_alt(58, LNW_GPIO);
ret = camera_sensor_gpio(58, "3X_I2C_LED", GPIOF_DIR_OUT, 0);
if (ret < 0){
printk("GPIO58 is not available.\n");
}else{
camera_3p3_en2 = ret;
printk(KERN_INFO "M10MO, gpio number, camera_3p3_en2 is %d\n", camera_3p3_en2);
}
}
break;
default:
if (camera_3p3_en2 < 0) {
gpio_free(54);/////// temp WA.
lnw_gpio_set_alt(54, LNW_GPIO);
ret = camera_sensor_gpio(54, "3X_I2C_LED", GPIOF_DIR_OUT, 0);
if (ret < 0){
printk("GPIO54 is not available.\n");
}else{
camera_3p3_en2 = ret;
printk(KERN_INFO "M10MO, gpio number, camera_3p3_en2 is %d\n", camera_3p3_en2);
}
}
break;
}//switch
if (camera_2p8_en < 0) {
lnw_gpio_set_alt(56, LNW_GPIO);
ret = camera_sensor_gpio(56,"INT_CAM_2V8_EN", GPIOF_DIR_OUT, 0);
if (ret < 0){
printk("camera_2p8_en not available.\n");
return ret;
}
camera_2p8_en = ret;
printk(KERN_INFO "M10MO, gpio number, camera_2p8_en is %d\n", camera_2p8_en);
}
if (flag) {
/*
static int camera_1p2_en = -1;
static int camera_2p8_en = -1;
static int camera_isp_1p2_en = -1;
*/
if(camera_1p2_en > 0){
printk("@%s %d, project zx550ml pull up GPIO%d\n", __func__, __LINE__, camera_1p2_en);
gpio_set_value(camera_1p2_en, 1);
}
#if 0
ret = intel_scu_ipc_iowrite8(MSIC_VPROG2_MRFLD_CTRL, MSIC_VPROG2_ON_1P8);
if (ret) {
pr_err("Failed to power on M10MO MSIC_VPROG2_ON_1P8.\n");
return ret;
}
#endif
if(camera_3p3_en2 > 0){
mdelay(1);
printk("@%s %d, project zx550ml pull up GPIO%d\n", __func__, __LINE__, camera_3p3_en2);
gpio_set_value(camera_3p3_en2, 1);
}
mdelay(1);
ret = intel_scu_ipc_iowrite8(MSIC_VPROG1_MRFLD_CTRL, MSIC_VPROG1_ON_1P8);
if (ret) {
pr_err("Failed to power on M10MO MSIC_VPROG1_ON_1P8.\n");
return ret;
}else{
printk("@%s %d, project zx550ml pull up Vprog1, 1.8V \n", __func__, __LINE__);
}
if(camera_2p8_en > 0){
printk("@%s %d, project zx550ml pull up GPIO%d\n", __func__, __LINE__, camera_2p8_en);
gpio_set_value(camera_2p8_en, 1);
}
/* Wait for 8ms to make all the power supplies to be stable. */
usleep_range(8000, 8000);
} else {
/*
static int camera_1p2_en = -1;
static int camera_2p8_en = -1;
static int camera_isp_1p2_en = -1;
*/
ret = intel_scu_ipc_iowrite8(MSIC_VPROG1_MRFLD_CTRL, MSIC_VPROG1_OFF);
if (ret) {
pr_err("Failed to power off M10MO MSIC_VPROG1_ON_2P8.\n");
return ret;
}
gpio_set_value(camera_2p8_en, 0);
camera_sensor_gpio_free(camera_2p8_en);
camera_2p8_en = -1;
gpio_set_value(camera_1p2_en, 0);
camera_sensor_gpio_free(camera_1p2_en);
camera_1p2_en = -1;
gpio_set_value(camera_3p3_en2, 0);
camera_sensor_gpio_free(camera_3p3_en2);
camera_3p3_en2 = -1;
camera_sensor_gpio_free(camera_reset);
camera_reset = -1;
}
#endif
return ret;
}
static int sn95031_write(void *ctx, unsigned int reg, unsigned int value)
{
return intel_scu_ipc_iowrite8(reg, value);
}
static void intel_led_set(struct led_classdev *led_cdev,
enum led_brightness value)
{
int ret;
int ret2;
uint8_t data_led;
if(!led_update){
return;
}
if(!LED_for_old_HW && !LED_for_new_HW)
return;
mutex_lock(&led_mutex);
switch (value) {
case 0: // off
if(LED_for_old_HW){
ret = intel_scu_ipc_iowrite8(CHRLEDPWM, 0x00); //duty_cycle = 0
ret = intel_scu_ipc_iowrite8(CHRLEDCTRL, 0x36); // led disable
}else if (LED_for_new_HW){
ret = intel_scu_ipc_iowrite8(CHRLEDPWM, 0xff); //duty_cycle = 0
ret = intel_scu_ipc_iowrite8(CHRLEDCTRL, 0x34); // led disable
}
gpio_set_value(LED_RED_GPIO, 0);
gpio_set_value(LED_GREEN_GPIO, 0);
break;
case 1: //red led
case 2: //green led
case 3: //orange led
if(LED_for_old_HW){
if((led_cdev -> blink_delay_on + led_cdev -> blink_delay_off) == 4000){//4s
data_led = (uint8_t)((255 * led_cdev -> blink_delay_on)/4000);
ret = intel_scu_ipc_iowrite8(CHRLEDPWM, data_led);
ret = intel_scu_ipc_iowrite8(CHRLEDCTRL, 0x27);
}
else if((led_cdev -> blink_delay_on + led_cdev -> blink_delay_off) == 2000){//2s
data_led = (uint8_t)((255 * led_cdev -> blink_delay_on)/2000);
ret = intel_scu_ipc_iowrite8(CHRLEDPWM, data_led);
ret = intel_scu_ipc_iowrite8(CHRLEDCTRL, 0x2f);
}
else{
ret = intel_scu_ipc_iowrite8(CHRLEDPWM, 0xff); //duty_cycle = 100
ret = intel_scu_ipc_iowrite8(CHRLEDCTRL, 0x37);
}
}else if (LED_for_new_HW){
if((led_cdev -> blink_delay_on + led_cdev -> blink_delay_off) == 4000){//4s
data_led = (uint8_t)((255 * led_cdev -> blink_delay_off)/4000);
ret = intel_scu_ipc_iowrite8(CHRLEDPWM, data_led);
ret = intel_scu_ipc_iowrite8(CHRLEDCTRL, 0x25);
}
else if((led_cdev -> blink_delay_on + led_cdev -> blink_delay_off) == 2000){//2s
data_led = (uint8_t)((255 * led_cdev -> blink_delay_off)/2000);
ret = intel_scu_ipc_iowrite8(CHRLEDPWM, data_led);
ret = intel_scu_ipc_iowrite8(CHRLEDCTRL, 0x2d);
}
else{
ret = intel_scu_ipc_iowrite8(CHRLEDPWM, 0x00); //duty_cycle = 100
ret = intel_scu_ipc_iowrite8(CHRLEDCTRL, 0x35);
}
}
if(value == 1){
gpio_set_value(LED_RED_GPIO,1);
gpio_set_value(LED_GREEN_GPIO, 0);
}else if(value == 2){
gpio_set_value(LED_RED_GPIO,0);
gpio_set_value(LED_GREEN_GPIO, 1);
}else if (value ==3){
gpio_set_value(LED_RED_GPIO,1);
gpio_set_value(LED_GREEN_GPIO, 1);
}
break;
default :
break;
}
//debug information
if(1){
printk("[LED SET] brightness = %d blink_delay_on = %d blink_delay_off = %d \n",value,led_cdev -> blink_delay_on,
led_cdev -> blink_delay_off);
ret2 = intel_scu_ipc_ioread8(CHRLEDPWM, &data_led);
printk("[LED]: Read CHRLEDPWM = %02X ret = %d\n",data_led,ret2);
ret2 = intel_scu_ipc_ioread8(CHRLEDCTRL, &data_led);
printk("[LED]: Read CHRLEDCTRL = %02X ret = %d\n",data_led,ret2);
}
mutex_unlock(&led_mutex);
}
static inline int gpadc_write(u16 addr, u8 data)
{
return intel_scu_ipc_iowrite8(addr, data);
}
static void pmic_dump_registers(int dump_mask)
{
int i, retval = 0, ret;
uint8_t reg_val;
uint16_t chk_reg_addr;
uint16_t reg_addr_boot[] = {MSIC_BATT_RESETIRQ1_ADDR,
MSIC_BATT_RESETIRQ2_ADDR, MSIC_BATT_CHR_LOWBATTDET_ADDR,
MSIC_BATT_CHR_SPCHARGER_ADDR, MSIC_BATT_CHR_CHRTTIME_ADDR,
MSIC_BATT_CHR_CHRCTRL1_ADDR, MSIC_BATT_CHR_CHRSTWDT_ADDR,
MSIC_BATT_CHR_CHRSAFELMT_ADDR};
char *reg_str_boot[] = {"rirq1", "rirq2", "lowdet",
"spchr", "chrtime", "chrctrl1",
"chrgwdt", "safelmt"};
uint16_t reg_addr_int[] = {MSIC_BATT_CHR_PWRSRCINT_ADDR,
MSIC_BATT_CHR_PWRSRCINT1_ADDR, MSIC_BATT_CHR_CHRINT_ADDR,
MSIC_BATT_CHR_CHRINT1_ADDR, MSIC_BATT_CHR_PWRSRCLMT_ADDR};
char *reg_str_int[] = {"pwrint", "pwrint1", "chrint",
"chrint1", "pwrsrclmt"};
uint16_t reg_addr_evt[] = {MSIC_BATT_CHR_CHRCTRL_ADDR,
MSIC_BATT_CHR_CHRCVOLTAGE_ADDR, MSIC_BATT_CHR_CHRCCURRENT_ADDR,
MSIC_BATT_CHR_SPWRSRCINT_ADDR, MSIC_BATT_CHR_SPWRSRCINT1_ADDR,
CHR_STATUS_FAULT_REG};
char *reg_str_evt[] = {"chrctrl", "chrcv", "chrcc",
"spwrsrcint", "sprwsrcint1", "chrflt"};
uint16_t reg_addr_others[] = {MSIC_BATT_CHR_MPWRSRCINT_ADDR,
MSIC_BATT_CHR_MPWRSRCINT1_ADDR, MSIC_BATT_CHR_MCHRINT_ADDR,
MSIC_BATT_CHR_MCHRINT1_ADDR, MSIC_BATT_CHR_VBUSDET_ADDR,
MSIC_BATT_CHR_WDTWRITE_ADDR};
char *reg_str_others[] = {"chrmpwrsrcint", "chrmpwrsrcint1", "chrmchrint",
"chrmchrint1", "chrvbusdet", "chrwdtwrite"};
if (dump_mask & MSIC_CHRG_REG_DUMP_BOOT) {
for (i = 0; i < ARRAY_SIZE(reg_addr_boot); i++) {
retval = intel_scu_ipc_ioread8(reg_addr_boot[i], ®_val);
if (retval) {
chk_reg_addr = reg_addr_boot[i];
goto ipcread_err;
}
BAT_DBG("PMIC(0x%03x)\tval: " BYTETOBINARYPATTERN "\t%s\n", reg_addr_boot[i],
BYTETOBINARY(reg_val), reg_str_boot[i]);
}
}
if (dump_mask & MSIC_CHRG_REG_DUMP_INT) {
for (i = 0; i < ARRAY_SIZE(reg_addr_int); i++) {
retval = intel_scu_ipc_ioread8(reg_addr_int[i], ®_val);
if (retval) {
chk_reg_addr = reg_addr_int[i];
goto ipcread_err;
}
BAT_DBG("PMIC(0x%03x)\tval: " BYTETOBINARYPATTERN "\t%s\n", reg_addr_int[i],
BYTETOBINARY(reg_val), reg_str_int[i]);
}
}
if (dump_mask & MSIC_CHRG_REG_DUMP_EVENT) {
for (i = 0; i < ARRAY_SIZE(reg_addr_evt); i++) {
retval = intel_scu_ipc_ioread8(reg_addr_evt[i], ®_val);
if (retval) {
chk_reg_addr = reg_addr_evt[i];
goto ipcread_err;
}
BAT_DBG("PMIC(0x%03x)\tval: " BYTETOBINARYPATTERN "\t%s\n", reg_addr_evt[i],
BYTETOBINARY(reg_val), reg_str_evt[i]);
}
}
if (dump_mask & MSIC_CHRG_REG_DUMP_OTHERS) {
for (i = 0; i < ARRAY_SIZE(reg_addr_others); i++) {
retval = intel_scu_ipc_ioread8(reg_addr_others[i], ®_val);
if (retval) {
chk_reg_addr = reg_addr_others[i];
goto ipcread_err;
}
BAT_DBG("PMIC(0x%03x)\t val: " BYTETOBINARYPATTERN "\t%s\n", reg_addr_others[i],
BYTETOBINARY(reg_val), reg_str_others[i]);
}
}
/*modify MSIC_BATT_CHR_LOWBATTDET_ADDR values [7:6]='11'*/
intel_scu_ipc_ioread8(MSIC_BATT_CHR_LOWBATTDET_ADDR, ®_val);
reg_val |= (BIT(6)|BIT(7));
ret = intel_scu_ipc_iowrite8(MSIC_BATT_CHR_LOWBATTDET_ADDR, reg_val);
if (ret) {
BAT_DBG_E("PMIC register MSIC_BATT_CHR_LOWBATTDET_ADDR Failed to write %d\n", ret);
}else {
intel_scu_ipc_ioread8(MSIC_BATT_CHR_LOWBATTDET_ADDR, ®_val);
BAT_DBG("PMIC register 0x%x Success to write 0x%x.\n", MSIC_BATT_CHR_LOWBATTDET_ADDR, reg_val);
}
return;
ipcread_err:
BAT_DBG("ipcread_err: address: 0x%03x!!!", chk_reg_addr);
}
bool ps_hdmi_power_rails_on(void)
{
int ret = 0;
pr_debug("Entered %s\n", __func__);
if (vrint_data == 0) {
/* If it is not invoked in response to hot plug event,
* then simply a NOP as power rails are never turned off.
*/
pr_debug("%s: NOP as there is no HPD.\n", __func__);
return true;
}
/* Turn on HDMI power rails. These will be on in all non-S0iX
* states so that HPD and connection status will work. VCC330
* will have ~1.7mW usage during idle states when the display
* is active
*/
ret = intel_scu_ipc_iowrite8(PS_MSIC_VCC330CNT, PS_VCC330_ON);
if (ret) {
pr_debug("%s: Failed to power on VCC330.\n", __func__);
return false;
}
if (vrint_data & PS_HDMI_OCP_STATUS) {
/* When there occurs overcurrent in MSIC HDMI HDP,
* need to reset VHDMIEN by clearing to 0 then set to 1
*/
ret = intel_scu_ipc_iowrite8(PS_MSIC_VHDMICNT,
PS_VHDMI_OFF);
if (ret) {
pr_debug("%s: Failed to power off VHDMI.\n", __func__);
goto err;
}
vrint_data = 0;
}
/* MSIC documentation requires that there be a 500us
* delay after enabling VCC330 before you can enable
* VHDMI
*/
usleep_range(500, 1000);
/* Extend VHDMI switch de-bounce time, to avoid
* redundant MSIC VREG/HDMI interrupt during HDMI
* cable plugged in/out
*/
ret = intel_scu_ipc_iowrite8(PS_MSIC_VHDMICNT,
PS_VHDMI_ON |
PS_VHDMI_DB_30MS);
if (ret) {
pr_debug("%s: Failed to power on VHDMI.\n", __func__);
goto err;
}
return true;
err:
ret = intel_scu_ipc_iowrite8(PS_MSIC_VCC330CNT, PS_VCC330_OFF);
if (ret) {
pr_debug("%s: Failed to power off VCC330 during clean up.\n",
__func__);
/* Fall through */
}
return false;
}
otm_hdmi_ret_t ps_hdmi_pci_dev_init(void *context, struct pci_dev *pdev)
{
otm_hdmi_ret_t rc = OTM_HDMI_SUCCESS;
int result = 0;
unsigned int vdc_start;
uint32_t pci_address = 0;
uint8_t pci_dev_revision = 0;
hdmi_context_t *ctx = NULL;
if (pdev == NULL || context == NULL) {
rc = OTM_HDMI_ERR_INTERNAL;
goto exit;
}
ctx = (hdmi_context_t *)context;
pr_debug("get resource start\n");
result = pci_read_config_dword(pdev, 16, &vdc_start);
if (result != 0) {
rc = OTM_HDMI_ERR_FAILED;
goto exit;
}
pci_address = vdc_start + PS_VDC_OFFSET;
pr_debug("map IO region\n");
/* Map IO region and save its length */
ctx->io_length = PS_VDC_SIZE;
ctx->io_address = ioremap(pci_address, ctx->io_length);
if (!ctx->io_address) {
rc = OTM_HDMI_ERR_FAILED;
goto exit;
}
pr_debug("get PCI dev revision\n");
result = pci_read_config_byte(pdev, 8, &pci_dev_revision);
if (result != 0) {
rc = OTM_HDMI_ERR_FAILED;
goto exit;
}
ctx->dev.id = pci_dev_revision;
/* Store this context for use by MSIC PCI driver */
g_context = ctx;
ctx->is_connected_overridden = true;
/* Handle Merrifield specific GPIO configuration
* to enable EDID reads
*/
ctx->gpio_hpd_pin = get_gpio_by_name(PS_MSIC_HPD_GPIO_PIN_NAME);
if (-1 == ctx->gpio_hpd_pin) {
ctx->gpio_hpd_pin = PS_MSIC_HPD_GPIO_PIN;
pr_debug("get_gpio_by_name failed! Use default pin %d\n",
PS_MSIC_HPD_GPIO_PIN);
}
ctx->gpio_ls_en_pin = get_gpio_by_name(PS_MSIC_LS_EN_GPIO_PIN_NAME);
if (-1 == ctx->gpio_ls_en_pin) {
ctx->gpio_ls_en_pin = PS_MSIC_LS_EN_GPIO_PIN;
pr_debug("get_gpio_by_name failed! Use default pin %d\n",
PS_MSIC_LS_EN_GPIO_PIN);
}
if (gpio_request(ctx->gpio_ls_en_pin, "HDMI_LS_EN")) {
pr_err("%s: Unable to request gpio %d\n", __func__,
ctx->gpio_ls_en_pin);
rc = OTM_HDMI_ERR_FAILED;
goto exit;
}
if (!gpio_is_valid(ctx->gpio_ls_en_pin)) {
pr_err("%s: Unable to validate gpio %d\n", __func__,
ctx->gpio_ls_en_pin);
rc = OTM_HDMI_ERR_FAILED;
goto exit;
}
/* on moorefield V0 platform, HDMI_LS_EN is driven from SHADYCOVE PMIC */
if (INTEL_MID_BOARD(2, PHONE, MOFD, V0, PRO)) {
pr_debug("configure MSIC GPIO0(HDMI_LS_EN) for MOOREFIELD V0 \
o/p=1 pu=50k pu/pd=enabled od=1 dir=ouptut\n");
result = intel_scu_ipc_iowrite8(PMIC_GPIO0_CTRL_REG_OFST, PMIC_GPIO0_CFG_VAL);
if(result != 0) {
pr_err("%s failed to configure GPIO0(HDMI_LS_EN)\n",__func__);
rc = OTM_HDMI_ERR_FAILED;
goto exit;
}
}
/*
* The camera_v1p8_en gpio pin is to enable 1.8v power.
*/
static int ov5670_power_ctrl(struct v4l2_subdev *sd, int flag)
{
int ret = 0;
printk("@%s PROJECT_ID = 0x%x, HW_ID = 0x%x\n", __func__, Read_PROJ_ID(), Read_HW_ID());
if (camera_1p2_en < 0) {
ret = camera_sensor_gpio(-1,"INT_CAM_1V2_EN", GPIOF_DIR_OUT, 0);
if (ret < 0){
printk("camera_1p2_en not available.\n");
return ret;
}
camera_1p2_en = ret;
printk(KERN_INFO "ov5670, gpio number, camera_1p2_en is %d\n", camera_1p2_en);
}
if (camera_2v8 < 0) {
ret = camera_sensor_gpio(-1, "INT_CAM_2V8_EN", GPIOF_DIR_OUT, 0);
if (ret < 0){
printk("INT_CAM_2V8_EN not available.\n");
return ret;
}
camera_2v8 = ret;
printk("<< camera_2v8:%d, flag:%d\n", camera_2v8, flag);
}
if (flag) {
switch (Read_PROJ_ID()) {
case PROJ_ID_ZE550ML:
case PROJ_ID_ZE551ML:
case PROJ_ID_ZR550ML:
case PROJ_ID_ZX550ML:
switch (Read_HW_ID()) {
case HW_ID_EVB:
pr_info("Hardware VERSION = EVB, ov5670 does not support.\n");
break;
case HW_ID_SR1:
case HW_ID_SR2:
case HW_ID_ER:
case HW_ID_ER1_1:
case HW_ID_ER1_2:
case HW_ID_PR:
case HW_ID_pre_PR:
case HW_ID_MP:
pr_info("ov5670 --> HW_ID = 0x%x\n", Read_HW_ID());
//turn on power 2.8V
if (camera_2v8 >= 0){
gpio_set_value(camera_2v8, 1);
printk(KERN_ALERT "ov5670 <<< camera_2v8 = 1\n");
}
//turn on power 1.8V
if (!camera_vprog2_on) {
camera_vprog2_on = 1;
ret = intel_scu_ipc_iowrite8(MSIC_VPROG2_MRFLD_CTRL, MSIC_VPROG2_ON_1P8);
if (ret){
printk(KERN_INFO "set vprog2 fails\n");
return -1;
}
msleep(1);
}
break;
default:
pr_info("ov5670 --> HW_ID 0x%x is not defined\n", Read_HW_ID());
break;
}
break;
case PROJ_ID_ZE500ML:
switch (Read_HW_ID()) {
case HW_ID_EVB:
pr_info("ov5670 --> HW_ID = 0x%x\n", Read_HW_ID());
//turn on power 1.8V
if (!camera_vprog2_on) {
camera_vprog2_on = 1;
ret = intel_scu_ipc_iowrite8(MSIC_VPROG2_MRFLD_CTRL, MSIC_VPROG2_ON_1P8);
if (ret){
printk(KERN_INFO "set vprog2 fails\n");
return -1;
}
msleep(1);
}
//turn on power 2.8V
if (!camera_vprog1_on) {
camera_vprog1_on = 1;
intel_scu_ipc_iowrite8(MSIC_VPROG1_MRFLD_CTRL ,MSIC_VPROG1_ON_2P8);
if (ret){
printk(KERN_INFO "set vprog1 fails\n");
return -1;
}
msleep(1);
}
break;
case HW_ID_SR1:
case HW_ID_SR2:
case HW_ID_ER:
case HW_ID_pre_PR:
case HW_ID_PR:
case HW_ID_MP:
pr_info("HW_ID 0x%x, ov5670 does not support.\n", Read_HW_ID());
break;
default:
pr_info("ov5670 --> HW_ID 0x%x is not defined\n", Read_HW_ID());
break;
}
break;
default:
pr_info("Project ID is not defined\n");
break;
}//end switch
//turn on power 1.2V
gpio_set_value(camera_1p2_en, 1);
printk(KERN_INFO "ov5670---camera_1p2_en is %d\n", camera_1p2_en);
usleep_range(10000, 11000);
//flag == 0
} else {
//turn OFF power 1.2V
gpio_set_value(camera_1p2_en, 0);
gpio_free(camera_1p2_en);
camera_1p2_en = -1;
switch (Read_PROJ_ID()) {
case PROJ_ID_ZE550ML:
case PROJ_ID_ZE551ML:
case PROJ_ID_ZR550ML:
case PROJ_ID_ZX550ML:
switch (Read_HW_ID()) {
case HW_ID_EVB:
pr_info("Hardware VERSION = EVB, ov5670 does not support.\n");
break;
case HW_ID_SR1:
case HW_ID_SR2:
case HW_ID_ER:
case HW_ID_ER1_1:
case HW_ID_ER1_2:
case HW_ID_PR:
case HW_ID_pre_PR:
case HW_ID_MP:
pr_info("ov5670 --> HW_ID = 0x%x\n", Read_HW_ID());
//turn off power 2.8V
if (camera_2v8 >= 0){
gpio_set_value(camera_2v8, 0);
gpio_free(camera_2v8);
camera_2v8 = -1;
printk("<<< camera_2v8 = 0\n");
}
break;
default:
pr_info("ov5670 --> HW_ID is not defined\n");
break;
}
break;
case PROJ_ID_ZE500ML:
switch (Read_HW_ID()) {
case HW_ID_EVB:
pr_info("ov5670 --> HW_ID = 0x%x\n", Read_HW_ID());
//turn off power 2.8V
if (camera_vprog1_on) {
camera_vprog1_on = 0;
ret = intel_scu_ipc_iowrite8(MSIC_VPROG1_MRFLD_CTRL, MSIC_VPROG1_OFF);
if (ret) {
printk(KERN_ALERT "Failed to disable regulator vprog1\n");
return ret;
}
printk("<<< 2.8V = 0\n");
}
break;
case HW_ID_SR1:
case HW_ID_SR2:
case HW_ID_ER:
case HW_ID_PR:
case HW_ID_pre_PR:
case HW_ID_MP:
pr_info("HW_ID 0x%x, ov5670 does not support.\n", Read_HW_ID());
break;
default:
pr_info("ov5670 --> HW_ID is not defined\n");
break;
}
break;
default:
pr_info("Project ID is not defined\n");
break;
}//end switch
//turn off power 1.8V
if (camera_vprog2_on) {
camera_vprog2_on = 0;
ret = intel_scu_ipc_iowrite8(MSIC_VPROG2_MRFLD_CTRL, MSIC_VPROG2_OFF);
if (ret) {
printk(KERN_ALERT "Failed to disable regulator vprog2\n");
return ret;
}
printk("<<< 1.8V= 0\n");
}
}//end if
return 0;
}
int intel_scu_ipc_msic_vprog2(int on)
{
return intel_scu_ipc_iowrite8(MSIC_VPROG2_CTRL,
on ? MSIC_VPROG_ON : MSIC_VPROG_OFF);
}
