void ti89_put_byte(uint32_t adr, uint8_t arg) { // RAM access if(IN_BOUNDS(0x000000, adr, 0x1fffff)) { put_b(tihw.ram, adr, RAM_SIZE_TI89 - 1, arg); } // FLASH access else if(IN_BOUNDS(0x200000, adr, 0x5fffff)) { FlashWriteByte(adr, arg); } // memory-mapped I/O else if(IN_BOUNDS(0x600000, adr, 0x6fffff)) { io_put_byte(adr, arg); } // memory-mapped I/O (hw2) else if(IN_RANGE(adr, 0x700000, IO2_SIZE_TI89)) { io2_put_byte(adr, arg); } return; }
void ti89t_put_byte(uint32_t adr, uint8_t arg) { // RAM access if(IN_BOUNDS(0x000000, adr, 0x03ffff) || IN_BOUNDS(0x200000, adr, 0x23ffff) || IN_BOUNDS(0x400000, adr, 0x43ffff)) { put_b(tihw.ram, adr, 0x03ffff, arg); } // FLASH access else if(IN_BOUNDS(0x800000, adr, 0xbfffff)) { FlashWriteByte(adr, arg); } // memory-mapped I/O else if(IN_BOUNDS(0x600000, adr, 0x6fffff)) { io_put_byte(adr, arg); } // memory-mapped I/O (hw2) else if(IN_RANGE(adr, 0x700000, IO2_SIZE_TI89T)) { io2_put_byte(adr, arg); } // memory-mapped I/O (hw3) else if(IN_RANGE(adr, 0x710000, IO3_SIZE_TI89T)) { io3_put_byte(adr, arg); } return; }
void io2_put_word(uint32_t addr, uint16_t arg) { io2_put_byte(addr, MSB(arg)); io2_put_byte(addr+1, LSB(arg)); }