void static rtc_write_burst(int adr, unsigned char *data, int dataLen) { int i; #ifdef DEBUG for (i = 0; i < dataLen; i++) printk(" rtc_write_burst : data=%08x\n", data[i]); #endif DBG(" rtc_write_burst : adr=0x%02x\n", adr); csi1_reset(); while(io_in32(CSI1_MODE) & CSIn_MODE_CSOT); reg_set32(CSI1_MODE, CSIn_MODE_AUTO, SET_32_BIT); reg_set32(CSI1_MODE, CSIn_MODE_TRMD, SET_32_BIT); io_out32(CSI1_INT, CSIn_INT_CSIEND); rtc_set_ce(1); DBG(" rtc_write_burst : CSI1_MODE=%08x\n", io_in32(CSI1_MODE)); DBG(" rtc_write_burst : CSI1_CNT=%08x\n", io_in32(CSI1_CNT)); io_out32(CSI1_SOTBF, ((adr << 4) | 0x00)); for (i = 0; i < dataLen; i++) { io_out32(CSI1_SOTB, data[i]); while(!(io_in32(CSI1_INT) & CSIn_INT_CSIEND)); io_out32(CSI1_INT, CSIn_INT_CSIEND); } while(io_in32(CSI1_MODE) & CSIn_MODE_CSOT); rtc_set_ce(0); }
static inline void pci_write_dword(uint8_t bus, uint8_t dev, uint8_t func, uint8_t reg, uint32_t val) { union pci_address addr; addr.raw = 0; addr.structure.enable = 1; addr.structure.bus = bus; addr.structure.device = dev; addr.structure.function = func; addr.structure.reg = reg & 0xfc; io_out32(&pci_ioaddr, PCI_CONFIG_ADDRESS, addr.raw); io_out32(&pci_ioaddr, PCI_CONFIG_DATA, val); }
void pci_writeconfig(uint32_t bus, uint32_t slot, uint32_t fun, uint32_t off, uint32_t value) { uint32_t address; // enable bit address = (1UL<<31); address |= bus << 16; address |= slot << 11; address |= fun << 8; address |= (off & 0xfc); io_out32(0xcf8, address); io_out32(0xcfc, value); }
void static rtc_read_burst(int adr, unsigned char *data, int dataLen) { int i; DBG(" rtc_read_burst : adr=0x%02x\n", adr); csi1_reset(); while(io_in32(CSI1_MODE) & CSIn_MODE_CSOT); reg_set32(CSI1_MODE, CSIn_MODE_AUTO, CLR_32_BIT); reg_set32(CSI1_MODE, CSIn_MODE_TRMD, SET_32_BIT); io_out32(CSI1_INT, CSIn_INT_CSIEND); rtc_set_ce(1); DBG(" rtc_read_burst : CSI1_MODE=%08x\n", io_in32(CSI1_MODE)); DBG(" rtc_read_burst : CSI1_CNT=%08x\n", io_in32(CSI1_CNT)); io_out32(CSI1_SOTB, (((adr & 0xf) << 4) | 0x04)); while(!(io_in32(CSI1_INT) & CSIn_INT_CSIEND)); while(io_in32(CSI1_MODE) & CSIn_MODE_CSOT); reg_set32(CSI1_MODE, CSIn_MODE_AUTO, SET_32_BIT); reg_set32(CSI1_MODE, CSIn_MODE_TRMD, CLR_32_BIT); io_out32(CSI1_INT, CSIn_INT_CSIEND); udelay(50); DBG(" rtc_read_burst : CSI1_MODE=%08x\n", io_in32(CSI1_MODE)); DBG(" rtc_read_burst : CSI1_CNT=%08x\n", io_in32(CSI1_CNT)); io_in32(CSI1_SIRB); /* dummy read */ //// io_out32(CSI1_INT, CSIn_INT_CSIEND); for (i = 0; i < dataLen; i++) { while(!(io_in32(CSI1_INT) & CSIn_INT_CSIEND)); io_out32(CSI1_INT, CSIn_INT_CSIEND); data[i] = io_in32(CSI1_SIRB); } while(io_in32(CSI1_MODE) & CSIn_MODE_CSOT); rtc_set_ce(0); #ifdef DEBUG for (i = 0; i < dataLen; i++) printk(" rtc_read_burst : data=%08x\n", data[i]); #endif }
static inline uint32_t pci_read_dword(uint8_t bus, uint8_t dev, uint8_t func, uint8_t reg) { union pci_address addr; addr.raw = 0; addr.structure.enable = 1; addr.structure.bus = bus; addr.structure.device = dev; addr.structure.function = func; addr.structure.reg = reg & 0xfc; io_out32(&pci_ioaddr, PCI_CONFIG_ADDRESS, addr.raw); return io_in32(&pci_ioaddr, PCI_CONFIG_DATA); }
uint32_t pci_readconfig(uint32_t bus, uint32_t slot, uint32_t fun, uint32_t off) { uint32_t address; // enable bit address = (1UL<<31); address |= bus << 16; address |= slot << 11; address |= fun << 8; address |= (off & 0xfc); io_out32(0xcf8, address); return io_in32(0xcfc); }
Pci_data_reg pci_read_data(Pci_conf_reg const pcr) { io_out32(PCI_CONFIG_ADDR_PORT, pcr.bit_expr); io_hlt(); Pci_data_reg d = {.bit_expr = io_in32(PCI_CONFIG_DATA_PORT)}; return d; }
static inline void reg_set32(u32 offset, u32 mask, u32 val) { u32 val0 = io_in32(offset); io_out32(offset, (val & mask) | (val0 & ~mask)); }