Example #1
0
static int ip101a_config_init(struct phy_device *phydev)
{
	int c;

	c = ip1xx_reset(phydev);
	if (c < 0)
		return c;

	c = phy_write(phydev, IP101A_IRQ_CONF_STATUS, IP101A_IRQ_DEFAULT);
	if (c < 0)
		return c;

	/* Set the WoL+ with the default configuration */
	phy_write_page(phydev, IP101A_G_WOL_CTRL, 4, IP101A_G_DEFAULT_WOL);
	DBG("IC+101A/G WoL+ crtl register 0x%x\n",
	    phy_read_page(phydev, IP101A_G_WOL_CTRL, 4));

	c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
	if (c < 0)
		return c;

	/* Enable Auto Power Saving mode */
	c |= IP101A_APS_ON;
	c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
	if (c < 0)
		return c;

	return 0;
}
Example #2
0
static int ip1001_config_init(struct phy_device *phydev)
{
	int c;

	c = ip1xx_reset(phydev);
	if (c < 0)
		return c;

	/* Enable Auto Power Saving mode */
	c = phy_read(phydev, IP1001_SPEC_CTRL_STATUS_2);
	if (c < 0)
		return c;
	c |= IP1001_APS_ON;
	c = phy_write(phydev, IP1001_SPEC_CTRL_STATUS_2, c);
	if (c < 0)
		return c;

	if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
		/* Additional delay (2ns) used to adjust RX clock phase
		 * at RGMII interface */
		c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
		if (c < 0)
			return c;

		c |= IP1001_PHASE_SEL_MASK;
		c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
		if (c < 0)
			return c;
	}

	return 0;
}
Example #3
0
static int ip101a_config_init(struct phy_device *phydev)
{
	int c;

	c = ip1xx_reset(phydev);
	if (c < 0)
		return c;

	/* Enable Auto Power Saving mode */
	c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
	c |= IP101A_APS_ON;
	return c;
}
Example #4
0
static int ip1001_config_init(struct phy_device *phydev)
{
	int c;

	c = ip1xx_reset(phydev);
	if (c < 0)
		return c;

	/* Enable Auto Power Saving mode */
	c = phy_read(phydev, IP1001_SPEC_CTRL_STATUS_2);
	if (c < 0)
		return c;
	c |= IP1001_APS_ON;
	c = phy_write(phydev, IP1001_SPEC_CTRL_STATUS_2, c);
	if (c < 0)
		return c;

	return 0;
}
Example #5
0
static int ip101a_g_config_init(struct phy_device *phydev)
{
	struct ip101a_g_phy_priv *priv = phydev->priv;
	int err, c;

	c = ip1xx_reset(phydev);
	if (c < 0)
		return c;

	/* configure the RXER/INTR_32 pin of the 32-pin IP101GR if needed: */
	switch (priv->sel_intr32) {
	case IP101GR_SEL_INTR32_RXER:
		err = phy_modify(phydev, IP101G_DIGITAL_IO_SPEC_CTRL,
				 IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32, 0);
		if (err < 0)
			return err;
		break;

	case IP101GR_SEL_INTR32_INTR:
		err = phy_modify(phydev, IP101G_DIGITAL_IO_SPEC_CTRL,
				 IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32,
				 IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32);
		if (err < 0)
			return err;
		break;

	default:
		/* Don't touch IP101G_DIGITAL_IO_SPEC_CTRL because it's not
		 * documented on IP101A and it's not clear whether this would
		 * cause problems.
		 * For the 32-pin IP101GR we simply keep the SEL_INTR32
		 * configuration as set by the bootloader when not configured
		 * to one of the special functions.
		 */
		break;
	}

	/* Enable Auto Power Saving mode */
	c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
	c |= IP101A_G_APS_ON;

	return phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
}
Example #6
0
static int ip1001_config_init(struct phy_device *phydev)
{
    int c;

    c = ip1xx_reset(phydev);
    if (c < 0)
        return c;

    /* Enable Auto Power Saving mode */
    c = phy_read(phydev, IP1001_SPEC_CTRL_STATUS_2);
    if (c < 0)
        return c;
    c |= IP1001_APS_ON;
    c = phy_write(phydev, IP1001_SPEC_CTRL_STATUS_2, c);
    if (c < 0)
        return c;

    if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
            (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
            (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
            (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {

        c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
        if (c < 0)
            return c;

        c &= ~(IP1001_RXPHASE_SEL | IP1001_TXPHASE_SEL);

        if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
            c |= (IP1001_RXPHASE_SEL | IP1001_TXPHASE_SEL);
        else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
            c |= IP1001_RXPHASE_SEL;
        else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
            c |= IP1001_TXPHASE_SEL;

        c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
        if (c < 0)
            return c;
    }

    return 0;
}