/**
* amdgpu_irq_remove_domain - remove the irq domain
*
* @adev: amdgpu device pointer
*
* Remove the irq domain for GPU interrupt sources
* that may be driven by another driver (e.g., ACP).
*/
void amdgpu_irq_remove_domain(struct amdgpu_device *adev)
{
if (adev->irq.domain) {
irq_domain_remove(adev->irq.domain);
adev->irq.domain = NULL;
}
}
void mdp5_irq_domain_fini(struct mdp5_kms *mdp5_kms)
{
if (mdp5_kms->irqcontroller.domain) {
irq_domain_remove(mdp5_kms->irqcontroller.domain);
mdp5_kms->irqcontroller.domain = NULL;
}
}
static int pdc_intc_remove(struct platform_device *pdev)
{
struct pdc_intc_priv *priv = platform_get_drvdata(pdev);
irq_domain_remove(priv->domain);
return 0;
}
static int altera_gpio_remove(struct platform_device *pdev)
{
unsigned int irq, i;
int status;
struct altera_gpio_chip *altera_gc = platform_get_drvdata(pdev);
status = gpiochip_remove(&altera_gc->mmchip.gc);
if (status < 0)
return status;
if (altera_gc->irq) {
irq_dispose_mapping(altera_gc->hwirq);
for (i = 0; i < altera_gc->mmchip.gc.ngpio; i++) {
irq = irq_find_mapping(altera_gc->irq, i);
if (irq > 0)
irq_dispose_mapping(irq);
}
irq_domain_remove(altera_gc->irq);
}
irq_set_handler_data(altera_gc->hwirq, NULL);
irq_set_chained_handler(altera_gc->hwirq, NULL);
devm_kfree(&pdev->dev, altera_gc);
return -EIO;
}
static int __init nvic_of_init(struct device_node *node,
struct device_node *parent)
{
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
unsigned int irqs, i, ret, numbanks;
void __iomem *nvic_base;
numbanks = (readl_relaxed(V7M_SCS_ICTR) &
V7M_SCS_ICTR_INTLINESNUM_MASK) + 1;
nvic_base = of_iomap(node, 0);
if (!nvic_base) {
pr_warn("unable to map nvic registers\n");
return -ENOMEM;
}
irqs = numbanks * 32;
if (irqs > NVIC_MAX_IRQ)
irqs = NVIC_MAX_IRQ;
nvic_irq_domain =
irq_domain_add_linear(node, irqs, &irq_generic_chip_ops, NULL);
if (!nvic_irq_domain) {
pr_warn("Failed to allocate irq domain\n");
return -ENOMEM;
}
ret = irq_alloc_domain_generic_chips(nvic_irq_domain, 32, 1,
"nvic_irq", handle_fasteoi_irq,
clr, 0, IRQ_GC_INIT_MASK_CACHE);
if (ret) {
pr_warn("Failed to allocate irq chips\n");
irq_domain_remove(nvic_irq_domain);
return ret;
}
for (i = 0; i < numbanks; ++i) {
struct irq_chip_generic *gc;
gc = irq_get_domain_generic_chip(nvic_irq_domain, 32 * i);
gc->reg_base = nvic_base + 4 * i;
gc->chip_types[0].regs.enable = NVIC_ISER;
gc->chip_types[0].regs.disable = NVIC_ICER;
gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
gc->chip_types[0].chip.irq_eoi = nvic_eoi;
/* disable interrupts */
writel_relaxed(~0, gc->reg_base + NVIC_ICER);
}
/* Set priority on all interrupts */
for (i = 0; i < irqs; i += 4)
writel_relaxed(0, nvic_base + NVIC_IPR + i);
return 0;
}
static void intel_teardown_irq_remapping(struct intel_iommu *iommu)
{
if (iommu && iommu->ir_table) {
if (iommu->ir_msi_domain) {
irq_domain_remove(iommu->ir_msi_domain);
iommu->ir_msi_domain = NULL;
}
if (iommu->ir_domain) {
irq_domain_remove(iommu->ir_domain);
iommu->ir_domain = NULL;
}
free_pages((unsigned long)iommu->ir_table->base,
INTR_REMAP_PAGE_ORDER);
kfree(iommu->ir_table->bitmap);
kfree(iommu->ir_table);
iommu->ir_table = NULL;
}
}
static int em_gio_remove(struct platform_device *pdev)
{
struct em_gio_priv *p = platform_get_drvdata(pdev);
gpiochip_remove(&p->gpio_chip);
irq_domain_remove(p->irq_domain);
return 0;
}
static int intc_irqpin_remove(struct platform_device *pdev)
{
struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
irq_domain_remove(p->irq_domain);
pm_runtime_put(&pdev->dev);
pm_runtime_disable(&pdev->dev);
return 0;
}
static int __init moxart_of_intc_init(struct device_node *node,
struct device_node *parent)
{
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
int ret;
struct irq_chip_generic *gc;
intc.base = of_iomap(node, 0);
if (!intc.base) {
pr_err("%s: unable to map IC registers\n",
node->full_name);
return -EINVAL;
}
intc.domain = irq_domain_add_linear(node, 32, &irq_generic_chip_ops,
intc.base);
if (!intc.domain) {
pr_err("%s: unable to create IRQ domain\n", node->full_name);
return -EINVAL;
}
ret = irq_alloc_domain_generic_chips(intc.domain, 32, 1,
"MOXARTINTC", handle_edge_irq,
clr, 0, IRQ_GC_INIT_MASK_CACHE);
if (ret) {
pr_err("%s: could not allocate generic chip\n",
node->full_name);
irq_domain_remove(intc.domain);
return -EINVAL;
}
ret = of_property_read_u32(node, "interrupt-mask",
&intc.interrupt_mask);
if (ret)
pr_err("%s: could not read interrupt-mask DT property\n",
node->full_name);
gc = irq_get_domain_generic_chip(intc.domain, 0);
gc->reg_base = intc.base;
gc->chip_types[0].regs.mask = IRQ_MASK_REG;
gc->chip_types[0].regs.ack = IRQ_CLEAR_REG;
gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
writel(0, intc.base + IRQ_MASK_REG);
writel(0xffffffff, intc.base + IRQ_CLEAR_REG);
writel(intc.interrupt_mask, intc.base + IRQ_MODE_REG);
writel(intc.interrupt_mask, intc.base + IRQ_LEVEL_REG);
set_handle_irq(handle_irq);
return 0;
}
static int xgene_gpio_sb_remove(struct platform_device *pdev)
{
struct xgene_gpio_sb *priv = platform_get_drvdata(pdev);
if (priv->nirq > 0) {
acpi_gpiochip_free_interrupts(&priv->gc);
}
irq_domain_remove(priv->irq_domain);
return 0;
}
static int gpio_rcar_remove(struct platform_device *pdev)
{
struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
int ret;
ret = gpiochip_remove(&p->gpio_chip);
if (ret)
return ret;
irq_domain_remove(p->irq_domain);
return 0;
}
static int tb10x_gpio_remove(struct platform_device *pdev)
{
struct tb10x_gpio *tb10x_gpio = platform_get_drvdata(pdev);
if (tb10x_gpio->gc.to_irq) {
irq_remove_generic_chip(tb10x_gpio->domain->gc->gc[0],
BIT(tb10x_gpio->gc.ngpio) - 1, 0, 0);
kfree(tb10x_gpio->domain->gc);
irq_domain_remove(tb10x_gpio->domain);
}
return 0;
}
static int irqc_remove(struct platform_device *pdev)
{
struct irqc_priv *p = platform_get_drvdata(pdev);
int k;
for (k = 0; k < p->number_of_irqs; k++)
free_irq(p->irq[k].requested_irq, &p->irq[k]);
irq_domain_remove(p->irq_domain);
iounmap(p->iomem);
kfree(p);
return 0;
}
/**
* gb_gpio_irqchip_remove() - removes an irqchip added to a gb_gpio_controller
* @ggc: the gb_gpio_controller to remove the irqchip from
*
* This is called only from gb_gpio_remove()
*/
static void gb_gpio_irqchip_remove(struct gb_gpio_controller *ggc)
{
unsigned int offset;
/* Remove all IRQ mappings and delete the domain */
if (ggc->irqdomain) {
for (offset = 0; offset < (ggc->line_max + 1); offset++)
irq_dispose_mapping(irq_find_mapping(ggc->irqdomain, offset));
irq_domain_remove(ggc->irqdomain);
}
if (ggc->irqchip)
ggc->irqchip = NULL;
}
static int mpc8xxx_remove(struct platform_device *pdev)
{
struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
if (mpc8xxx_gc->irq) {
irq_set_handler_data(mpc8xxx_gc->irqn, NULL);
irq_set_chained_handler(mpc8xxx_gc->irqn, NULL);
irq_domain_remove(mpc8xxx_gc->irq);
}
of_mm_gpiochip_remove(&mpc8xxx_gc->mm_gc);
return 0;
}
/**
* regmap_del_irq_chip(): Stop interrupt handling for a regmap IRQ chip
*
* @irq: Primary IRQ for the device
* @d: regmap_irq_chip_data allocated by regmap_add_irq_chip()
*/
void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
{
if (!d)
return;
free_irq(irq, d);
irq_domain_remove(d->domain);
kfree(d->wake_buf);
kfree(d->mask_buf_def);
kfree(d->mask_buf);
kfree(d->status_reg_buf);
kfree(d->status_buf);
kfree(d);
}
static void ssb_gpio_irq_extif_domain_exit(struct ssb_bus *bus)
{
struct ssb_extif *extif = &bus->extif;
struct gpio_chip *chip = &bus->gpio;
int gpio;
if (bus->bustype != SSB_BUSTYPE_SSB)
return;
free_irq(ssb_mips_irq(bus->extif.dev) + 2, extif);
for (gpio = 0; gpio < chip->ngpio; gpio++) {
int irq = irq_find_mapping(bus->irq_domain, gpio);
irq_dispose_mapping(irq);
}
irq_domain_remove(bus->irq_domain);
}
static void bcma_gpio_irq_domain_exit(struct bcma_drv_cc *cc)
{
struct gpio_chip *chip = &cc->gpio;
int gpio;
if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
return;
bcma_cc_mask32(cc, BCMA_CC_IRQMASK, ~BCMA_CC_IRQ_GPIO);
free_irq(bcma_core_irq(cc->core, 0), cc);
for (gpio = 0; gpio < chip->ngpio; gpio++) {
int irq = irq_find_mapping(cc->irq_domain, gpio);
irq_dispose_mapping(irq);
}
irq_domain_remove(cc->irq_domain);
}
void msm_mdss_destroy(struct drm_device *dev)
{
struct msm_drm_private *priv = dev->dev_private;
struct msm_mdss *mdss = priv->mdss;
if (!mdss)
return;
irq_domain_remove(mdss->irqcontroller.domain);
mdss->irqcontroller.domain = NULL;
regulator_disable(mdss->vdd);
pm_runtime_put_sync(dev->dev);
pm_runtime_disable(dev->dev);
}
static int armada_370_xp_msi_init(struct device_node *node,
phys_addr_t main_int_phys_base)
{
struct msi_chip *msi_chip;
u32 reg;
int ret;
msi_doorbell_addr = main_int_phys_base +
ARMADA_370_XP_SW_TRIG_INT_OFFS;
msi_chip = kzalloc(sizeof(*msi_chip), GFP_KERNEL);
if (!msi_chip)
return -ENOMEM;
msi_chip->setup_irq = armada_370_xp_setup_msi_irq;
msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq;
msi_chip->of_node = node;
armada_370_xp_msi_domain =
irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
&armada_370_xp_msi_irq_ops,
NULL);
if (!armada_370_xp_msi_domain) {
kfree(msi_chip);
return -ENOMEM;
}
ret = of_pci_msi_chip_add(msi_chip);
if (ret < 0) {
irq_domain_remove(armada_370_xp_msi_domain);
kfree(msi_chip);
return ret;
}
reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
| PCI_MSI_DOORBELL_MASK;
writel(reg, per_cpu_int_base +
ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
/* Unmask IPI interrupt */
writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
return 0;
}
static int __exit dra7xx_pcie_remove(struct platform_device *pdev)
{
struct dra7xx_pcie *dra7xx = platform_get_drvdata(pdev);
struct pcie_port *pp = &dra7xx->pp;
struct device *dev = &pdev->dev;
int count = dra7xx->phy_count;
if (pp->irq_domain)
irq_domain_remove(pp->irq_domain);
pm_runtime_put(dev);
pm_runtime_disable(dev);
while (count--) {
phy_power_off(dra7xx->phy[count]);
phy_exit(dra7xx->phy[count]);
}
return 0;
}
static void ssb_gpio_irq_chipco_domain_exit(struct ssb_bus *bus)
{
struct ssb_chipcommon *chipco = &bus->chipco;
struct gpio_chip *chip = &bus->gpio;
int gpio;
if (bus->bustype != SSB_BUSTYPE_SSB)
return;
chipco_mask32(chipco, SSB_CHIPCO_IRQMASK, ~SSB_CHIPCO_IRQ_GPIO);
free_irq(ssb_mips_irq(bus->chipco.dev) + 2, chipco);
for (gpio = 0; gpio < chip->ngpio; gpio++) {
int irq = irq_find_mapping(bus->irq_domain, gpio);
irq_dispose_mapping(irq);
}
irq_domain_remove(bus->irq_domain);
}
void its_fsl_mc_msi_cleanup(void)
{
struct device_node *np;
for (np = of_find_matching_node(NULL, its_device_id); np;
np = of_find_matching_node(np, its_device_id)) {
struct irq_domain *mc_msi_domain = irq_find_matching_host(
np,
DOMAIN_BUS_FSL_MC_MSI);
if (!of_property_read_bool(np, "msi-controller"))
continue;
if (mc_msi_domain &&
mc_msi_domain->host_data == &its_fsl_mc_msi_domain_info)
irq_domain_remove(mc_msi_domain);
}
}
static int __exit tb10x_gpio_remove(struct platform_device *pdev)
{
struct tb10x_gpio *tb10x_gpio = platform_get_drvdata(pdev);
int ret;
if (tb10x_gpio->gc.to_irq) {
irq_remove_generic_chip(tb10x_gpio->domain->gc->gc[0],
BIT(tb10x_gpio->gc.ngpio) - 1, 0, 0);
kfree(tb10x_gpio->domain->gc);
irq_domain_remove(tb10x_gpio->domain);
free_irq(tb10x_gpio->irq, tb10x_gpio);
}
ret = gpiochip_remove(&tb10x_gpio->gc);
if (ret)
return ret;
return 0;
}
static int ssb_gpio_irq_chipco_domain_init(struct ssb_bus *bus)
{
struct ssb_chipcommon *chipco = &bus->chipco;
struct gpio_chip *chip = &bus->gpio;
int gpio, hwirq, err;
if (bus->bustype != SSB_BUSTYPE_SSB)
return 0;
bus->irq_domain = irq_domain_add_linear(NULL, chip->ngpio,
&irq_domain_simple_ops, chipco);
if (!bus->irq_domain) {
err = -ENODEV;
goto err_irq_domain;
}
for (gpio = 0; gpio < chip->ngpio; gpio++) {
int irq = irq_create_mapping(bus->irq_domain, gpio);
irq_set_chip_data(irq, bus);
irq_set_chip_and_handler(irq, &ssb_gpio_irq_chipco_chip,
handle_simple_irq);
}
hwirq = ssb_mips_irq(bus->chipco.dev) + 2;
err = request_irq(hwirq, ssb_gpio_irq_chipco_handler, IRQF_SHARED,
"gpio", bus);
if (err)
goto err_req_irq;
ssb_chipco_gpio_intmask(&bus->chipco, ~0, 0);
chipco_set32(chipco, SSB_CHIPCO_IRQMASK, SSB_CHIPCO_IRQ_GPIO);
return 0;
err_req_irq:
for (gpio = 0; gpio < chip->ngpio; gpio++) {
int irq = irq_find_mapping(bus->irq_domain, gpio);
irq_dispose_mapping(irq);
}
irq_domain_remove(bus->irq_domain);
err_irq_domain:
return err;
}
static int bcma_gpio_irq_domain_init(struct bcma_drv_cc *cc)
{
struct gpio_chip *chip = &cc->gpio;
int gpio, hwirq, err;
if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
return 0;
cc->irq_domain = irq_domain_add_linear(NULL, chip->ngpio,
&irq_domain_simple_ops, cc);
if (!cc->irq_domain) {
err = -ENODEV;
goto err_irq_domain;
}
for (gpio = 0; gpio < chip->ngpio; gpio++) {
int irq = irq_create_mapping(cc->irq_domain, gpio);
irq_set_chip_data(irq, cc);
irq_set_chip_and_handler(irq, &bcma_gpio_irq_chip,
handle_simple_irq);
}
hwirq = bcma_core_irq(cc->core, 0);
err = request_irq(hwirq, bcma_gpio_irq_handler, IRQF_SHARED, "gpio",
cc);
if (err)
goto err_req_irq;
bcma_chipco_gpio_intmask(cc, ~0, 0);
bcma_cc_set32(cc, BCMA_CC_IRQMASK, BCMA_CC_IRQ_GPIO);
return 0;
err_req_irq:
for (gpio = 0; gpio < chip->ngpio; gpio++) {
int irq = irq_find_mapping(cc->irq_domain, gpio);
irq_dispose_mapping(irq);
}
irq_domain_remove(cc->irq_domain);
err_irq_domain:
return err;
}
static int __init omap_init_irq_of(struct device_node *node)
{
int ret;
omap_irq_base = of_iomap(node, 0);
if (WARN_ON(!omap_irq_base))
return -ENOMEM;
domain = irq_domain_add_linear(node, omap_nr_irqs,
&irq_generic_chip_ops, NULL);
omap_irq_soft_reset();
ret = omap_alloc_gc_of(domain, omap_irq_base);
if (ret < 0)
irq_domain_remove(domain);
return ret;
}
static int em_gio_remove(struct platform_device *pdev)
{
struct em_gio_priv *p = platform_get_drvdata(pdev);
struct resource *irq[2];
int ret;
ret = gpiochip_remove(&p->gpio_chip);
if (ret)
return ret;
irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
free_irq(irq[1]->start, pdev);
free_irq(irq[0]->start, pdev);
irq_domain_remove(p->irq_domain);
iounmap(p->base1);
iounmap(p->base0);
kfree(p);
return 0;
}
int its_alloc_vcpu_irqs(struct its_vm *vm)
{
int vpe_base_irq, i;
vm->fwnode = irq_domain_alloc_named_id_fwnode("GICv4-vpe",
task_pid_nr(current));
if (!vm->fwnode)
goto err;
vm->domain = irq_domain_create_hierarchy(gic_domain, 0, vm->nr_vpes,
vm->fwnode, vpe_domain_ops,
vm);
if (!vm->domain)
goto err;
for (i = 0; i < vm->nr_vpes; i++) {
vm->vpes[i]->its_vm = vm;
vm->vpes[i]->idai = true;
}
vpe_base_irq = __irq_domain_alloc_irqs(vm->domain, -1, vm->nr_vpes,
NUMA_NO_NODE, vm,
false, NULL);
if (vpe_base_irq <= 0)
goto err;
for (i = 0; i < vm->nr_vpes; i++)
vm->vpes[i]->irq = vpe_base_irq + i;
return 0;
err:
if (vm->domain)
irq_domain_remove(vm->domain);
if (vm->fwnode)
irq_domain_free_fwnode(vm->fwnode);
return -ENOMEM;
}
static struct at91_pmc *__init at91_pmc_init(struct device_node *np,
void __iomem *regbase, int virq,
const struct at91_pmc_caps *caps)
{
struct at91_pmc *pmc;
if (!regbase || !virq || !caps)
return NULL;
at91_pmc_base = regbase;
pmc = kzalloc(sizeof(*pmc), GFP_KERNEL);
if (!pmc)
return NULL;
spin_lock_init(&pmc->lock);
pmc->regbase = regbase;
pmc->virq = virq;
pmc->caps = caps;
pmc->irqdomain = irq_domain_add_linear(np, 32, &pmc_irq_ops, pmc);
if (!pmc->irqdomain)
goto out_free_pmc;
pmc_write(pmc, AT91_PMC_IDR, 0xffffffff);
if (request_irq(pmc->virq, pmc_irq_handler,
IRQF_SHARED | IRQF_COND_SUSPEND, "pmc", pmc))
goto out_remove_irqdomain;
return pmc;
out_remove_irqdomain:
irq_domain_remove(pmc->irqdomain);
out_free_pmc:
kfree(pmc);
return NULL;
}
