static void uart_nrf5_irq_config(struct device *port)
{
IRQ_CONNECT(NRF52_IRQ_UARTE0_UART0_IRQn,
CONFIG_UART_NRF5_IRQ_PRI,
uart_nrf5_isr, DEVICE_GET(uart_nrf5_0),
0);
irq_enable(NRF52_IRQ_UARTE0_UART0_IRQn);
}
__attribute__((noreturn)) void reboot()
{
uart_force_sync(1); /* flush UART buffers */
irq_setmask(0);
irq_enable(0);
CSR_SYSTEM_ID = 1; /* Writing to CSR_SYSTEM_ID causes a system reset */
while(1);
}
int qrk_cxxxx_rtc_init(struct device *rtc_dev)
{
IRQ_CONNECT(SOC_RTC_INTERRUPT, ISR_DEFAULT_PRIO, rtc_isr,
DEVICE_GET(rtc), 0);
irq_enable(SOC_RTC_INTERRUPT);
rtc_dev->driver_api = &qrk_cxxxx_rtc_funcs;
return 0;
}
/*
* Decrease the level,
* and if it's null then
* enable interruption
*/
void enable_it()
{
if (--it <= 0)
{
it = 0;
irq_enable();
}
}
static void mcux_lpsci_config_func_0(struct device *dev)
{
IRQ_CONNECT(NXP_KINETIS_LPSCI_4006A000_IRQ_0,
NXP_KINETIS_LPSCI_4006A000_IRQ_0_PRIORITY,
mcux_lpsci_isr, DEVICE_GET(uart_0), 0);
irq_enable(NXP_KINETIS_LPSCI_4006A000_IRQ_0);
}
static void usart1_sam_irq_config_func(struct device *port)
{
IRQ_CONNECT(DT_USART_SAM_PORT_1_IRQ,
DT_USART_SAM_PORT_1_IRQ_PRIO,
usart_sam_isr,
DEVICE_GET(usart1_sam), 0);
irq_enable(DT_USART_SAM_PORT_1_IRQ);
}
static void mcux_elcdif_config_func_1(struct device *dev)
{
IRQ_CONNECT(DT_FSL_IMX6SX_LCDIF_0_IRQ_0,
DT_FSL_IMX6SX_LCDIF_0_IRQ_0_PRIORITY,
mcux_elcdif_isr, DEVICE_GET(mcux_elcdif_1), 0);
irq_enable(DT_FSL_IMX6SX_LCDIF_0_IRQ_0);
}
void nrm_loop(void)
{
int i = 0;
uart_init();
uart_print(GUEST_LABEL); uart_print("=== Starting...\n\r");
gic_init();
/* We are ready to accept irqs with GIC. Enable it now */
irq_enable();
/* Test the sample virtual device
* - Uncomment the following line of code only if 'vdev_sample' is registered at the monitor
* - Otherwise, the monitor will hang with data abort
*/
#ifdef TESTS_ENABLE_VDEV_SAMPLE
test_vdev_sample();
#endif
#ifdef TESTS_ENABLE_PWM_TIMER
hvmm_tests_pwm_timer();
#endif
#ifdef TESTS_ENABLE_SP804_TIMER
/* Test the SP804 timer */
hvmm_tests_sp804_timer();
#endif
for( i = 0; i < NUM_ITERATIONS; i++ ) {
uart_print(GUEST_LABEL); uart_print("iteration "); uart_print_hex32( i ); uart_print( "\n\r" );
nrm_delay();
#ifdef __MONITOR_CALL_HVC__
/* Hyp monitor guest run in Non-secure supervisor mode.
Request test hvc ping and yield one after another
*/
if (i & 0x1) {
uart_print(GUEST_LABEL); uart_print( "hsvc_ping()\n\r" );
hsvc_ping();
uart_print(GUEST_LABEL); uart_print( "returned from hsvc_ping() \n\r" );
} else {
uart_print(GUEST_LABEL); uart_print( "hsvc_yield()\n\r" );
hsvc_yield();
uart_print(GUEST_LABEL); uart_print( "returned from hsvc_yield() \n\r" );
}
#else
/* Secure monitor guest run in Non-secure supervisor mode
Request for switch to Secure mode (sec_loop() in the monitor)
*/
SWITCH_MANUAL();
#endif
nrm_delay();
}
uart_print(GUEST_LABEL); uart_print("done\n\r");
while(1);
}
// Set the direction of the next queued step
void
command_set_next_step_dir(uint32_t *args)
{
struct stepper *s = stepper_oid_lookup(args[0]);
uint8_t nextdir = args[1] ? SF_NEXT_DIR : 0;
irq_disable();
s->flags = (s->flags & ~SF_NEXT_DIR) | nextdir;
irq_enable();
}
static void
arckbd_pollc(void *cookie, int poll)
{
struct arckbd_softc *sc = cookie;
int s;
s = spltty();
if (poll) {
sc->sc_flags |= AKF_POLLING;
irq_disable(sc->sc_rirq);
irq_disable(sc->sc_xirq);
} else {
sc->sc_flags &= ~AKF_POLLING;
irq_enable(sc->sc_rirq);
irq_enable(sc->sc_xirq);
}
splx(s);
}
static void uart_cmsdk_apb_irq_config_func_4(struct device *dev)
{
IRQ_CONNECT(CMSDK_APB_UART_4_IRQ,
CONFIG_UART_CMSDK_APB_PORT4_IRQ_PRI,
uart_cmsdk_apb_isr,
DEVICE_GET(uart_cmsdk_apb_4),
0);
irq_enable(CMSDK_APB_UART_4_IRQ);
}
static void uart_cmsdk_apb_irq_config_func_1(struct device *dev)
{
IRQ_CONNECT(DT_ARM_CMSDK_UART_1_IRQ_0,
DT_ARM_CMSDK_UART_1_IRQ_0_PRIORITY,
uart_cmsdk_apb_isr,
DEVICE_GET(uart_cmsdk_apb_1),
0);
irq_enable(DT_ARM_CMSDK_UART_1_IRQ_0);
}
static void adc_config_irq(void)
{
IRQ_CONNECT(CONFIG_ADC_IRQ, CONFIG_ADC_PRI, qm_adc_0_isr,
NULL, (IOAPIC_LEVEL | IOAPIC_HIGH));
irq_enable(CONFIG_ADC_IRQ);
QM_SCSS_INT->int_adc_calib_mask &= ~BIT(0);
}
static void i2c_mcux_config_func_0(struct device *dev)
{
ARG_UNUSED(dev);
IRQ_CONNECT(CONFIG_I2C_MCUX_0_IRQ, CONFIG_I2C_MCUX_0_IRQ_PRI,
i2c_mcux_isr, DEVICE_GET(i2c_mcux_0), 0);
irq_enable(CONFIG_I2C_MCUX_0_IRQ);
}
void thread_exit(void)
{
irq_disable();
current_thread->state = TASK_FINISHED;
irq_enable();
/* this call also enables IRQs */
switch_next();
}
static void __attribute__((noreturn)) boot(unsigned int r1, unsigned int r2, unsigned int r3, unsigned int r4, unsigned int addr)
{
vga_blank();
uart_force_sync(1);
irq_setmask(0);
irq_enable(0);
boot_helper(r1, r2, r3, r4, addr);
while(1);
}
static void i2c_imx_config_func_3(struct device *dev)
{
ARG_UNUSED(dev);
IRQ_CONNECT(DT_FSL_IMX7D_I2C_I2C_3_IRQ, DT_FSL_IMX7D_I2C_I2C_3_IRQ_PRIORITY,
i2c_imx_isr, DEVICE_GET(i2c_imx_3), 0);
irq_enable(DT_FSL_IMX7D_I2C_I2C_3_IRQ);
}
void sem_up(struct sem_s * sem){
irq_disable();
sem->cpt++;
if(sem->cpt<=0){
sem->first_ctx_bloque->ctx_state =CTX_EXEQ;
sem->first_ctx_bloque=sem->first_ctx_bloque->next_ctx_bloque;
}
irq_enable();
}
static void uart_cmsdk_apb_irq_config_func_3(struct device *dev)
{
IRQ_CONNECT(CMSDK_APB_UART_3_IRQ,
DT_ARM_CMSDK_UART_3_IRQ_PRIORITY,
uart_cmsdk_apb_isr,
DEVICE_GET(uart_cmsdk_apb_3),
0);
irq_enable(CMSDK_APB_UART_3_IRQ);
}
static void ipm_mhu_irq_config_func_1(struct device *d)
{
ARG_UNUSED(d);
IRQ_CONNECT(DT_ARM_MHU_1_IRQ_0,
DT_ARM_MHU_1_IRQ_0_PRIORITY,
ipm_mhu_isr,
DEVICE_GET(mhu_1),
0);
irq_enable(DT_ARM_MHU_1_IRQ_0);
}
// Report the current position of the stepper
void
command_stepper_get_position(uint32_t *args)
{
uint8_t oid = args[0];
struct stepper *s = stepper_oid_lookup(oid);
irq_disable();
uint32_t position = stepper_get_position(s);
irq_enable();
sendf("stepper_position oid=%c pos=%i", oid, position - POSITION_BIAS);
}
PUBLIC void irq_add_flih(u8_t irq, struct irq_node* node)
{
if (irq < IRQ_VECTORS)
{
LLIST_ADD(irq_flih[irq],node);
irq_enable(irq);
}
return;
}
void i2c_config_1(struct device *port)
{
struct i2c_dw_rom_config * const config = port->config->config_info;
struct device *shared_irq_dev;
ARG_UNUSED(shared_irq_dev);
IRQ_CONNECT(I2C_DW_1_IRQ, CONFIG_I2C_DW_1_IRQ_PRI,
i2c_dw_isr, DEVICE_GET(i2c_1), I2C_DW_IRQ_FLAGS);
irq_enable(config->irq_num);
}
/* Initialize simcard interface */
void calypso_sim_init(void)
{
/* Register IRQ handler and turn interrupts on */
#if (SIM_DEBUG == 1)
puts("SIM: Registering interrupt handler for simcard-interface\n");
#endif
irq_register_handler(IRQ_SIMCARD, &sim_irq_handler);
irq_config(IRQ_SIMCARD, 0, 0, 0xff);
irq_enable(IRQ_SIMCARD);
}
int
spl0()
{
irq_disable();
int opl = CIPL;
CIPL = IPL_NONE;
i8259a_reset_mask();
irq_enable();
return opl;
}
int usb_dc_ep_write(const u8_t ep, const u8_t *const data,
const u32_t data_len, u32_t * const ret_bytes)
{
struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
HAL_StatusTypeDef status;
u32_t len = data_len;
int ret = 0;
LOG_DBG("ep 0x%02x, len %u", ep, data_len);
if (!ep_state || !EP_IS_IN(ep)) {
LOG_ERR("invalid ep 0x%02x", ep);
return -EINVAL;
}
ret = k_sem_take(&ep_state->write_sem, K_NO_WAIT);
if (ret) {
LOG_ERR("Unable to get write lock (%d)", ret);
return -EAGAIN;
}
if (!k_is_in_isr()) {
irq_disable(DT_USB_IRQ);
}
if (ep == EP0_IN && len > USB_MAX_CTRL_MPS) {
len = USB_MAX_CTRL_MPS;
}
status = HAL_PCD_EP_Transmit(&usb_dc_stm32_state.pcd, ep,
(void *)data, len);
if (status != HAL_OK) {
LOG_ERR("HAL_PCD_EP_Transmit failed(0x%02x), %d", ep,
(int)status);
k_sem_give(&ep_state->write_sem);
ret = -EIO;
}
if (!ret && ep == EP0_IN && len > 0) {
/* Wait for an empty package as from the host.
* This also flushes the TX FIFO to the host.
*/
usb_dc_ep_start_read(ep, NULL, 0);
}
if (!k_is_in_isr()) {
irq_enable(DT_USB_IRQ);
}
if (ret_bytes) {
*ret_bytes = len;
}
return ret;
}
static int spi_qmsi_init(struct device *dev)
{
const struct spi_qmsi_config *spi_config = dev->config->config_info;
struct spi_qmsi_runtime *context = dev->driver_data;
switch (spi_config->spi) {
case QM_SPI_MST_0:
IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_SPI_MASTER_0_INT),
CONFIG_SPI_0_IRQ_PRI, qm_spi_master_0_isr,
0, IOAPIC_LEVEL | IOAPIC_HIGH);
irq_enable(IRQ_GET_NUMBER(QM_IRQ_SPI_MASTER_0_INT));
clk_periph_enable(CLK_PERIPH_CLK | CLK_PERIPH_SPI_M0_REGISTER);
QM_IR_UNMASK_INTERRUPTS(
QM_INTERRUPT_ROUTER->spi_master_0_int_mask);
break;
#ifdef CONFIG_SPI_1
case QM_SPI_MST_1:
IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_SPI_MASTER_1_INT),
CONFIG_SPI_1_IRQ_PRI, qm_spi_master_1_isr,
0, IOAPIC_LEVEL | IOAPIC_HIGH);
irq_enable(IRQ_GET_NUMBER(QM_IRQ_SPI_MASTER_1_INT));
clk_periph_enable(CLK_PERIPH_CLK | CLK_PERIPH_SPI_M1_REGISTER);
QM_IR_UNMASK_INTERRUPTS(
QM_INTERRUPT_ROUTER->spi_master_1_int_mask);
break;
#endif /* CONFIG_SPI_1 */
default:
return -EIO;
}
context->gpio_cs = gpio_cs_init(spi_config);
k_sem_init(&context->device_sync_sem, 0, UINT_MAX);
k_sem_init(&context->sem, 1, UINT_MAX);
spi_master_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
dev->driver_api = &spi_qmsi_api;
return 0;
}
void yield()
{
ctx_t *current;
if (ctx == NULL)
return;
irq_disable();
//CORE LOCK
current = find_next_iddle();
if (current == NULL)
{
//CORE UNLOCK
irq_enable();
return;
}
switch_to_ctx(current, _in(CORE_ID));
clean_ctx(current);
//CORE UNLOCK
irq_enable();
}
void sys_init(void)
{
pll_init();
power_init();
vic_init();
SYS_SetFastGPIO();
gpio_init(test_handler);
i2c_init();
irq_enable();
}
void dm9000_send(unsigned long addr,int size)
{
int i;
irq_disable(1);
DM9000_INDEX = 0xf8;
for(i = 0;i < (size + 1)/2; i++)
DM9000_DATA16 = ((short *)addr)[i];
iow(0xfd,(size >> 8) & 0xff);
iow(0xfc,size & 0xff);
iow(0x02,1);
irq_enable(1);
}
