int snd_record_refill(short *buffer) { unsigned int oldmask; oldmask = irq_getmask(); irq_setmask(0); if(record_level >= RECORD_BUFQ_SIZE) { irq_setmask(oldmask); printf("SND: record bufq overflow\n"); return 0; } record_queue[record_produce] = buffer; record_produce = (record_produce + 1) & RECORD_BUFQ_MASK; record_level++; if(record_overrun) { record_overrun = 0; record_start(buffer); } irq_setmask(oldmask); return 1; }
int snd_play_refill(short *buffer) { unsigned int oldmask; oldmask = irq_getmask(); irq_setmask(0); if(play_level >= PLAY_BUFQ_SIZE) { irq_setmask(oldmask); printf("SND: play bufq overflow\n"); return 0; } play_queue[play_produce] = buffer; play_produce = (play_produce + 1) & PLAY_BUFQ_MASK; play_level++; if(play_underrun) { play_underrun = 0; play_start(buffer); } irq_setmask(oldmask); return 1; }
void isr(void) { unsigned int irqs; irqs = irq_pending() & irq_getmask(); if(irqs & IRQ_UART) uart_isr(); if(irqs & IRQ_TIMER0) time_isr(); if(irqs & IRQ_AC97CRREQUEST) snd_isr_crrequest(); if(irqs & IRQ_AC97CRREPLY) snd_isr_crreply(); if(irqs & IRQ_AC97DMAR) snd_isr_dmar(); if(irqs & IRQ_AC97DMAW) snd_isr_dmaw(); if(irqs & IRQ_TMU) tmu_isr(); if(irqs & IRQ_PFPU) pfpu_isr(); irq_ack(irqs); }
void hdmi_in1_init_video(int hres, int vres) { unsigned int mask; hdmi_in1_clocking_pll_reset_write(1); hdmi_in1_connected = hdmi_in1_locked = 0; hdmi_in1_hres = hres; hdmi_in1_vres = vres; hdmi_in1_dma_frame_size_write(hres*vres*2); hdmi_in1_fb_slot_indexes[0] = 0; hdmi_in1_dma_slot0_address_write(hdmi_in1_framebuffer_base(0)); hdmi_in1_dma_slot0_status_write(DVISAMPLER_SLOT_LOADED); hdmi_in1_fb_slot_indexes[1] = 1; hdmi_in1_dma_slot1_address_write(hdmi_in1_framebuffer_base(1)); hdmi_in1_dma_slot1_status_write(DVISAMPLER_SLOT_LOADED); hdmi_in1_next_fb_index = 2; hdmi_in1_dma_ev_pending_write(hdmi_in1_dma_ev_pending_read()); hdmi_in1_dma_ev_enable_write(0x3); mask = irq_getmask(); mask |= 1 << HDMI_IN1_INTERRUPT; irq_setmask(mask); hdmi_in1_fb_index = 3; }
int pfpu_submit_task(struct pfpu_td *td) { unsigned int oldmask; oldmask = irq_getmask(); irq_setmask(oldmask & (~IRQ_PFPU)); if(level >= PFPU_TASKQ_SIZE) { irq_setmask(oldmask); printf("FPU: taskq overflow\n"); return 0; } queue[produce] = td; produce = (produce + 1) & PFPU_TASKQ_MASK; level++; if(cts) { cts = 0; pfpu_start(td); } irq_setmask(oldmask); return 1; }
void uart_init(void) { uint32_t mask; uint8_t value; rx_produce = 0; rx_consume = 0; irq_ack(IRQ_UART); /* enable UART interrupts */ writeb(LM32_UART_IER_RBRI, &uart->ier); mask = irq_getmask(); mask |= IRQ_UART; irq_setmask(mask); /* Line control 8 bit, 1 stop, no parity */ writeb(LM32_UART_LCR_8BIT, &uart->lcr); /* Modem control, DTR = 1, RTS = 1 */ writeb(LM32_UART_MCR_DTR | LM32_UART_MCR_RTS, &uart->mcr); /* Set baud rate */ value = (CPU_FREQUENCY / UART_BAUD_RATE) & 0xff; writeb(value, &uart->divl); value = (CPU_FREQUENCY / UART_BAUD_RATE) >> 8; writeb(value, &uart->divh); }
void snd_init() { unsigned int codec_id; unsigned int mask; snd_cr_request = 0; snd_cr_reply = 0; CSR_AC97_DCTL = 0; CSR_AC97_UCTL = 0; mask = irq_getmask(); mask |= IRQ_AC97CRREQUEST|IRQ_AC97CRREPLY|IRQ_AC97DMAR|IRQ_AC97DMAW; irq_setmask(mask); codec_id = snd_ac97_read(0x00); if(codec_id == 0x0d50) printf("SND: found LM4550 AC'97 codec\n"); else printf("SND: warning, unknown codec found (ID:%04x)\n", codec_id); /* Unmute and set volumes */ /* TODO: API for this */ snd_ac97_write(0x02, 0x0000); snd_ac97_write(0x04, 0x0f0f); snd_ac97_write(0x18, 0x0000); snd_ac97_write(0x0e, 0x0000); snd_ac97_write(0x1c, 0x0f0f); snd_play_empty(); snd_record_empty(); printf("SND: initialization complete\n"); }
int slowout_queue(unsigned int duration, unsigned int mask) { unsigned int oldmask; oldmask = irq_getmask(); irq_setmask(oldmask & (~IRQ_TIMER1)); if(level >= OPQ_SIZE) { irq_setmask(oldmask); printf("SLO: opq overflow\n"); return 0; } queue[produce].duration = duration; queue[produce].mask = mask; if(cts) { cts = 0; slowout_start(&queue[produce]); } produce = (produce + 1) & OPQ_MASK; level++; irq_setmask(oldmask); return 1; }
void rpipe_swap_bottom_half() { unsigned short *b; unsigned int oldmask; /* Swap texture buffers */ b = tex_backbuffer; tex_backbuffer = tex_frontbuffer; tex_frontbuffer = b; /* Update display */ vga_swap_buffers(); /* Update statistics */ oldmask = irq_getmask(); irq_setmask(oldmask & ~(IRQ_TIMER0)); frames++; irq_setmask(oldmask); /* Ready to process the next frame ! */ queue[consume]->callback(queue[consume]); consume = (consume + 1) & RPIPE_FRAMEQ_MASK; level--; if(level > 0) rpipe_start(queue[consume]); else cts = 1; }
void dvisampler_init_video(int hres, int vres) { unsigned int mask; dvisampler_clocking_pll_reset_write(1); dvisampler_connected = dvisampler_locked = 0; dvisampler_hres = hres; dvisampler_vres = vres; dvisampler_dma_frame_size_write(hres*vres*2); dvisampler_fb_slot_indexes[0] = 0; dvisampler_dma_slot0_address_write(dvisampler_framebuffer_base(0)); dvisampler_dma_slot0_status_write(DVISAMPLER_SLOT_LOADED); dvisampler_fb_slot_indexes[1] = 1; dvisampler_dma_slot1_address_write(dvisampler_framebuffer_base(1)); dvisampler_dma_slot1_status_write(DVISAMPLER_SLOT_LOADED); dvisampler_next_fb_index = 2; dvisampler_dma_ev_pending_write(dvisampler_dma_ev_pending_read()); dvisampler_dma_ev_enable_write(0x3); mask = irq_getmask(); mask |= 1 << DVISAMPLER_INTERRUPT; irq_setmask(mask); fb_fi_base0_write(dvisampler_framebuffer_base(3)); }
void isr(void) { unsigned int irqs; irqs = irq_pending() & irq_getmask(); if(irqs & (1 << UART_INTERRUPT)) uart_isr(); }
void snd_record_stop() { unsigned int oldmask; oldmask = irq_getmask(); irq_setmask(oldmask & (~IRQ_AC97DMAW)); CSR_AC97_UCTL = 0; /* this also acks any pending IRQ in the AC97 core */ irq_ack(IRQ_AC97DMAW); irq_setmask(oldmask); }
void snd_record_stop() { unsigned int oldmask; oldmask = irq_getmask(); irq_setmask(0); CSR_AC97_UCTL = 0; record_overrun = 0; irq_ack(IRQ_AC97DMAW); irq_setmask(oldmask); }
void snd_play_stop() { unsigned int oldmask; oldmask = irq_getmask(); irq_setmask(0); CSR_AC97_DCTL = 0; play_underrun = 0; irq_ack(IRQ_AC97DMAR); irq_setmask(oldmask); }
void hdmi_in1_disable(void) { unsigned int mask; mask = irq_getmask(); mask &= ~(1 << HDMI_IN1_INTERRUPT); irq_setmask(mask); hdmi_in1_dma_slot0_status_write(DVISAMPLER_SLOT_EMPTY); hdmi_in1_dma_slot1_status_write(DVISAMPLER_SLOT_EMPTY); hdmi_in1_clocking_pll_reset_write(1); }
void dvisampler_disable(void) { unsigned int mask; mask = irq_getmask(); mask &= ~(1 << DVISAMPLER_INTERRUPT); irq_setmask(mask); dvisampler_dma_slot0_status_write(DVISAMPLER_SLOT_EMPTY); dvisampler_dma_slot1_status_write(DVISAMPLER_SLOT_EMPTY); dvisampler_clocking_pll_reset_write(1); }
void cpustats_enter() { unsigned int oldmask = 0; oldmask = irq_getmask(); irq_setmask(0); enter_count++; if(enter_count == 1) time_get(&first_enter); irq_setmask(oldmask); }
void uart_write(char c) { unsigned int oldmask; oldmask = irq_getmask(); irq_setmask(0); while (!(readb(&uart->lsr) & (LM32_UART_LSR_THRR | LM32_UART_LSR_TEMT))) ; writeb(c, &uart->rxtx); irq_setmask(oldmask); }
void putsnonl(const char *s) { unsigned int oldmask; oldmask = irq_getmask(); irq_setmask(IRQ_UART); // HACK: prevent UART data loss while(*s) { writechar(*s); s++; } irq_setmask(oldmask); }
void up_enable_irq(int irq) { irqstate_t flags; DEBUGASSERT(irq >= 0 && irq < NR_IRQS); /* Ignore any attempt to enable software interrupts */ if (irq < LM32_NINTERRUPTS) { /* Enable interrupts by setting the bit that corresponds to the irq */ flags = irq_getmask(); flags |= (1 << irq); irq_setmask(flags); } }
int puts(const char *s) { unsigned int oldmask; oldmask = irq_getmask(); irq_setmask(IRQ_UART); // HACK: prevent UART data loss while(*s) { writechar(*s); s++; } writechar('\n'); irq_setmask(oldmask); return 1; }
void uart_write(char c) { unsigned int oldmask; oldmask = irq_getmask(); irq_setmask(0); if(tx_cts) { tx_cts = 0; CSR_UART_RXTX = c; } else { tx_buf[tx_produce] = c; tx_produce = (tx_produce + 1) & UART_RINGBUFFER_MASK_TX; } irq_setmask(oldmask); }
void isr(void) { unsigned int irqs; irqs = irq_pending() & irq_getmask(); if(irqs & IRQ_UART) uart_isr(); #ifdef FIXME if(irqs & IRQ_TMU) tmu_isr(); if(irqs & IRQ_USB) usb_isr(); #endif }
void snd_init() { unsigned int codec_id; unsigned int mask; if(!(CSR_CAPABILITIES & CAP_AC97)) { printf("SND: not supported by SoC, giving up.\n"); return; } snd_cr_request = 0; snd_cr_reply = 0; /* Reset AC'97 controller */ CSR_AC97_CRCTL = 0; CSR_AC97_DCTL = 0; CSR_AC97_UCTL = 0; irq_ack(IRQ_AC97CRREQUEST|IRQ_AC97CRREPLY|IRQ_AC97DMAR|IRQ_AC97DMAW); mask = irq_getmask(); mask |= IRQ_AC97CRREQUEST|IRQ_AC97CRREPLY|IRQ_AC97DMAR|IRQ_AC97DMAW; irq_setmask(mask); codec_id = snd_ac97_read(0x00); if(codec_id == 0x0d50) printf("SND: found LM4550 AC'97 codec\n"); else if(codec_id == 0x6150) printf("SND: found WM9707 AC'97 codec\n"); else printf("SND: warning, unknown codec found (ID:%04x)\n", codec_id); /* Unmute and set volumes */ /* TODO: API for this */ snd_ac97_write(0x02, 0x0000); /* master volume */ snd_ac97_write(0x04, 0x0f0f); /* headphones volume */ snd_ac97_write(0x18, 0x0000); /* PCM out volume */ snd_ac97_write(0x1c, 0x0f0f); /* record gain */ snd_ac97_write(0x0e, 0x0000); /* mic volume: max */ snd_ac97_write(0x10, 0x0000); /* line in volume: max */ snd_ac97_write(0x1a, 0x0505); /* record select: stero mix */ snd_play_empty(); snd_record_empty(); printf("SND: initialization complete\n"); }
void tmu_init() { unsigned int mask; produce = 0; consume = 0; level = 0; cts = 1; CSR_TMU_CTL = 0; /* Ack any pending IRQ */ mask = irq_getmask(); mask |= IRQ_TMU; irq_setmask(mask); printf("TMU: texture mapping unit initialized\n"); }
void cpustats_leave() { unsigned int oldmask = 0; oldmask = irq_getmask(); irq_setmask(0); enter_count--; if(enter_count == 0) { struct timestamp ts; struct timestamp diff; time_get(&ts); time_diff(&diff, &ts, &first_enter); time_add(&acc, &diff); } irq_setmask(oldmask); }
void uart_init(void) { unsigned int mask; rx_produce = 0; rx_consume = 0; tx_produce = 0; tx_consume = 0; tx_cts = 1; tx_level = 0; uart_ev_pending_write(uart_ev_pending_read()); uart_ev_enable_write(UART_EV_TX | UART_EV_RX); mask = irq_getmask(); mask |= 1 << UART_INTERRUPT; irq_setmask(mask); }
void slowout_init() { unsigned int mask; produce = 0; consume = 0; level = 0; cts = 1; /* Reset timer */ CSR_TIMER1_CONTROL = 0; irq_ack(IRQ_TIMER1); mask = irq_getmask(); mask |= IRQ_TIMER1; irq_setmask(mask); printf("SLO: slow outputs initialized\n"); }
void tmu_init() { unsigned int mask; frequency = get_board_desc()->clk_frequency; produce = 0; consume = 0; level = 0; cts = 1; CSR_TMU_CTL = 0; irq_ack(IRQ_TMU); mask = irq_getmask(); mask |= IRQ_TMU; irq_setmask(mask); printf("TMU: texture mapping unit initialized\n"); }
void pfpu_init() { unsigned int mask; /* Reset PFPU */ CSR_PFPU_CTL = 0; irq_ack(IRQ_PFPU); produce = 0; consume = 0; level = 0; cts = 1; mask = irq_getmask(); mask |= IRQ_PFPU; irq_setmask(mask); printf("FPU: programmable floating point unit initialized\n"); }