void dis_irq() {
int i = 0;
irq_set_mask(0x02);
irq_disable();
isr_table_clr();
for (i = 0; i < MAX_SCU_SLAVES; i++) {
icounter[i] = 0; //reset counter in ISR
}
}
bool irq_add_handler(int irq_num, size_t addr) {
for( unsigned int i=0;i<irq_handlers[irq_num].length();i++ ) {
if( irq_handlers[irq_num].get(i) == addr ) {
return false;
}
}
irq_handlers[irq_num].add(addr);
irq_set_mask(irq_num, false);
return true;
}
void block_for_irq(int irq) {
if((irq < 0) || (irq > 15))
return;
waiting_for = irq;
unsigned short mask = pic_get_mask();
set_all_irq_status(true);
irq_set_mask(irq, false);
while(true) {
system_wait_for_interrupt();
if(waiting_for == -1)
break;
}
pic_set_mask(mask);
}
void init_irq() {
int i;
//SCU Bus Master
scub_base[GLOBAL_IRQ_ENA] = 0x20; //enable slave irqs
scub_irq_base[0] = 0x1; // reset irq master
scub_irq_base[2] = 0xfff; //enable all slaves
for (i = 0; i < 12; i++) {
scub_irq_base[8] = i; //channel select
scub_irq_base[9] = 0x08154711; //msg
scub_irq_base[10] = 0x200300 + ((i+1) << 2); //destination address, do not use lower 2 bits
}
isr_table_clr();
isr_ptr_table[1] = &isr1;
irq_set_mask(0x02);
irq_enable();
mprintf("MSI IRQs configured.\n");
}
int main()
{
uint32_t gpio=0;
uint8_t c;
uint32_t flag;
uint32_t pruebah=0;
uint32_t hbe=0; //el enable ha sido activado
uint32_t x1=0; // valor del contador en segundos flanco positivo
uint32_t x2=0; // valor del contador en segundos flanco negativo
uint32_t tiempo; // valor del contador
uint32_t i=0;
c='u'; // Initialize UART
gpio0->dir=0x00;
//for(;;)
//prueba();
//tic_init();
irq_set_mask(0x02);
irq_enable();
for(;;);
/*
if (1800 < tem <2100)
gpio=1;
else
gpio=0;
data = data<<1 + gpio;
uart_putchar(data); */
}
int main(int argc, char **argv)
{
// Initialize TIC
isr_init();
tic_init();
irq_set_mask(0x000FFFFF);
//irq_enable();
// Initialize I2C Core
i2c_core_init(0x00, 0xC7);
//MPU6050_Initialize();
for(;;)
{
i2c_write_register(MPU6050_DEFAULT_ADDRESS, MPU6050_RA_WHO_AM_I, 0x00);
}
//i2c_test();
//spi_test();
//gpio_test();
//uart_test();
//timer_test();
}
int main()
{
char test2[] = "Lokalerstr";
char *str = test2;
uint32_t i;
// for (i = 0; i < 4; i++)
// test2[i] = 'l';
// glob[0] = 'g';
// Initialize stuff
uart_init();
// Say Hello!
uart_putstr( "** Spike Test Firmware **\n" );
// Initialize TIC
isr_init();
tic_init();
irq_set_mask( 0x00000002 );
irq_enable();
// Say Hello!
uart_putstr( "Timer Interrupt instelled.\n" );
// Do some trivial tests
uart_putstr( "Subroutine-Return Test: " );
test();
uart_putchar('\n');
uart_putstr( "Local-Pointer Test:" );
for (;*str; str++) {
uart_putchar(*str);
}
uart_putchar('\n');
uart_putstr( "Global-Pointer Test:" );
str = glob;
for (;*str; str++) {
uart_putchar(*str);
}
uart_putchar('\n');
uart_putstr( "Stack Pointer : " );
writeint(get_sp());
uart_putchar('\n');
uart_putstr( "Global Pointer: " );
writeint(get_gp());
uart_putchar('\n');
uart_putstr( "Timer Test (1s): " );
for(i=0; i<4; i++) {
uart_putstr("tic...");
msleep(1000);
}
uart_putchar('\n');
uart_putstr( "Timer Interrupt counter: " );
writeint( tic_msec );
uart_putchar('\n');
int val = tic_msec;
uart_putstr( "Shift: " );
writeint( val );
uart_putstr(" <-> ");
for(i=0; i<32; i++) {
if (val & 0x80000000)
uart_putchar( '1' );
else
uart_putchar( '0' );
val <<= 1;
}
uart_putstr("\r\n");
uart_putstr( "GPIO Test..." );
gpio0->oe = 0x000000ff;
for(;;) {
for(i=0; i<8; i++) {
uint32_t out1, out2;
out1 = 0x01 << i;
out2 = 0x80 >> i;
gpio0->out = out1 | out2;
msleep(100);
}
}
/*
uart_putstr( "Memory Dump: " );
uint32_t *start = (uint32_t *)0x40000000;
uint32_t *end = (uint32_t *)0x40000100;
uint32_t *p;
for (p=start; p<end; p++) {
if (((uint32_t)p & 12) == 0) {
uart_putstr("\r\n[");
writeint((uint32_t) p);
uart_putchar(']');
}
uart_putchar(' ');
writeint(*p);
}
*/
uart_putstr("Entering Echo Test...\n");
while (1) {
uart_putchar(uart_getchar());
}
}
int main(int argc, char **argv) {
local_exceptions_init();
// example is too fast/boring with caches on, so don't
//mmu_simple_init();
video_init(1280, 1024);
rp = graphics_init(FBADDR, WIDTH, HEIGHT, BM_RGB16);
omap_attach_framebuffer(0, rp->drawable.bitmap);
// also set it to the tv out (top-left corner of same data)
omap_attach_framebuffer(VID_VID2 | VID_TVOUT, rp->drawable.bitmap);
moveTo(rp, 0, 0);
setColour(rp, 0x3e31a2);
drawRect(rp, WIDTH, HEIGHT);
// setup tasks to run
int i;
NewList(&tasks);
dprintf("tasks %08x, Head=%08x Tail=%08x TailPred=%08x\n",
&tasks, tasks.Head, tasks.Tail, tasks.TailPred);
for (i=0;taskinit[i];i++ ){
struct task *t = taskinit[i];
// set initial pc and proc state
t->tcb.pc = taskpc[i];
// runs in user mode
t->tcb.spsr = 0x10;
// initial argument 0 in reg 0
t->tcb.regs[0] = i;
t->id = i;
int j;
for (j=1;j<10;j++)
t->tcb.regs[j] = j;
// initial stack - 4K each, before 32K of master stack
t->tcb.regs[13] = 0x88000000 - 32768 - i*4096;
AddTail((struct List *)&tasks, &t->Node);
dprintf("adding task %d = %08x pc=%08x sp=%08x\n", i, t, t->tcb.pc, t->tcb.regs[13]);
}
dprintf("tasks %08x, Head=%08x Tail=%08x TailPred=%08x\n",
&tasks, tasks.Head, tasks.Tail, tasks.TailPred);
// set task 0 to `execute first' (it's actually us)
thistask = &t1;
fptask = 0;
irq_new_task(tcb_to_sp(&thistask->tcb));
// add an irq handler for the vsync interrupt (lcd display?)
irq_set_handler(INTC_DSS_IRQ, dispc_handler);
irq_set_mask(INTC_DSS_IRQ, 1);
// disable all but vsync
reg32w(DISPC_BASE, DISPC_IRQENABLE, DISPC_VSYNC);
reg32w(DISPC_BASE, DISPC_IRQSTATUS, ~0);
// dss intterrupt can also receive DSI, so disable those too
reg32w(DSI_BASE, DSI_IRQENABLE, 0);
reg32w(DSI_BASE, DSI_IRQSTATUS, ~0);
dprintf("enabling interrupts\n");
// data barrier for previous register writes
asm volatile("dsb");
// turn on irq's, which enables task switching
irq_enable();
// jump to user mode - we are now 'task 0'
asm volatile("cps #0x10");
asm volatile("ldr sp,=0x88000000 - 32768");
task1(0);
return 0;
}
int main(int argc, char **argv) {
local_exceptions_init();
// example is too fast/boring with caches on, so don't
//mmu_simple_init();
video_init(1280, 1024);
rp = graphics_init(FBADDR, WIDTH, HEIGHT, BM_RGB16);
omap_attach_framebuffer(0, rp->drawable.bitmap);
// also set it to the tv out (top-left corner of same data)
omap_attach_framebuffer(VID_VID2 | VID_TVOUT, rp->drawable.bitmap);
moveTo(rp, 0, 0);
setColour(rp, 0x3e31a2);
drawRect(rp, WIDTH, HEIGHT);
// setup tasks to run
int i;
NewList(&tasks);
dprintf("tasks %08x, Head=%08x Tail=%08x TailPred=%08x\n",
&tasks, tasks.Head, tasks.Tail, tasks.TailPred);
for (i=0;taskinit[i];i++ ){
struct task *t = taskinit[i];
// set initial pc and proc state
t->tcb.pc = (uint32_t)task;
// runs in user mode
t->tcb.spsr = 0x10;
// initial argument 0 in reg 0
t->tcb.regs[0] = i;
t->id = i;
int j;
for (j=1;j<10;j++)
t->tcb.regs[j] = j;
// initial stack - 4K each, before 32K of master stack
t->tcb.regs[13] = 0x88000000 - 32768 - i*4096;
AddTail((struct List *)&tasks, &t->Node);
dprintf("adding task %d = %08x pc=%08x sp=%08x\n", i, t, t->tcb.pc, t->tcb.regs[13]);
}
dprintf("tasks %08x, Head=%08x Tail=%08x TailPred=%08x\n",
&tasks, tasks.Head, tasks.Tail, tasks.TailPred);
// set task 0 to `execute first' (it's actually us)
thistask = &t1;
irq_new_task(tcb_to_sp(&thistask->tcb));
//
// Setup timer interrupt via GPTIMER1
//
// timer off
reg32s(GPTIMER1_BASE, GPT_TCLR, 1, 0);
// Sets true 1Khz rate w/ 32768Hz clock: S 16.2.4.3 TRM D
reg32w(GPTIMER1_BASE, GPT_TPIR, 232000);
reg32w(GPTIMER1_BASE, GPT_TNIR, -768000);
reg32w(GPTIMER1_BASE, GPT_TLDR, 0xffffffe0);
reg32w(GPTIMER1_BASE, GPT_TCRR, 0xffffffe0);
// clear int status bits
reg32w(GPTIMER1_BASE, GPT_TISR, ~0);
// enable overflow int
reg32w(GPTIMER1_BASE, GPT_TIER, OVF_IT_FLAG);
// dividisor = 100 -> 10Hz so it's visible
reg32w(GPTIMER1_BASE, GPT_TOCR, 0);
reg32w(GPTIMER1_BASE, GPT_TOWR, 100);
irq_set_handler(INTC_GPT1_IRQ, gptimer1_handler);
irq_set_mask(INTC_GPT1_IRQ, 1);
// force 32K clock
reg32s(0x48004c00, 0x40, 1, 0);
// turn timer back on
reg32s(GPTIMER1_BASE, GPT_TCLR, 1|2|(2<<10), ~0);
dprintf("enabling interrupts\n");
// data barrier for previous register writes
asm volatile("dsb");
// turn on irq's, which enables task switching
irq_enable();
// jump to user mode - we are now 'task 0'
asm volatile("cps #0x10");
asm volatile("ldr sp,=0x88000000 - 32768");
task(0);
return 0;
}
