// Helper Functions for Ntk Construction Validation Check
const bool
V3Ntk::reportInvertingNet(const V3NetId& id) const {
assert (validNetId(id));
if (isV3NetInverted(id))
Msg(MSG_ERR) << "Unexpected Inverting Net = " << id.id << endl;
else return false;
return true;
}
void
V3NtkElaborate::elaboratePOConstraints(const uint32_t& start, const uint32_t& end, V3NetVec& constrList) {
V3Ntk* const ntk = _handler->getNtk(); assert (ntk);
assert (start < ntk->getOutputSize() && end < ntk->getOutputSize());
constrList.clear(); if (!_ntk || !_p2cMap.size()) return;
// Elaborate Constraint Logics
if (start <= end) { // Fwd-Order Construction
constrList.reserve(end - start);
for (uint32_t i = start; i <= end; ++i) {
assert (ntk->getOutput(i).id < _p2cMap.size());
assert (1 == ntk->getNetWidth(ntk->getOutput(i)));
if (V3NetUD != _p2cMap[ntk->getOutput(i).id]) continue;
constrList.push_back(V3NetId::makeNetId(ntk->getOutput(i).id));
}
}
else { // Rev-Order Construction
uint32_t i = 1 + start; assert (i > start); constrList.reserve(start - end);
while (i-- > end) {
assert (ntk->getOutput(i).id < _p2cMap.size());
assert (1 == ntk->getNetWidth(ntk->getOutput(i)));
if (V3NetUD != _p2cMap[ntk->getOutput(i).id]) continue;
constrList.push_back(V3NetId::makeNetId(ntk->getOutput(i).id));
}
}
if (constrList.size()) attachToNtk(_handler, _ntk, constrList, _p2cMap, _c2pMap, _netHash);
// Put Constraints into List
constrList.clear();
if (start <= end) { // Fwd-Order Construction
for (uint32_t i = start; i <= end; ++i) {
const V3NetId id = ntk->getOutput(i); assert (V3NetUD != _p2cMap[id.id]);
constrList.push_back(isV3NetInverted(id) ? getV3InvertNet(_p2cMap[id.id]) : _p2cMap[id.id]);
}
}
else { // Rev-Order Construction
uint32_t i = 1 + start; assert (i > start);
while (i-- > end) {
const V3NetId id = ntk->getOutput(i); assert (V3NetUD != _p2cMap[id.id]);
constrList.push_back(isV3NetInverted(id) ? getV3InvertNet(_p2cMap[id.id]) : _p2cMap[id.id]);
}
}
}
void
V3SvrBoolector::add_FF_Formula(const V3NetId& out, const uint32_t& depth) {
// Check Output Validation
assert (validNetId(out)); assert (V3_FF == _ntk->getGateType(out)); assert (!getVerifyData(out, depth));
const uint32_t index = getV3NetIndex(out); assert (depth == _ntkData[index].size());
const uint32_t width = _ntk->getNetWidth(out); assert (width);
if (_freeBound) {
// Set BtorExp*
_ntkData[index].push_back(boolector_var(_Solver, width, NULL));
}
else if (depth) {
// Build FF I/O Relation
const V3NetId in1 = _ntk->getInputNetId(out, 0); assert (validNetId(in1));
BtorExp* const exp1 = getVerifyData(in1, depth - 1); assert (exp1);
// Set BtorExp*
_ntkData[index].push_back(boolector_copy(_Solver, exp1));
}
else {
// Set BtorExp*
_ntkData[index].push_back(boolector_var(_Solver, width, NULL));
BtorExp* const exp = _ntkData[index].back(); assert (exp);
// Build FF Initial State
const V3NetId in1 = _ntk->getInputNetId(out, 1); assert (validNetId(in1));
const V3BvNtk* const ntk = dynamic_cast<const V3BvNtk*>(_ntk);
if (ntk) {
if (BV_CONST == ntk->getGateType(in1)) {
const V3BitVecX* const value = ntk->getInputConstValue(in1);
assert (value); assert (width == value->size());
char* bv_value = new char[width + 1]; bv_value[width] = '\0';
for (uint32_t i = 0, j = width - 1; i < width; ++i, --j) bv_value[j] = (*value)[i];
BtorExp* const init_exp = boolector_const(_Solver, bv_value); assert (init_exp);
_init.push_back(boolector_eq(_Solver, exp, init_exp));
delete[] bv_value; boolector_release(_Solver, init_exp);
}
else { // Build Initial Circuit
BtorExp* const exp1 = getVerifyData(in1, 0); assert (exp1);
_init.push_back(boolector_eq(_Solver, exp, exp1));
}
}
else {
if (AIG_FALSE == _ntk->getGateType(in1))
_init.push_back(!isV3NetInverted(in1) ? boolector_not(_Solver, exp) : boolector_copy(_Solver, exp));
else { // Build Initial Circuit
BtorExp* const exp1 = getVerifyData(in1, 0); assert (exp1);
_init.push_back(boolector_eq(_Solver, exp, exp1));
}
}
}
assert (getVerifyData(out, depth));
}
const V3NetId
V3Ntk::createNet(const uint32_t& width) {
// Validation Check
if (width != 1) {
Msg(MSG_ERR) << "Unexpected Net width = " << width << " in Base / AIG Network !!" << endl;
return V3NetUD;
}
assert (_inputData.size() == _typeMisc.size());
// Create New V3NetId
V3NetId id = V3NetId::makeNetId(_inputData.size()); assert (!isV3NetInverted(id));
_typeMisc.push_back(V3MiscType()); _inputData.push_back(V3InputVec());
assert (V3_PI == _typeMisc.back().type); assert (!_typeMisc.back().misc);
assert (!_inputData.back().size()); return id;
}
const V3NetId
V3NtkElaborate::getCurrentNetId(const V3NetId& id, const uint32_t& index) const {
if (V3NetUD == id || _p2cMap.size() <= id.id) return V3NetUD;
return (isV3NetInverted(id) ? getV3InvertNet(_p2cMap[id.id]) : _p2cMap[id.id]);
}
// Net Ancestry Functions
const V3NetId
V3NtkElaborate::getParentNetId(const V3NetId& id) const {
if (V3NetUD == id || _c2pMap.size() <= id.id) return V3NetUD;
return (isV3NetInverted(id) ? getV3InvertNet(_c2pMap[id.id]) : _c2pMap[id.id]);
}
const V3NetId
V3NtkExpand2::getCurrentNetId(const V3NetId& id, const uint32_t& index) const {
if (V3NetUD == id || !_p2cMap.size() || _p2cMap[0].size() <= id.id) return V3NetUD; assert (index < _cycle);
return isV3NetInverted(id) ? getV3InvertNet(_p2cMap[index][getV3NetIndex(id)]) : _p2cMap[index][getV3NetIndex(id)];
}
const V3NetId
V3NtkExpand2::getParentNetId(const V3NetId& id) const {
if (V3NetUD == id || _c2pMap.size() <= id.id || V3NetUD == _c2pMap[id.id]) return V3NetUD;
return isV3NetInverted(id) ? getV3InvertNet(_c2pMap[getV3NetIndex(id)]) : _c2pMap[getV3NetIndex(id)];
}
void
V3Ntk::createConst(const V3NetId& id) {
assert (validNetId(id)); assert (!isV3NetInverted(id));
createGate(dynamic_cast<const V3BvNtk*>(this) ? BV_CONST : AIG_FALSE, id); _ConstList.push_back(id);
}
void
V3Ntk::createLatch(const V3NetId& id) {
assert (validNetId(id)); assert (!isV3NetInverted(id));
createGate(V3_FF, id); _FFList.push_back(id);
}
void
V3Ntk::createInout(const V3NetId& id) {
assert (validNetId(id)); assert (!isV3NetInverted(id));
createGate(V3_PIO, id); _IOList[2].push_back(id);
}
void
V3Ntk::createInput(const V3NetId& id) {
assert (validNetId(id)); assert (!isV3NetInverted(id));
assert (!reportMultipleDrivenNet(V3_PI, id));
_IOList[0].push_back(id);
}
