HAL_BOOL
ar5210SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,
u_int pktLen,
u_int hdrLen,
HAL_PKT_TYPE type,
u_int txPower,
u_int txRate0, u_int txTries0,
u_int keyIx,
u_int antMode,
u_int flags,
u_int rtsctsRate,
u_int rtsctsDuration,
u_int compicvLen,
u_int compivLen,
u_int comp)
{
struct ar5210_desc *ads = AR5210DESC(ds);
uint32_t frtype;
(void) txPower;
(void) rtsctsDuration;
HALASSERT(txTries0 != 0);
HALASSERT(isValidPktType(type));
HALASSERT(isValidTxRate(txRate0));
if (type == HAL_PKT_TYPE_BEACON || type == HAL_PKT_TYPE_PROBE_RESP)
frtype = AR_Frm_NoDelay;
else
frtype = type << 26;
ads->ds_ctl0 = (pktLen & AR_FrameLen)
| (txRate0 << AR_XmitRate_S)
| ((hdrLen << AR_HdrLen_S) & AR_HdrLen)
| frtype
| (flags & HAL_TXDESC_CLRDMASK ? AR_ClearDestMask : 0)
| (flags & HAL_TXDESC_INTREQ ? AR_TxInterReq : 0)
| (antMode ? AR_AntModeXmit : 0)
;
if (keyIx != HAL_TXKEYIX_INVALID) {
ads->ds_ctl1 = (keyIx << AR_EncryptKeyIdx_S) & AR_EncryptKeyIdx;
ads->ds_ctl0 |= AR_EncryptKeyValid;
} else
ads->ds_ctl1 = 0;
if (flags & HAL_TXDESC_RTSENA) {
ads->ds_ctl0 |= AR_RTSCTSEnable;
ads->ds_ctl1 |= (rtsctsDuration << AR_RTSDuration_S)
& AR_RTSDuration;
}
return AH_TRUE;
}
HAL_BOOL
ar5211SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,
u_int pktLen,
u_int hdrLen,
HAL_PKT_TYPE type,
u_int txPower,
u_int txRate0, u_int txTries0,
u_int keyIx,
u_int antMode,
u_int flags,
u_int rtsctsRate,
u_int rtsctsDuration,
u_int compicvLen,
u_int compivLen,
u_int comp)
{
struct ar5211_desc *ads = AR5211DESC(ds);
(void) hdrLen;
(void) txPower;
(void) rtsctsRate; (void) rtsctsDuration;
HALASSERT(txTries0 != 0);
HALASSERT(isValidPktType(type));
HALASSERT(isValidTxRate(txRate0));
/* XXX validate antMode */
ads->ds_ctl0 = (pktLen & AR_FrameLen)
| (txRate0 << AR_XmitRate_S)
| (antMode << AR_AntModeXmit_S)
| (flags & HAL_TXDESC_CLRDMASK ? AR_ClearDestMask : 0)
| (flags & HAL_TXDESC_INTREQ ? AR_TxInterReq : 0)
| (flags & HAL_TXDESC_RTSENA ? AR_RTSCTSEnable : 0)
| (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
;
ads->ds_ctl1 = (type << 26)
| (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0)
;
if (keyIx != HAL_TXKEYIX_INVALID) {
ads->ds_ctl1 |=
(keyIx << AR_EncryptKeyIdx_S) & AR_EncryptKeyIdx;
ads->ds_ctl0 |= AR_EncryptKeyValid;
}
return AH_TRUE;
#undef RATE
}
HAL_BOOL
ar5416SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,
u_int pktLen,
u_int hdrLen,
HAL_PKT_TYPE type,
u_int txPower,
u_int txRate0, u_int txTries0,
u_int key_ix,
u_int antMode,
u_int flags,
u_int rts_cts_rate,
u_int rts_cts_duration,
u_int compicvLen,
u_int compivLen,
u_int comp)
{
#define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)
struct ar5416_desc *ads = AR5416DESC(ds);
(void) hdrLen;
ads->ds_txstatus9 &= ~AR_TxDone;
HALASSERT(txTries0 != 0);
HALASSERT(isValidPktType(type));
HALASSERT(isValidTxRate(txRate0));
HALASSERT((flags & RTSCTS) != RTSCTS);
/* XXX validate antMode */
/*
* If descriptor-based tpc, tx power is controlled by
* ar5416Set11nRateScenario().
* If not, what you put in the descriptor is ignored anyway.
*/
txPower = 0;
ads->ds_ctl0 = (pktLen & AR_FrameLen)
| (txPower << AR_XmitPower0_S)
| (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
| (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
| (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0)
;
ads->ds_ctl1 = (type << AR_FrameType_S)
| (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0);
ads->ds_ctl2 = SM(txTries0, AR_XmitDataTries0)
;
ads->ds_ctl3 = (txRate0 << AR_XmitRate0_S)
;
ads->ds_ctl7 = SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel0)
| SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel1)
| SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel2)
| SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel3)
;
if (key_ix != HAL_TXKEYIX_INVALID) {
/* XXX validate key index */
ads->ds_ctl1 |= SM(key_ix, AR_DestIdx);
ads->ds_ctl0 |= AR_DestIdxValid;
}
if (flags & RTSCTS) {
if (!isValidTxRate(rts_cts_rate)) {
HDPRINTF(ah, HAL_DBG_TXDESC, "%s: invalid rts/cts rate 0x%x\n",
__func__, rts_cts_rate);
return AH_FALSE;
}
/* XXX validate rts_cts_duration */
ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0)
| (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0)
;
ads->ds_ctl2 |= SM(rts_cts_duration, AR_BurstDur);
ads->ds_ctl3 |= (rts_cts_rate << AR_RTSCTSRate_S);
}
return AH_TRUE;
#undef RTSCTS
}
HAL_BOOL ar5416SetupTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
a_uint32_t pktLen,
a_uint32_t hdrLen,
HAL_PKT_TYPE type,
a_uint32_t txPower,
a_uint32_t txRate0, a_uint32_t txTries0,
a_uint32_t keyIx,
a_uint32_t antMode,
a_uint32_t flags,
a_uint32_t rtsctsRate,
a_uint32_t rtsctsDuration,
a_uint32_t compicvLen,
a_uint32_t compivLen,
a_uint32_t comp)
{
#define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)
struct ar5416_desc *ads = AR5416DESC(ds);
(void) hdrLen;
ads->ds_txstatus9 &= ~AR_TxDone;
HALASSERT(txTries0 != 0);
HALASSERT(isValidPktType(type));
HALASSERT(isValidTxRate(txRate0));
HALASSERT((flags & RTSCTS) != RTSCTS);
if (txPower > 63)
txPower=63;
ads->ds_ctl0 = (pktLen & AR_FrameLen)
| (txPower << AR_XmitPower_S)
| (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
| (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
| (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0);
ads->ds_ctl1 = (type << AR_FrameType_S)
| (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0);
ads->ds_ctl2 = SM(txTries0, AR_XmitDataTries0);
ads->ds_ctl3 = (txRate0 << AR_XmitRate0_S);
ads->ds_ctl7 = SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel0)
| SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel1)
| SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel2)
| SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel3);
if (keyIx != HAL_TXKEYIX_INVALID) {
/* XXX validate key index */
ads->ds_ctl1 |= SM(keyIx, AR_DestIdx);
ads->ds_ctl0 |= AR_DestIdxValid;
}
if (flags & RTSCTS) {
if (!isValidTxRate(rtsctsRate)) {
return AH_FALSE;
}
/* XXX validate rtsctsDuration */
ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0)
| (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0);
ads->ds_ctl2 |= SM(rtsctsDuration, AR_BurstDur);
ads->ds_ctl3 |= (rtsctsRate << AR_RTSCTSRate_S);
}
return AH_TRUE;
#undef RTSCTS
}
