int
ar7240_mem_config(void)
{
#if !defined(CONFIG_WASP_EMU)
unsigned int tap_val1, tap_val2;
ar7240_ddr_initial_config(CFG_DDR_REFRESH_VAL);
/* Default tap values for starting the tap_init*/
if (!(is_ar7241() || is_ar7242())) {
ar7240_reg_wr (AR7240_DDR_TAP_CONTROL0, 0x8);
ar7240_reg_wr (AR7240_DDR_TAP_CONTROL1, 0x9);
ar7240_ddr_tap_init();
}
else {
ar7240_reg_wr (AR7240_DDR_TAP_CONTROL0, 0x2);
ar7240_reg_wr (AR7240_DDR_TAP_CONTROL1, 0x2);
ar7240_reg_wr (AR7240_DDR_TAP_CONTROL2, 0x0);
ar7240_reg_wr (AR7240_DDR_TAP_CONTROL3, 0x0);
}
tap_val1 = ar7240_reg_rd(0xb800001c);
tap_val2 = ar7240_reg_rd(0xb8000020);
printf("#### TAP VALUE 1 = 0x%x, 2 = 0x%x [0x%x: 0x%x]\n",
tap_val1, tap_val2, *(unsigned *)0x80500000,
*(unsigned *)0x80500004);
ar7240_usb_initial_config();
ar7240_gpio_config();
#endif
return (ar7240_ddr_find_size());
}
int
ar7240_mem_config(void)
{
#ifndef COMPRESSED_UBOOT
unsigned int tap_val1, tap_val2;
#endif
ar7240_ddr_initial_config(CFG_DDR_REFRESH_VAL);
/* Default tap values for starting the tap_init*/
if (!(is_ar7241() || is_ar7242())) {
ar7240_reg_wr (AR7240_DDR_TAP_CONTROL0, 0x8);
ar7240_reg_wr (AR7240_DDR_TAP_CONTROL1, 0x9);
#ifndef COMPRESSED_UBOOT
ar7240_ddr_tap_init();
#endif
}
else {
ar7240_reg_wr (AR7240_DDR_TAP_CONTROL0, 0x2);
ar7240_reg_wr (AR7240_DDR_TAP_CONTROL1, 0x2);
ar7240_reg_wr (AR7240_DDR_TAP_CONTROL2, 0x0);
ar7240_reg_wr (AR7240_DDR_TAP_CONTROL3, 0x0);
}
#ifndef COMPRESSED_UBOOT
tap_val1 = ar7240_reg_rd(0xb800001c);
tap_val2 = ar7240_reg_rd(0xb8000020);
printf("#### TAP VALUE 1 = %x, 2 = %x\n",tap_val1, tap_val2);
#endif
ar7240_usb_initial_config();
ar7240_gpio_config();
return (ar7240_ddr_find_size());
}
int ar7240_platform_init(void)
{
int ret;
/* need to set clock appropriately */
#ifdef CONFIG_WASP_SUPPORT
ar7240_uart_data[0].uartclk = ath_ref_clk_freq;
#else
ar7240_uart_data[0].uartclk = ar7240_ahb_freq;
#endif
#if 1
ret = platform_add_devices(ar724x_platform_devices,
ARRAY_SIZE(ar724x_platform_devices));
printk("===== ar7240_platform_init: %d\n", ret);
if (ret < 0)
return ret;
#endif
if (is_ar7241() || is_ar7242() || is_ar933x() || is_wasp()) {
return (platform_add_devices(ar7241_platform_devices,
ARRAY_SIZE(ar7241_platform_devices)));
}
if (is_ar7240()) {
return (platform_add_devices(ar7240_platform_devices,
ARRAY_SIZE(ar7240_platform_devices)));
}
return 0;
}
void plat_dev_init(void)
{
u32 val;
u32 addr;
u32 BaseAddr = 0x10000000;
u32 CalAddr = WLANCAL;
volatile u16 *calData;
/*
* Copy the device ID from Flash to device config space.
*/
calData = (u16 *)CalAddr;
#ifndef CONFIG_PCI_CONFIG_DATA_IN_OTP
if(calData[0] != 0xa55a && calData[0] != 0x5aa5 )
{
/*
** Board is not calibrated.
*/
#ifndef COMPRESSED_UBOOT
printf("BOARD IS NOT CALIBRATED!!!\n");
#endif
return;
}
#else
return;
#endif
/*
** Need to setup the PCI device to access the internal registers
*/
if ((is_ar7241() || is_ar7242()))
ar7240_pci_write_config(&hose, NULL, 0x10, 0x1000ffff);
else
ar7240_pci_write_config(&hose, NULL, 0x10, 0xffff);
ar7240_pci_write_config(&hose, NULL, 0x04, 0x6);
/*
** Set pointer to first reg address
*/
calData += AR7240_ART_PCICFG_OFFSET;
while(*calData != 0xffff)
{
u16 cd;
cd = *calData++;
addr = BaseAddr + cd;
val = *calData++;
val |= (*calData++) << 16;
ar7240_reg_wr_nf(addr,val);
udelay(100);
}
return;
}
int checkboard (void)
{
if ((is_ar7241() || is_ar7242()))
printf("AP99 (ar7241 - Virian) U-boot\n");
else
printf("AP99 (ar7240 - Python) U-boot\n");
return 0;
}
int checkboard (char *board_string)
{
if ((is_ar7241() || is_ar7242()))
strcpy(board_string, "AP98 (ar7241 - Virian) Compressed U-boot");
else
strcpy(board_string, "AP98 (ar7240 - Python) Compressed U-boot");
return 0;
}
void
ar7240_ddr_initial_config(uint32_t refresh)
{
int ddr2 = 0,ddr_config;
int ddr_config2,ext_mod,ddr2_ext_mod;
int mod_val,mod_val_init;
#if 0
ar7240_reg_wr(AR7240_RESET, AR7240_RESET_DDR);
udelay(10);
#endif
ddr2 = ((ar7240_reg_rd(0xb8050020) & 0x1) == 0);
#ifdef ENABLE_DYNAMIC_CONF
if(*(volatile int *)CFG_DDR_MAGIC_F == CFG_DDR_MAGIC){
ddr_config = CFG_DDR_CONFIG_VAL_F;
ddr_config2 = CFG_DDR_CONFIG2_VAL_F;
ext_mod = CFG_DDR_EXT_MODE_VAL_F;
ddr2_ext_mod = ext_mod;
}
else
#endif
{
#ifdef CONFIG_SUPPORT_AR7241
if (is_ar7241() || is_ar7242()) {
if (ddr2) {
printf("%s(%d): virian ddr2 init\n", __func__, __LINE__);
ddr_config = CFG_7241_DDR2_CONFIG_VAL;
ddr_config2 = CFG_7241_DDR2_CONFIG2_VAL;
ext_mod = CFG_7241_DDR2_EXT_MODE_VAL;
ddr2_ext_mod = CFG_DDR2_EXT_MODE_VAL;
mod_val_init = CFG_7241_DDR2_MODE_VAL_INIT;
mod_val = CFG_7241_DDR2_MODE_VAL;
} else {
//printf("%s(%d): virian ddr1 init\n", __func__, __LINE__);
ddr_config = CFG_7241_DDR1_CONFIG_VAL;
ddr_config2 = CFG_7241_DDR1_CONFIG2_VAL;
ext_mod = CFG_7241_DDR1_EXT_MODE_VAL;
ddr2_ext_mod = CFG_DDR2_EXT_MODE_VAL;
mod_val_init = CFG_7241_DDR1_MODE_VAL_INIT;
mod_val = CFG_7241_DDR1_MODE_VAL;
}
}
else
#endif
{
printf("%s(%d): python ddr init\n", __func__, __LINE__);
ddr_config = CFG_DDR_CONFIG_VAL;
ddr_config2 = CFG_DDR_CONFIG2_VAL;
ext_mod = CFG_DDR_EXT_MODE_VAL;
ddr2_ext_mod = CFG_DDR2_EXT_MODE_VAL;
mod_val_init = CFG_DDR_MODE_VAL_INIT;
mod_val = CFG_DDR_MODE_VAL;
}
}
if (ddr2) {
ar7240_reg_wr_nf(0xb800008c, 0xA59);
udelay(100);
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x10);
udelay(10);
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x20);
udelay(10);
}
ar7240_reg_wr_nf(AR7240_DDR_CONFIG, ddr_config);
udelay(100);
ar7240_reg_wr_nf(AR7240_DDR_CONFIG2, ddr_config2 | 0x80);
udelay(100);
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x8);
udelay(10);
ar7240_reg_wr_nf(AR7240_DDR_MODE, mod_val_init);
udelay(1000);
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x1);
udelay(10);
if (ddr2) {
ar7240_reg_wr_nf(AR7240_DDR_EXT_MODE, ddr2_ext_mod);
} else {
ar7240_reg_wr_nf(AR7240_DDR_EXT_MODE, ext_mod);
}
udelay(100);
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x2);
udelay(10);
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x8);
udelay(10);
ar7240_reg_wr_nf(AR7240_DDR_MODE, mod_val);
udelay(100);
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x1);
udelay(10);
ar7240_reg_wr_nf(AR7240_DDR_REFRESH, refresh);
udelay(100);
ar7240_reg_wr_nf(AR7240_DDR_RD_DATA_THIS_CYCLE,
CFG_DDR_RD_DATA_THIS_CYCLE_VAL);
udelay(100);
}
static int ag7240_check_link(ag7240_mac_t *mac)
{
u32 link, duplex, speed, fdx;
ag7240_phy_link(mac->mac_unit, &link);
ag7240_phy_duplex(mac->mac_unit, &duplex);
ag7240_phy_speed(mac->mac_unit, &speed);
mac->link = link;
#ifdef SUPPORT_PLC
if(strcmp(mac->dev->name, "eth0") == 0) {
printf("ag7240_check_link: %s link forced down\n",mac->dev->name);
return 0;
}
#endif
if(!mac->link) {
printf("%s link down\n",mac->dev->name);
return 0;
}
switch (speed)
{
case _1000BASET:
ag7240_set_mac_if(mac, 1);
ag7240_reg_rmw_set(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19));
if (is_ar7242() && (mac->mac_unit == 0)) {
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x1c000000);
}
#ifdef CONFIG_F1E_PHY
if (is_wasp() && (mac->mac_unit == 0)) {
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x0e000000);
}
#elif CONFIG_VIR_PHY
if (is_wasp() && (mac->mac_unit == 0)) {
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x82000000);
ar7240_reg_wr(AG7240_ETH_CFG,0x000c0001);
}
#else
if (is_wasp() && (mac->mac_unit == 0) && !is_f2e()) {
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x06000000);
}
#endif
if (is_wasp() && mac->mac_unit == 0 && is_f1e() ) {
ar7240_reg_rmw_set(AG7240_ETH_CFG,AG7240_ETH_CFG_RXD_DELAY);
ar7240_reg_rmw_set(AG7240_ETH_CFG,AG7240_ETH_CFG_RDV_DELAY);
}
break;
case _100BASET:
ag7240_set_mac_if(mac, 0);
ag7240_set_mac_speed(mac, 1);
ag7240_reg_rmw_clear(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19));
if ((is_ar7242() || is_wasp()) && (mac->mac_unit == 0) && !is_f2e())
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x0101);
if (is_wasp() && mac->mac_unit == 0 && is_f1e()) {
ar7240_reg_rmw_clear(AG7240_ETH_CFG,AG7240_ETH_CFG_RXD_DELAY);
ar7240_reg_rmw_clear(AG7240_ETH_CFG,AG7240_ETH_CFG_RDV_DELAY);
}
break;
case _10BASET:
ag7240_set_mac_if(mac, 0);
ag7240_set_mac_speed(mac, 0);
ag7240_reg_rmw_clear(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19));
if ((is_ar7242() || is_wasp()) && (mac->mac_unit == 0) && !is_f2e())
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x1616);
if (is_wasp() && mac->mac_unit == 0 && is_f1e()) {
ar7240_reg_rmw_clear(AG7240_ETH_CFG,AG7240_ETH_CFG_RXD_DELAY);
ar7240_reg_rmw_clear(AG7240_ETH_CFG,AG7240_ETH_CFG_RDV_DELAY);
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x1313);
}
if (is_f2e()) {
ar7240_reg_rmw_clear(AG7240_ETH_CFG, AG7240_ETH_CFG_RMII_HISPD_GE0);
}
break;
default:
printf("Invalid speed detected\n");
return 0;
}
if (mac->link && (duplex == mac->duplex) && (speed == mac->speed))
return 1;
mac->duplex = duplex;
mac->speed = speed;
printf("dup %d speed %d\n", duplex, speed);
ag7240_set_mac_duplex(mac,duplex);
return 1;
}
static void ag7240_get_ethaddr(struct eth_device *dev)
{
unsigned char *eeprom;
unsigned char *mac = dev->enetaddr;
#ifndef CONFIG_AR7240_EMU
#ifdef CONFIG_ATH_NAND_BR
unsigned char sectorBuff[ATH_ETH_MAC_READ_SIZE];
eeprom = ath_eth_mac_addr(sectorBuff);
if(eeprom == NULL) {
/* mac address will be set to default mac address */
mac[0] = 0xff;
}
else {
#else /* CONFIG_ATH_NAND_BR */
eeprom = ag7240_mac_addr_loc();
#endif /* CONFIG_ATH_NAND_BR */
if (strcmp(dev->name, "eth0") == 0) {
memcpy(mac, eeprom, 6);
} else if (strcmp(dev->name, "eth1") == 0) {
eeprom += 6;
memcpy(mac, eeprom, 6);
} else {
printf("%s: unknown ethernet device %s\n", __func__, dev->name);
return;
}
#ifdef CONFIG_ATH_NAND_BR
}
#endif /* CONFIG_ATH_NAND_BR */
/* Use fixed address if the above address is invalid */
if (mac[0] != 0x00 || (mac[0] == 0xff && mac[5] == 0xff)) {
#else
if (1) {
#endif
mac[0] = 0x00;
mac[1] = 0x03;
mac[2] = 0x7f;
mac[3] = 0x09;
mac[4] = 0x0b;
mac[5] = 0xad;
printf("No valid address in Flash. Using fixed address\n");
} else {
printf("Fetching MAC Address from 0x%p\n", __func__, eeprom);
}
}
int ag7240_enet_initialize(bd_t * bis)
{
struct eth_device *dev[CFG_AG7240_NMACS];
u32 mask, mac_h, mac_l;
int i;
printf("ag934x_enet_initialize...\n");
if(is_ar933x() && (ar7240_reg_rd(AR7240_RESET)!=0))
ar7240_reg_wr(AR7240_RESET,0);
if(is_ar933x()) //Turn on LED
ar7240_reg_wr(AR7240_GPIO_BASE + 0x28 , ar7240_reg_rd(AR7240_GPIO_BASE + 0x28) | (0xF8));
for (i = 0; i < CFG_AG7240_NMACS; i++) {
if ((dev[i] = (struct eth_device *) malloc(sizeof (struct eth_device))) == NULL) {
puts("malloc failed\n");
return 0;
}
if ((ag7240_macs[i] = (ag7240_mac_t *) malloc(sizeof (ag7240_mac_t))) == NULL) {
puts("malloc failed\n");
return 0;
}
memset(ag7240_macs[i], 0, sizeof(ag7240_macs[i]));
memset(dev[i], 0, sizeof(dev[i]));
sprintf(dev[i]->name, "eth%d", i);
ag7240_get_ethaddr(dev[i]);
ag7240_macs[i]->mac_unit = i;
ag7240_macs[i]->mac_base = i ? AR7240_GE1_BASE : AR7240_GE0_BASE ;
ag7240_macs[i]->dev = dev[i];
dev[i]->iobase = 0;
dev[i]->init = ag7240_clean_rx;
dev[i]->halt = ag7240_halt;
dev[i]->send = ag7240_send;
dev[i]->recv = ag7240_recv;
dev[i]->priv = (void *)ag7240_macs[i];
}
#if !defined(CONFIG_ATH_NAND_BR)
mask = AR7240_RESET_GE1_PHY;
ar7240_reg_rmw_set(AR7240_RESET, mask);
udelay(1000 * 100);
ar7240_reg_rmw_clear(AR7240_RESET, mask);
udelay(100);
#endif
mask = AR7240_RESET_GE0_PHY;
ar7240_reg_rmw_set(AR7240_RESET, mask);
udelay(1000 * 100);
ar7240_reg_rmw_clear(AR7240_RESET, mask);
udelay(100);
for (i = 0; i < CFG_AG7240_NMACS; i++) {
eth_register(dev[i]);
#if(CONFIG_COMMANDS & CFG_CMD_MII)
miiphy_register(dev[i]->name, ag7240_miiphy_read, ag7240_miiphy_write);
#endif
ag7240_reg_rmw_set(ag7240_macs[i], AG7240_MAC_CFG1, AG7240_MAC_CFG1_SOFT_RST
| AG7240_MAC_CFG1_RX_RST | AG7240_MAC_CFG1_TX_RST);
if(!i) {
mask = (AR7240_RESET_GE0_MAC | AR7240_RESET_GE1_MAC);
if (is_ar7241() || is_ar7242() || is_wasp())
mask = mask | AR7240_RESET_GE0_MDIO | AR7240_RESET_GE1_MDIO;
printf(" wasp reset mask:%x \n",mask);
ar7240_reg_rmw_set(AR7240_RESET, mask);
udelay(1000 * 100);
ar7240_reg_rmw_clear(AR7240_RESET, mask);
udelay(1000 * 100);
udelay(10 * 1000);
}
ag7240_mii_setup(ag7240_macs[i]);
/* if using header for register configuration, we have to */
/* configure s26 register after frame transmission is enabled */
if (ag7240_macs[i]->mac_unit == 0) { /* WAN Phy */
#ifdef CONFIG_AR7242_S16_PHY
if (is_ar7242() || is_wasp()) {
athrs16_reg_init();
} else
#endif
{
#ifdef CONFIG_ATHRS17_PHY
athrs17_reg_init();
#endif
#ifdef CFG_ATHRS26_PHY
athrs26_reg_init();
#endif
#ifdef CFG_ATHRS27_PHY
printf("s27 reg init \n");
athrs27_reg_init();
#endif
#ifdef CONFIG_F1E_PHY
printf("F1Phy reg init \n");
athr_reg_init();
#endif
#ifdef CONFIG_VIR_PHY
printf("VIRPhy reg init \n");
athr_vir_reg_init();
#endif
#ifdef CONFIG_F2E_PHY
printf("F2Phy reg init \n");
athr_reg_init();
#endif
}
} else {
#ifdef CFG_ATHRS26_PHY
athrs26_reg_init_lan();
#endif
#ifdef CFG_ATHRS27_PHY
printf("s27 reg init lan \n");
athrs27_reg_init_lan();
#endif
}
ag7240_hw_start(ag7240_macs[i]);
ag7240_setup_fifos(ag7240_macs[i]);
udelay(100 * 1000);
{
unsigned char *mac = dev[i]->enetaddr;
printf("%s: %02x:%02x:%02x:%02x:%02x:%02x\n", dev[i]->name,
mac[0] & 0xff, mac[1] & 0xff, mac[2] & 0xff,
mac[3] & 0xff, mac[4] & 0xff, mac[5] & 0xff);
}
mac_l = (dev[i]->enetaddr[4] << 8) | (dev[i]->enetaddr[5]);
mac_h = (dev[i]->enetaddr[0] << 24) | (dev[i]->enetaddr[1] << 16) |
(dev[i]->enetaddr[2] << 8) | (dev[i]->enetaddr[3] << 0);
ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR1, mac_l);
ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR2, mac_h);
ag7240_phy_setup(ag7240_macs[i]->mac_unit);
printf("%s up\n",dev[i]->name);
}
return 1;
}
#if (CONFIG_COMMANDS & CFG_CMD_MII)
int
ag7240_miiphy_read(char *devname, uint32_t phy_addr, uint8_t reg, uint16_t *data)
{
ag7240_mac_t *mac = ag7240_name2mac(devname);
uint16_t addr = (phy_addr << AG7240_ADDR_SHIFT) | reg, val;
volatile int rddata;
uint16_t ii = 0xFFFF;
/*
* Check for previous transactions are complete. Added to avoid
* race condition while running at higher frequencies.
*/
do
{
udelay(5);
rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1;
} while(rddata && --ii);
if (ii == 0)
printf("ERROR:%s:%d transaction failed\n",__func__,__LINE__);
ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, 0x0);
ag7240_reg_wr(mac, AG7240_MII_MGMT_ADDRESS, addr);
ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, AG7240_MGMT_CMD_READ);
do
{
udelay(5);
rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1;
} while(rddata && --ii);
if(ii==0)
printf("Error!!! Leave ag7240_miiphy_read without polling correct status!\n");
val = ag7240_reg_rd(mac, AG7240_MII_MGMT_STATUS);
ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, 0x0);
if(data != NULL)
*data = val;
return val;
}
int ag7240_enet_initialize(bd_t * bis) {
struct eth_device *dev[CFG_AG7240_NMACS];
u32 mask, mac_h, mac_l;
int i;
#ifdef AG7240_DEBUG
printf("ag7240_enet_initialize...\n");
#endif
// TODO check this register!
ar7240_reg_wr(HORNET_BOOTSTRAP_STATUS, ar7240_reg_rd(HORNET_BOOTSTRAP_STATUS) & ~HORNET_BOOTSTRAP_MDIO_SLAVE_MASK);
if (is_ar933x()) {
u32 rd = 0x0;
/*
* To get s26 out of reset, we have to...
* bit0~bit3: has to be deasserted
* bit4: has to be asserted
*/
rd = ar7240_reg_rd(AR7240_S26_CLK_CTRL_OFFSET) & ~(0x1f);
rd |= 0x10;
ar7240_reg_wr(AR7240_S26_CLK_CTRL_OFFSET, rd);
if (ar7240_reg_rd(AR7240_RESET) != 0) {
ar7240_reg_wr(AR7240_RESET, 0);
}
}
for (i = 0; i < CFG_AG7240_NMACS; i++) {
if ((dev[i] = (struct eth_device *) malloc(sizeof(struct eth_device))) == NULL) {
puts("## Error: malloc failed\n");
return 0;
}
if ((ag7240_macs[i] = (ag7240_mac_t *) malloc(sizeof(ag7240_mac_t))) == NULL) {
puts("## Error: malloc failed\n");
return 0;
}
memset(ag7240_macs[i], 0, sizeof(ag7240_macs[i]));
memset(dev[i], 0, sizeof(dev[i]));
sprintf(dev[i]->name, "eth%d", i);
ag7240_get_ethaddr(dev[i]);
ag7240_macs[i]->mac_unit = i;
ag7240_macs[i]->mac_base = i ? AR7240_GE1_BASE : AR7240_GE0_BASE;
ag7240_macs[i]->dev = dev[i];
dev[i]->iobase = 0;
dev[i]->init = ag7240_clean_rx;
dev[i]->halt = ag7240_halt;
dev[i]->send = ag7240_send;
dev[i]->recv = ag7240_recv;
dev[i]->priv = (void *) ag7240_macs[i];
}
for (i = 0; i < CFG_AG7240_NMACS; i++) {
eth_register(dev[i]);
#if(CONFIG_COMMANDS & CFG_CMD_MII)
miiphy_register(dev[i]->name, ag7240_miiphy_read, ag7240_miiphy_write);
#endif
ag7240_reg_rmw_set(ag7240_macs[i], AG7240_MAC_CFG1, AG7240_MAC_CFG1_SOFT_RST | AG7240_MAC_CFG1_RX_RST | AG7240_MAC_CFG1_TX_RST);
if (!i) {
mask = (AR7240_RESET_GE0_MAC | AR7240_RESET_GE0_PHY | AR7240_RESET_GE1_MAC | AR7240_RESET_GE1_PHY);
if (is_ar7241() || is_ar7242() || is_wasp()){
mask = mask | AR7240_RESET_GE0_MDIO | AR7240_RESET_GE1_MDIO;
}
ar7240_reg_rmw_set(AR7240_RESET, mask);
if (!is_ar933x()){
udelay(1000 * 100);
}
ar7240_reg_rmw_clear(AR7240_RESET, mask);
if (!is_ar933x()){
udelay(1000 * 100);
}
if (!is_ar933x()){
udelay(10 * 1000);
}
}
ag7240_hw_start(ag7240_macs[i]);
ag7240_setup_fifos(ag7240_macs[i]);
if (!is_ar933x()){
udelay(100 * 1000);
}
#ifdef AG7240_DEBUG
unsigned char *mac = dev[i]->enetaddr;
printf("\nInterface %s MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n", dev[i]->name, mac[0] & 0xff, mac[1] & 0xff, mac[2] & 0xff, mac[3] & 0xff, mac[4] & 0xff, mac[5] & 0xff);
#endif
mac_l = (dev[i]->enetaddr[4] << 8) | (dev[i]->enetaddr[5]);
mac_h = (dev[i]->enetaddr[0] << 24) | (dev[i]->enetaddr[1] << 16) | (dev[i]->enetaddr[2] << 8) | (dev[i]->enetaddr[3] << 0);
ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR1, mac_l);
ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR2, mac_h);
/* if using header for register configuration, we have to */
/* configure s26 register after frame transmission is enabled */
if (ag7240_macs[i]->mac_unit == 0) { /* WAN Phy */
#ifdef CONFIG_AR7242_S16_PHY
if (is_ar7242() || is_wasp()) {
athrs16_reg_init();
} else
#endif
{
#ifdef CFG_ATHRS26_PHY
#ifdef AG7240_DEBUG
printf("s26 reg init \n");
#endif
athrs26_reg_init();
#endif
#ifdef CFG_ATHRS27_PHY
#ifdef AG7240_DEBUG
printf("s27 reg init \n");
#endif
athrs27_reg_init();
#endif
#ifdef CONFIG_F1E_PHY
#ifdef AG7240_DEBUG
printf("F1Phy reg init \n");
#endif
athr_reg_init();
#endif
}
} else {
#ifdef CFG_ATHRS26_PHY
#ifdef AG7240_DEBUG
printf("athrs26_reg_init_lan\n");
#endif
athrs26_reg_init_lan();
#endif
#ifdef CFG_ATHRS27_PHY
#ifdef AG7240_DEBUG
printf("s27 reg init lan \n");
#endif
athrs27_reg_init_lan();
#endif
}
#ifdef AG7240_DEBUG
printf("ag7240_phy_setup\n");
#endif
//udelay(100*1000);
ag7240_phy_setup(ag7240_macs[i]->mac_unit);
#ifdef AG7240_DEBUG
printf("Interface %s is up\n", dev[i]->name);
#endif
}
return 1;
}
void ag7240_mii_setup(ag7240_mac_t *mac)
{
u32 mgmt_cfg_val;
u32 cpu_freq,ddr_freq,ahb_freq;
u32 check_cnt,revid_val;
if ((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & WASP_REF_CLK_25) == 0) {
#ifndef CFG_DUAL_PHY_SUPPORT
ar7240_reg_wr(AR934X_SWITCH_CLOCK_SPARE, 0x271);
#endif
} else {
ar7240_reg_wr(AR934X_SWITCH_CLOCK_SPARE, 0x570);
}
#if defined(CONFIG_AR7242_S16_PHY) || defined(CONFIG_ATHRS17_PHY)
if (is_wasp() && mac->mac_unit == 0) {
#ifdef CONFIG_AR7242_S16_PHY
printf("WASP ----> S16 PHY *\n");
#else
printf("WASP ----> S17 PHY *\n");
#endif
mgmt_cfg_val = 4;
if(mac->mac_unit == 0)
ar7240_reg_wr(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);
udelay(1000);
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
return;
}
#endif
#ifdef CFG_ATHRS27_PHY
if (is_wasp()) {
printf("WASP ----> S27 PHY \n");
mgmt_cfg_val = 2;
ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
return;
}
#endif
#ifdef CONFIG_F2E_PHY
if (is_wasp()) {
printf("WASP ----> F2 PHY *\n");
ar7240_reg_wr(AG7240_ETH_CFG, (AG7240_ETH_CFG_RMII_MASTER_MODE | AG7240_ETH_CFG_RMII_GE0
| AG7240_ETH_CFG_RMII_HISPD_GE0));
mgmt_cfg_val = 6;
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
return;
}
#endif
#if defined(CONFIG_F1E_PHY) || defined(CONFIG_VIR_PHY)
if (is_wasp()) {
#ifdef CONFIG_VIR_PHY
printf("WASP ----> VIR PHY *\n");
#else
printf("WASP ----> F1 PHY *\n");
#endif
if(mac->mac_unit == 0)
ar7240_reg_wr(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);
mgmt_cfg_val = 6;
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
return;
}
#endif
if ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR7240_REV_1_2) {
mgmt_cfg_val = 0x2;
if (mac->mac_unit == 0) {
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
}
}
else {
ar7240_sys_frequency(&cpu_freq, &ddr_freq, &ahb_freq);
switch (ahb_freq/1000000) {
case 150:
mgmt_cfg_val = 0x7;
break;
case 175:
mgmt_cfg_val = 0x5;
break;
case 200:
mgmt_cfg_val = 0x4;
break;
case 210:
mgmt_cfg_val = 0x9;
break;
case 220:
mgmt_cfg_val = 0x9;
break;
default:
mgmt_cfg_val = 0x7;
}
if ((is_ar7241() || is_ar7242())) {
/* External MII mode */
if (mac->mac_unit == 0 && is_ar7242()) {
mgmt_cfg_val = 0x6;
ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
}
/* Virian */
mgmt_cfg_val = 0x4;
ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
printf("Virian MDC CFG Value ==> %x\n",mgmt_cfg_val);
}
else if(is_ar933x()) {
//GE0 receives Rx/Tx clock, and use S26 phy
ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_MII_GE0_SLAVE);
mgmt_cfg_val = 0xF;
if (mac->mac_unit == 1) {
check_cnt = 0;
while (check_cnt++ < 10) {
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
#ifdef CFG_ATHRS26_PHY
if(athrs26_mdc_check() == 0)
break;
#endif
}
if(check_cnt == 11)
printf("%s: MDC check failed\n", __func__);
}
}
else { /* Python 1.0 & 1.1 */
if (mac->mac_unit == 0) {
check_cnt = 0;
while (check_cnt++ < 10) {
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
#ifdef CFG_ATHRS26_PHY
if(athrs26_mdc_check() == 0)
break;
#endif
}
if(check_cnt == 11)
printf("%s: MDC check failed\n", __func__);
}
}
}
}
/*
* Called in ag7240_hw_start() function
* */
void ag7240_mii_setup(ag7240_mac_t *mac) {
u32 mgmt_cfg_val;
u32 cpu_freq, ddr_freq, ahb_freq;
u32 check_cnt;
#ifdef CFG_ATHRS27_PHY
if (is_wasp()) {
printf("WASP ----> S27 PHY \n");
mgmt_cfg_val = 2;
ar7240_reg_wr(0xb8050024, 0x271); // 25MHz ref clock
//ar7240_reg_wr(0xb8050024, 0x570); // 40MHz ref clock
ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
return;
}
#endif
#ifdef CONFIG_AR7242_S16_PHY
if (is_wasp()) {
printf("WASP ----> S16 PHY *\n");
mgmt_cfg_val = 4;
if(mac->mac_unit == 0)
ar7240_reg_wr(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);
ar7240_reg_rmw_clear(AG7240_ETH_SWITCH_CLK_SPARE, (1 << 6));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
return;
}
#endif
#ifdef CONFIG_F1E_PHY
if (is_wasp()) {
printf("WASP ----> F1 PHY *\n");
mgmt_cfg_val = 6;
if(mac->mac_unit == 0)
ar7240_reg_wr(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
return;
}
#endif
if ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR7240_REV_1_2) {
mgmt_cfg_val = 0x2;
if (mac->mac_unit == 0) {
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
}
} else {
ar933x_sys_frequency(&cpu_freq, &ddr_freq, &ahb_freq);
switch (ahb_freq / 1000000) {
case 150:
mgmt_cfg_val = 0x7;
break;
case 175:
mgmt_cfg_val = 0x5;
break;
case 200:
mgmt_cfg_val = 0x4;
break;
case 210:
mgmt_cfg_val = 0x9;
break;
case 220:
mgmt_cfg_val = 0x9;
break;
default:
mgmt_cfg_val = 0x7;
}
if ((is_ar7241() || is_ar7242())) {
/* External MII mode */
if (mac->mac_unit == 0 && is_ar7242()) {
mgmt_cfg_val = 0x6;
ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
}
/* Virian */
mgmt_cfg_val = 0x4;
ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
printf("Virian MDC CFG Value ==> %x\n", mgmt_cfg_val);
} else if (is_ar933x()) {
//GE0 receives Rx/Tx clock, and use S26 phy
ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_MII_GE0_SLAVE);
mgmt_cfg_val = 0xF;
if (mac->mac_unit == 1) {
check_cnt = 0;
while (check_cnt++ < 10) {
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
#ifdef CFG_ATHRS26_PHY
if (athrs26_mdc_check() == 0) {
break;
}
#endif
}
if (check_cnt == 11) {
printf("%s: MDC check failed\n", __func__);
}
}
} else { /* Python 1.0 & 1.1 */
if (mac->mac_unit == 0) {
check_cnt = 0;
while (check_cnt++ < 10) {
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
#ifdef CFG_ATHRS26_PHY
if (athrs26_mdc_check() == 0) {
break;
}
#endif
}
if (check_cnt == 11) {
printf("%s: MDC check failed\n", __func__);
}
}
}
}
}
static int ag7240_check_link(ag7240_mac_t *mac) {
int link = 0, duplex = 0, speed = 0;
char *s;
s = getenv("stdin");
ag7240_phy_link(mac->mac_unit, &link);
ag7240_phy_duplex(mac->mac_unit, &duplex);
ag7240_phy_speed(mac->mac_unit, &speed);
mac->link = link;
if (!mac->link) {
if((s != NULL) && (strcmp(s, "nc") != 0)){
printf("Link down: %s\n", mac->dev->name);
}
return 0;
}
switch (speed) {
case _1000BASET:
ag7240_set_mac_if(mac, 1);
ag7240_reg_rmw_set(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19));
if (is_ar7242() && (mac->mac_unit == 0)) {
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x1c000000);
}
#ifdef CONFIG_F1E_PHY
if (is_wasp() && (mac->mac_unit == 0)) {
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x0e000000);
}
#else
if (is_wasp() && (mac->mac_unit == 0)) {
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x06000000);
}
#endif
break;
case _100BASET:
ag7240_set_mac_if(mac, 0);
ag7240_set_mac_speed(mac, 1);
ag7240_reg_rmw_clear(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19));
if ((is_ar7242() || is_wasp()) && (mac->mac_unit == 0)){
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x0101);
}
break;
case _10BASET:
ag7240_set_mac_if(mac, 0);
ag7240_set_mac_speed(mac, 0);
ag7240_reg_rmw_clear(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19));
if ((is_ar7242() || is_wasp()) && (mac->mac_unit == 0)){
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x1616);
}
break;
default:
if((s != NULL) && (strcmp(s, "nc") != 0)){
printf("## Error: invalid speed detected\n");
}
return 0;
}
if (mac->link && (duplex == mac->duplex) && (speed == mac->speed)){
return 1;
}
mac->duplex = duplex;
mac->speed = speed;
if((s != NULL) && (strcmp(s, "nc") != 0)){
printf("Ethernet mode (duplex/speed): %d/%d Mbps\n", duplex, speed);
}
ag7240_set_mac_duplex(mac, duplex);
return 1;
}
void
ar7240_ddr_initial_config(uint32_t refresh)
{
int ddr2 = 0,ddr_config;
int ddr_config2,ext_mod,ddr2_ext_mod;
int mod_val,mod_val_init;
#ifndef COMPRESSED_UBOOT
printf("\nsri\n");
#endif
#if 0
ar7240_reg_wr(AR7240_RESET, AR7240_RESET_DDR);
udelay(10);
#endif
ddr2 = ((ar7240_reg_rd(0xb8050020) & 0x1) == 0);
#ifdef ENABLE_DYNAMIC_CONF
if(*(volatile int *)CFG_DDR_MAGIC_F == CFG_DDR_MAGIC){
ddr_config = CFG_DDR_CONFIG_VAL_F;
ddr_config2 = CFG_DDR_CONFIG2_VAL_F;
ext_mod = CFG_DDR_EXT_MODE_VAL_F;
ddr2_ext_mod = ext_mod;
}
else
#endif
{
#ifdef CONFIG_SUPPORT_AR7241
if (is_ar7241() || is_ar7242()) {
if (ddr2) {
#ifndef COMPRESSED_UBOOT
printf("%s(%d): virian ddr2 init\n", __func__, __LINE__);
#endif /* #ifndef COMPRESSED_UBOOT */
ddr_config = CFG_7241_DDR2_CONFIG_VAL;
ddr_config2 = CFG_7241_DDR2_CONFIG2_VAL;
#if defined(ENABLE_DYNAMIC_CONF) && (defined(CONFIG_WNR2200) || defined(CONFIG_WNR2000V3))
char *s;
s = getenv("ddr_ext_mode_value");
ext_mod = s?(int)simple_strtol(s,NULL,16):CFG_DDR_EXT_MODE_VAL;
#else
ext_mod = CFG_7241_DDR2_EXT_MODE_VAL;
#endif
ddr2_ext_mod = CFG_DDR2_EXT_MODE_VAL;
mod_val_init = CFG_7241_DDR2_MODE_VAL_INIT;
mod_val = CFG_7241_DDR2_MODE_VAL;
} else {
#ifndef COMPRESSED_UBOOT
printf("%s(%d): virian ddr1 init\n", __func__, __LINE__);
#endif /* #ifndef COMPRESSED_UBOOT */
ddr_config = CFG_7241_DDR1_CONFIG_VAL;
ddr_config2 = CFG_7241_DDR1_CONFIG2_VAL;
#if defined(ENABLE_DYNAMIC_CONF) && (defined(CONFIG_WNR2200) || defined(CONFIG_WNR2000V3))
char *s;
s = getenv("ddr_ext_mode_value");
ext_mod = s?(int)simple_strtol(s,NULL,16):CFG_DDR_EXT_MODE_VAL;
#else
ext_mod = CFG_7241_DDR1_EXT_MODE_VAL;
#endif
ddr2_ext_mod = CFG_DDR2_EXT_MODE_VAL;
mod_val_init = CFG_7241_DDR1_MODE_VAL_INIT;
mod_val = CFG_7241_DDR1_MODE_VAL;
}
}
else
#endif
{
#ifndef COMPRESSED_UBOOT
printf("%s(%d): python ddr init\n", __func__, __LINE__);
#endif /* #ifndef COMPRESSED_UBOOT */
ddr_config = CFG_DDR_CONFIG_VAL;
ddr_config2 = CFG_DDR_CONFIG2_VAL;
#if (defined(CONFIG_WNR1000V2) || defined(CONFIG_WNR1100) || defined(CONFIG_WNR612)) && defined(ENABLE_DYNAMIC_CONF)
char *s;
s = getenv("ddr_ext_mode_value");
ext_mod = s?(int)simple_strtol(s,NULL,16):CFG_DDR_EXT_MODE_VAL;
#else
ext_mod = CFG_DDR_EXT_MODE_VAL;
#endif
ddr2_ext_mod = CFG_DDR2_EXT_MODE_VAL;
mod_val_init = CFG_DDR_MODE_VAL_INIT;
mod_val = CFG_DDR_MODE_VAL;
}
}
if (ddr2) {
ar7240_reg_wr_nf(0xb800008c, 0xA59);
udelay(100);
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x10);
udelay(10);
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x20);
udelay(10);
}
#if defined(CONFIG_WNR2200) || defined(CONFIG_WNR2000V3) || defined(CONFIG_AP121) || defined(CONFIG_WNR1000V4) || defined(CONFIG_HW29763847P16P64)
ar7240_reg_wr_nf(AR7240_DDR_CONFIG, ddr_config);
udelay(100);
ar7240_reg_wr_nf(AR7240_DDR_CONFIG2, ddr_config2 | 0x80);
udelay(100);
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x8);
udelay(10);
#else
else {
void pci_init_board (void)
#endif /* #ifdef COMPRESSED_UBOOT */
{
#ifdef CONFIG_AP123
return;
#else
uint32_t cmd = 0, reg_val;
//printf("%s: PCIe PLL 0x%x\n", __func__, mips3_cp0_count_read());
//printf("%s: PCIe PLL 0x%x 0xb8000008 = 0x%08x\n", __func__, mips3_cp0_count_read(), ar7240_reg_rd(0xb8040008));
pci_udelay(100000);
//count ++;
if ((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & WASP_REF_CLK_25) == 0) {
ar7240_reg_wr_nf(AR934X_PCIE_PLL_DITHER_DIV_MAX,
PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(0) |
PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(1) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x20) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0));
} else {
#ifndef COMPRESSED_UBOOT
printf("%s: PCIe PLL not set for 40MHz refclk\n", __func__);
#endif
}
ar7240_reg_rmw_set(AR7240_RESET, AR7240_RESET_PCIE); // core in reset
pci_udelay(10000);
ar7240_reg_rmw_set(AR7240_RESET, AR7240_RESET_PCIE_PHY);// phy in reset
pci_udelay(10000);
ar7240_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); // pci phy analog in reset
pci_udelay(10000);
ar7240_reg_wr(0x180f0000, 0x1ffc0); // ltssm is disabled
pci_udelay(100);
ar7240_reg_wr_nf(AR7240_PCI_LCL_RESET, 0); // End point in reset
pci_udelay(100000);
//ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE_PHY);
if ((ar7240_reg_rd(AR7240_REV_ID) & 0xf) == 0) {
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
PCIE_PLL_CONFIG_REFDIV_SET(1) |
PCIE_PLL_CONFIG_BYPASS_SET(1) |
PCIE_PLL_CONFIG_PLLPWD_SET(1));
pci_udelay(10000);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
PCIE_PLL_CONFIG_REFDIV_SET(1) |
PCIE_PLL_CONFIG_BYPASS_SET(1) |
PCIE_PLL_CONFIG_PLLPWD_SET(0));
pci_udelay(1000);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
ar7240_reg_rd(AR934X_PCIE_PLL_CONFIG) &
(~PCIE_PLL_CONFIG_BYPASS_SET(1)));
pci_udelay(1000);
} else {
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
PCIE_PLL_CONFIG_REFDIV_SET(2) |
PCIE_PLL_CONFIG_BYPASS_SET(1) |
PCIE_PLL_CONFIG_PLLPWD_SET(1));
pci_udelay(10000);
if ((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & WASP_REF_CLK_25) == 0) {
ar7240_reg_wr_nf(0xb8116c00, (0x5 << 27) | (160 << 18) | 0);
} else {
ar7240_reg_wr_nf(0xb8116c00, (0x2 << 27) | (0x28 << 18) | 0);
}
do {
ar7240_reg_wr_nf(0xb8116c04, (0x1 << 30) | (0x4 << 26) | (0x32 << 19) | (1 << 16) | (3 << 13) | (0x1e << 7));
ar7240_reg_wr_nf(0xb8116c08, (6 << 23));
pci_udelay(10000);
ar7240_reg_wr_nf(0xb8116c04, (0x1 << 30) | (0x4 << 26) | (0x32 << 19) | (3 << 13) | (0x1e << 7));
ar7240_reg_rmw_clear(KSEG1ADDR(PCIe_DPLL3_ADDRESS), PCIe_DPLL3_DO_MEAS_SET(1));
ar7240_reg_rmw_set(KSEG1ADDR(PCIe_DPLL3_ADDRESS), PCIe_DPLL3_DO_MEAS_SET(1));
ar7240_reg_wr(0xb804000c, 1 << 2);
pci_udelay(1000);
while (((cmd = ar7240_reg_rd(PCIe_DPLL4_ADDRESS)) & PCIe_DPLL4_MEAS_DONE_SET(1)) == 0) {
printf("0x%x 0x%x 0x%x\n", KSEG1ADDR(PCIe_DPLL4_ADDRESS), cmd);
pci_udelay(10);
}
{ int i; for (i = 0; i < 100; i++) udelay(10); }
#if 0
msdvc = PCIe_DPLL4_MEAN_DVC_GET(cmd);
cmd = PCIe_DPLL3_SQSUM_DVC_GET(ar7240_reg_rd(PCIe_DPLL3_ADDRESS));
if (msdvc & 0x400) msdvc = ((~msdvc & 0x7FF) + 1); /* 11 bit signed number , but not intentioanlly multiply by (-1), ASK VIPUL*/
msdvc = cmd - (msdvc *msdvc);
msdvc_sq = msdvc * msdvc;
if (cmd >= 0x40000) {
err_count++;
if (sqsum_min_fail == 0)
sqsum_min_fail = cmd;
if (cmd > sqsum_max_fail)
sqsum_max_fail = cmd;
if (cmd < sqsum_min_fail)
sqsum_min_fail = cmd;
sqsum_avg_fail = (sqsum_avg_fail - (sqsum_avg_fail / err_count)) + (cmd / err_count);
if (num_pll_loops == 0)
err_pll1++;
if (num_pll_loops == 1)
err_pll2++;
if (num_pll_loops == 2)
err_pll3++;
if (num_pll_loops == 3)
err_pll4++;
if (num_pll_loops == 4) {
err_pll5++;
break;
}
} else {
if (sqsum_min == 0)
sqsum_min = cmd;
if (cmd < sqsum_min)
sqsum_min = cmd;
if (cmd > sqsum_max)
sqsum_max = cmd;
//sqsum_avg = (sqsum_avg - (sqsum_avg / count)) + (cmd / count);
sqsum_avg += cmd;
/*msdvc calc*/
if (msdvc_min == 0) msdvc_min = msdvc;
if (msdvc < msdvc_min) msdvc_min =msdvc;
if (msdvc > msdvc_max) msdvc_max =msdvc;
msdvc_avg += msdvc;
msdvc_sq_avg += msdvc_sq;
}
num_pll_loops++;
#endif
} while ((cmd = PCIe_DPLL3_SQSUM_DVC_GET(ar7240_reg_rd(PCIe_DPLL3_ADDRESS))) >= 0x40000);
ar7240_reg_rmw_clear(AR934X_PCIE_PLL_CONFIG, PCIE_PLL_CONFIG_PLLPWD_SET(1));
pci_udelay(10000);
ar7240_reg_rmw_clear(AR934X_PCIE_PLL_CONFIG, PCIE_PLL_CONFIG_BYPASS_SET(1));
pci_udelay(10000);
/*
* PCIe Dithering configuration
*/
if (is_ar934x_12_or_later()) {
ar7240_reg_wr_nf(PCIe_DPLL2_ADDRESS,
PCIe_DPLL2_LOCAL_PLL_SET(0) |
PCIe_DPLL2_KI_SET(0x4)|
PCIe_DPLL2_KD_SET(0x40));
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG, 0x40010800);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_DITHER_DIV_MAX, 0xc013fffe);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_DITHER_DIV_MIN, 0x0013e666);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG, 0x00010800);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG, 0x00000800);
}
//run_command("md 0xb8116c00 4", 0);
}
ar7240_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); // pci phy analog out of reset
pci_udelay(10000);
ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE_PHY); // phy out of reset
pci_udelay(10000);
ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE); // core out of reset
pci_udelay(1000);
cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
PCI_COMMAND_PARITY|PCI_COMMAND_SERR|PCI_COMMAND_FAST_BACK;
ar7240_local_write_config(PCI_COMMAND, 4, cmd); // pci cmd reg init
ar7240_local_write_config(0x20, 4, 0x1ff01000); // membase setting
ar7240_local_write_config(0x24, 4, 0x1ff01000); // prefetch membase setting
if ((is_ar7241() || is_ar7242() || is_wasp())) {
ar7240_reg_wr(0x180f0000, 0x1ffc1); // ltssm enable
} else {
ar7240_reg_wr(0x180f0000, 0x1);
}
pci_udelay(100000);
ar7240_reg_wr_nf(AR7240_PCI_LCL_RESET, 4); // EP out of reset
pci_udelay(100000);
#ifdef COMPRESSED_UBOOT
pci_udelay(100);
#else
/*
* Delay increased from 100 to 1000, so as to
* get the correct status from PCI LCL RESET register
*/
pci_udelay(100000);
/*
* Check if the WLAN PCI-E H/W is present, If the
* WLAN H/W is not present, skip the PCI platform
* initialization code and return
*/
if (((ar7240_reg_rd(AR7240_PCI_LCL_RESET)) & 0x1) == 0x0) {
printf("*** Warning *** : PCIe WLAN Module not found !!!\n");
return;
}
#endif
#ifndef COMPRESSED_UBOOT
/*
* Now, configure for u-boot tools
*/
hose.first_busno = 0;
hose.last_busno = 0xff;
/* System space */
pci_set_region( &hose.regions[0],
0x80000000,
0x00000000,
32 * 1024 * 1024,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* PCI memory space */
pci_set_region( &hose.regions[1],
0x10000000,
0x10000000,
128 * 1024 * 1024,
PCI_REGION_MEM);
hose.region_count = 2;
pci_register_hose(&hose);
pci_set_ops( &hose,
pci_hose_read_config_byte_via_dword,
pci_hose_read_config_word_via_dword,
ar7240_pci_read_config,
pci_hose_write_config_byte_via_dword,
pci_hose_write_config_word_via_dword,
ar7240_pci_write_config);
#endif
plat_dev_init();
#endif // CONFIG_AP123
#ifdef COMPRESSED_UBOOT
return 0;
#endif
}
int ag7240_enet_initialize(bd_t * bis){
struct eth_device *dev[CFG_AG7240_NMACS];
u32 mask, mac_h, mac_l;
int i;
//printf("ag934x_enet_initialize...\n");
/*
if(is_ar933x() && (ar7240_reg_rd(AR7240_RESET)!=0)){
ar7240_reg_wr(AR7240_RESET,0);
}
if(is_ar933x()) //Turn on LED
ar7240_reg_wr(AR7240_GPIO_BASE + 0x28 , ar7240_reg_rd(AR7240_GPIO_BASE + 0x28) | (0xF8));
*/
for(i = 0;i < CFG_AG7240_NMACS;i++){
if((dev[i] = (struct eth_device *)malloc(sizeof(struct eth_device))) == NULL){
//puts("malloc failed\n");
return(0);
}
if((ag7240_macs[i] = (ag7240_mac_t *)malloc(sizeof(ag7240_mac_t))) == NULL){
//puts("malloc failed\n");
return(0);
}
memset(ag7240_macs[i], 0, sizeof(ag7240_macs[i]));
memset(dev[i], 0, sizeof(dev[i]));
sprintf(dev[i]->name, "eth%d", i);
ag7240_get_ethaddr(dev[i]);
ag7240_macs[i]->mac_unit = i;
ag7240_macs[i]->mac_base = i ? AR7240_GE1_BASE : AR7240_GE0_BASE ;
ag7240_macs[i]->dev = dev[i];
dev[i]->iobase = 0;
dev[i]->init = ag7240_clean_rx;
dev[i]->halt = ag7240_halt;
dev[i]->send = ag7240_send;
dev[i]->recv = ag7240_recv;
dev[i]->priv = (void *)ag7240_macs[i];
}
for(i = 0;i < CFG_AG7240_NMACS;i++){
eth_register(dev[i]);
#if(CONFIG_COMMANDS & CFG_CMD_MII)
miiphy_register(dev[i]->name, ag7240_miiphy_read, ag7240_miiphy_write);
#endif
ag7240_reg_rmw_set(ag7240_macs[i], AG7240_MAC_CFG1, AG7240_MAC_CFG1_SOFT_RST | AG7240_MAC_CFG1_RX_RST | AG7240_MAC_CFG1_TX_RST);
if(!i){
mask = (AR7240_RESET_GE0_MAC | AR7240_RESET_GE0_PHY | AR7240_RESET_GE1_MAC | AR7240_RESET_GE1_PHY);
if(is_ar7241() || is_ar7242() || is_wasp()){
mask = mask | AR7240_RESET_GE0_MDIO | AR7240_RESET_GE1_MDIO;
}
//printf(" wasp reset mask:%x \n",mask);
ar7240_reg_rmw_set(AR7240_RESET, mask);
udelay(1000 * 100);
ar7240_reg_rmw_clear(AR7240_RESET, mask);
udelay(1000 * 100);
udelay(10 * 1000);
}
ag7240_hw_start(ag7240_macs[i]);
ag7240_setup_fifos(ag7240_macs[i]);
udelay(100 * 1000);
//unsigned char *mac = dev[i]->enetaddr;
//printf("%s: %02x:%02x:%02x:%02x:%02x:%02x\n", dev[i]->name, mac[0] & 0xff, mac[1] & 0xff, mac[2] & 0xff, mac[3] & 0xff, mac[4] & 0xff, mac[5] & 0xff);
mac_l = (dev[i]->enetaddr[4] << 8) | (dev[i]->enetaddr[5]);
mac_h = (dev[i]->enetaddr[0] << 24) | (dev[i]->enetaddr[1] << 16) | (dev[i]->enetaddr[2] << 8) | (dev[i]->enetaddr[3] << 0);
ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR1, mac_l);
ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR2, mac_h);
/* if using header for register configuration, we have to */
/* configure s26 register after frame transmission is enabled */
if(ag7240_macs[i]->mac_unit == 0){ /* WAN Phy */
#ifdef CONFIG_AR7242_S16_PHY
if(is_ar7242() || is_wasp()){
athrs16_reg_init();
} else
#endif
{
#ifdef CFG_ATHRS17_PHY
athrs17_reg_init();
#endif
#ifdef CFG_ATHRS26_PHY
athrs26_reg_init();
#endif
#ifdef CFG_ATHRS27_PHY
//printf("s27 reg init \n");
athrs27_reg_init();
#endif
#ifdef CONFIG_F1E_PHY
//printf("F1Phy reg init \n");
athr_reg_init();
#endif
#ifdef CONFIG_VIR_PHY
//printf("VIRPhy reg init \n");
athr_vir_reg_init();
#endif
#ifdef CONFIG_F2E_PHY
//printf("F2Phy reg init \n");
athr_reg_init();
#endif
}
} else {
#ifdef CFG_ATHRS26_PHY
athrs26_reg_init_lan();
#endif
#ifdef CFG_ATHRS27_PHY
//printf("s27 reg init lan \n");
athrs27_reg_init_lan();
#endif
}
ag7240_phy_setup(ag7240_macs[i]->mac_unit);
//printf("%s up\n",dev[i]->name);
}
return(1);
}
void pci_init_board (void)
#endif /* #ifdef COMPRESSED_UBOOT */
{
uint32_t cmd;
ar7240_reg_rmw_clear(AR7240_RESET,AR7240_RESET_PCIE_PHY_SERIAL);
udelay(100);
ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE_PHY);
ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE);
ar7240_reg_wr_nf(AR7240_PCI_LCL_RESET, 0);
udelay(100000);
/*
* Initialize PCIE PLL and get it out of RESET
*/
ar7240_reg_wr(AR7240_PCIE_PLL_CONFIG,0x02050800);
ar7240_reg_wr(AR7240_PCIE_PLL_CONFIG,0x00050800);
udelay(100);
ar7240_reg_wr(AR7240_PCIE_PLL_CONFIG,0x00040800);
udelay(100000);
ar7240_reg_wr_nf(AR7240_PCI_LCL_RESET, 4);
udelay(100000);
cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
PCI_COMMAND_PARITY|PCI_COMMAND_SERR|PCI_COMMAND_FAST_BACK;
ar7240_local_write_config(PCI_COMMAND, 4, cmd);
ar7240_local_write_config(0x20, 4, 0x1ff01000);
ar7240_local_write_config(0x24, 4, 0x1ff01000);
if ((is_ar7241() || is_ar7242() || is_wasp())) {
ar7240_reg_wr(0x180f0000, 0x1ffc1);
} else {
ar7240_reg_wr(0x180f0000, 0x1);
}
#ifdef COMPRESSED_UBOOT
udelay(100);
#else
udelay(1000);
/*
* Check if the WLAN PCI-E H/W is present, If the
* WLAN H/W is not present, skip the PCI platform
* initialization code and return
*/
if (((ar7240_reg_rd(AR7240_PCI_LCL_RESET)) & 0x1) == 0x0) {
printf("*** Warning *** : PCIe WLAN Module not found !!!\n");
return;
}
#endif
#ifndef COMPRESSED_UBOOT
/*
* Now, configure for u-boot tools
*/
hose.first_busno = 0;
hose.last_busno = 0xff;
/* System space */
pci_set_region( &hose.regions[0],
0x80000000,
0x00000000,
32 * 1024 * 1024,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* PCI memory space */
pci_set_region( &hose.regions[1],
0x10000000,
0x10000000,
128 * 1024 * 1024,
PCI_REGION_MEM);
hose.region_count = 2;
pci_register_hose(&hose);
pci_set_ops( &hose,
pci_hose_read_config_byte_via_dword,
pci_hose_read_config_word_via_dword,
ar7240_pci_read_config,
pci_hose_write_config_byte_via_dword,
pci_hose_write_config_word_via_dword,
ar7240_pci_write_config);
#endif
plat_dev_init();
#ifdef COMPRESSED_UBOOT
return 0;
#endif
}
/*
* We want a 1:1 mapping between PCI and DDR for inbound and outbound.
* The PCI<---AHB decoding works as follows:
*
* 8 registers in the DDR unit provide software configurable 32 bit offsets
* for each of the eight 16MB PCI windows in the 128MB. The offsets will be
* added to any address in the 16MB segment before being sent to the PCI unit.
*
* Essentially for any AHB address generated by the CPU,
* 1. the MSB four bits are stripped off, [31:28],
* 2. Bit 27 is used to decide between the lower 128Mb (PCI) or the rest of
* the AHB space
* 3. Bits 26:24 are used to access one of the 8 window registers and are
* masked off.
* 4. If it is a PCI address, then the WINDOW offset in the WINDOW register
* corresponding to the next 3 bits (bit 26:24) is ADDED to the address,
* to generate the address to PCI unit.
*
* eg. CPU address = 0x100000ff
* window 0 offset = 0x10000000
* This points to lowermost 16MB window in PCI space.
* So the resulting address would be 0x000000ff+0x10000000
* = 0x100000ff
*
* eg2. CPU address = 0x120000ff
* WINDOW 2 offset = 0x12000000
* resulting address would be 0x000000ff+0x12000000
* = 0x120000ff
*
* There is no translation for inbound access (PCI device as a master)
*/
static int __init ar7240_pcibios_init(void)
{
uint32_t cmd;
#ifdef CONFIG_WASP_SUPPORT
if (is_ar9341()) {
return 0;
}
#endif
/*
* Check if the WLAN PCI-E H/W is present, If the
* WLAN H/W is not present, skip the PCI
* initialization code and just return.
*/
if (((ar7240_reg_rd(AR7240_PCI_LCL_RESET)) & 0x1) == 0x0) {
printk("***** Warning *****: PCIe WLAN H/W not found !!!\n");
return 0;
}
if ((is_ar7241() || is_ar7242()))
ar7240_reg_wr(AR7240_PCI_LCL_APP, (ar7240_reg_rd(AR7240_PCI_LCL_APP) | (0x1 << 16)));
#ifdef CONFIG_PERICOM
ar7240_reg_wr(0xb80f0000, 0x0ffc1); // Address Translation disabled
ar7240_reg_wr(0x180f0040, 0); // Enable Type 0
ar7240_reg_rd(0x14000000); // Reading the Config space of Upstream port of Switch
ar7240_reg_wr(0x1400003c, 0x400000); // Assert Reset to the Downstream ports
ar7240_reg_wr(0x1400003c, 0x0); // Deassert Reset
ar7240_reg_wr(0x14000004, 0x106);
ar7240_reg_wr(0x14000018, 0x070504); // Program the Primary Bus, Sec Bus and Subordinate Bus
ar7240_reg_wr(0x14000020, 0x1ff01000); // Memory Base and Limit
ar7240_reg_wr(0x14000024, 0x1ff01000); // Prefetch Memory Base and Limit
ar7240_reg_wr(0x140000b4, 0x0200010a); // Enable Round robin priority on the ports
ar7240_reg_wr(0x180f0040, 1); // Enable Type 1
// Configure the Pericom Switch's Downstream Port0 using Type1 Configuration
ar7240_reg_rd(0x15080000); // Reading the Config space of Downstream port0 of Switch
ar7240_reg_wr(0x15080004, 0x106); // Command register
ar7240_reg_wr(0x15080018, 0x060605); // Program the pri bus, sec bus and subordinate bus
ar7240_reg_wr(0x15080020, 0x11f01000); // Memory base and limit
ar7240_reg_wr(0x15080024, 0x11f01000);
// Configure the Pericom Switch's Downstream Port1 using Type1 Configuration
ar7240_reg_rd(0x15100000); // Reading the Config space of Downstream port1 of Switch
ar7240_reg_wr(0x15100004, 0x106);
ar7240_reg_wr(0x15100018, 0x070705);
ar7240_reg_wr(0x15100020, 0x13f01200);
ar7240_reg_wr(0x15100024, 0x13f01200);
ar7240_reg_wr(0xb80f0000, 0x1ffc1); // Address Translation enabled
#endif /* CONFIG_PERICOM */
printk("PCI init:%s\n", __func__);
#ifndef CONFIG_PCI_INIT_IN_MONITOR
cmd = PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER |
PCI_COMMAND_INVALIDATE |
PCI_COMMAND_PARITY |
PCI_COMMAND_SERR |
PCI_COMMAND_FAST_BACK;
printk("%s(%d): PCI CMD write: 0x%x\n", __func__, __LINE__, cmd);
ar7240_local_write_config(PCI_COMMAND, 4, cmd);
/*
* clear any lingering errors and register core error IRQ
*/
#if 0
ar7240_check_error(0);
#endif
# if !defined(CONFIG_PERICOM)
ar7240_pci_ops.write(NULL, 0, PCI_COMMAND, 4, cmd);
# endif /* CONFIG_PERICOM */
#endif
#ifdef CONFIG_PERICOM
#define ar7240_udelay(us) do { \
extern uint32_t ar7240_cpu_freq; \
volatile register int N = (ar7240_cpu_freq / 1000000) * (us); \
while (--N > 0); \
} while(0)
/* For Pericom -> Merlin link availability */
ar7240_udelay(600);
cmd = PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER |
PCI_COMMAND_SERR;
printk("%s: cmd = 0x%x\n", __func__, cmd);
ar7240_pci_ops.write(2, 0, PCI_COMMAND, 4, cmd);
ar7240_pci_ops.write(1, 0, PCI_COMMAND, 4, cmd);
register_pci_controller(&ar7240_pci_controller1);
register_pci_controller(&ar7240_pci_controller2);
#else
register_pci_controller(&ar7240_pci_controller);
#endif /* CONFIG_PERICOM */
return 0;
}
